Innovative Programming Approaches to Address Z-Interference in High-Density 3D NAND Flash Memory

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

In this paper, the authors deal with the Z-interference from several aspects including programming sequence, memory hole shape, and bit line voltage.

However, the simulation design, condition, and results are not presented very clearly. Thus, this paper needs a major revision to fix the following issues and answer the following questions:

1. fig 1 a. The authors should not simply copy the figure from other papers without explaining the terminology.  For example, what do HB and P1 mean here? Why they can represent the Z-interference?

2. fig 2 (a) & (b). What does "programming environments at the bottom WL and top WL" mean? Why the victim WL doesn't have any charge in the CTN layer? Is it in the erased state? If so, why would the author skip the victim WL and program the attacker WL first?

3. Fig 2C. In ref[6], the interference is quantified statistically. After programming the attacker WL, the Vth distribution of victim WL becomes wider, and high-bound shifts up.  So for fig2c, how many cells did the author simulate? Do they all shift the same amount or does the width of their distribution also change? It would be better if the author can show a figure like fig3 in ref[6]

4. Line 126, "with WL2 and WL4 sequentially programmed to 17V". What does "programmed to 17V" mean here? The Vth becomes 17V or the cell is programmed with a 17V voltage?

5. Table 1 mentions that the Read Voltage is -6~5V.  Why is the lower bound so negative? How many states does 1 cell have and what is the Vth position for each state?

6. Why the SL voltage is higher than BL when doing the program?

7. Line 175, should be figure 4c

8. fig6 c, the tunnel oxide should be between the CTN and channel. And CD= 80nm has the smallest electrical field, which does not agree with what they claim

9. Section 5 proposes to decrease BL voltage up to 40% to reduce z-interference. This would greatly reduce the BL current during the verification and cause incorrect verification results. How are the authors planning to solve this issue?

10. fig 3 a. From the plot, all the voltage drops along the channel appear on the attacker and victim cells.  How can this be true?  All the other cells have zero resistance?

Author Response

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Author Response File: Author Response.docx

Reviewer 2 Report

Comments and Suggestions for Authors

The paper describes that the demand for NAND flash memory is increasing due to its superior performance, lower power consumption, and enhanced reliability compared to traditional HDDs. Increasing bit density in 3D NAND leads to significant Z-interference, which affects cell distribution and reliability. Previous studies show that programming from the top word line (WL) to the bottom WL reduces Z-interference compared to the bottom-to-top approach. This study found that Z-interference variations increase with more electrons programmed into WLs due to increased resistance in the poly-Si channel, and proposed adjusting bit line biases during verification operations to enhance performance and reliability. Simulations confirmed that programming from top to bottom WLs mitigates Z-interference more effectively.

Overall, the results are technically sound, and the drawn conclusion is well supported by the simulated results. The referee recommends this manuscript for publication as it is.

Author Response

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Author Response File: Author Response.docx

Reviewer 3 Report

Comments and Suggestions for Authors

There are many terms that are not defined, for example ON molds. There are too many places where I can't figure out what was being modeled and on what devices there were measurements. The subject is very important but I can't understand what is going on.

Comments on the Quality of English Language

The English language is also not completely understandable. Maybe mostly because of the undefined terms but that should also be improved.

Author Response

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Author Response File: Author Response.docx

Round 2

Reviewer 1 Report

Comments and Suggestions for Authors

The author has answered the questions to my satisfaction.