Fully Tunable Analog Biquadratic Filter for Low-Power Auditory Signal Processing in CMOS Technologies

Abstract

A novel Gm-C structure of a second-order continuous-time filter is proposed that allows for the independent control of the filter’s natural frequency (ω₀) and quality factor (Q). The structure consists of two capacitors and four transconductors. Two transconductors together with the capacitors form a lossless second-order circuit with tunable ω₀. The other two transconductors form a variable gain amplifier (VGA) which realizes an adjustable loss and thereby adjustable Q. The proposed solution can be used to implement low-voltage and low-power tunable front-end filter banks for fully integrated CMOS cochlear implants and edge intelligence accelerators. An example filter bank powered by 0.5 V and consuming 40 nW of power per single filter is designed and simulated using a 180 nm CMOS process. Circuitries for the adaptive control of transistor bias at a reduced supply voltage are proposed. The ω₀ and Q control circuitries are also proposed: a delay-locked loop (DLL)-based system for fine ω₀ tuning and a binary-weighted current mirror for Q adjustment. The proposed solution allows for the independent regulation of ω₀ and Q within the ranges of 0.25–8 kHz and 1–14, respectively, with a relative tolerance of up to 5% across a filter bank.

1. Introduction

The natural auditory process takes place, in simple words, in three stages: the conversion of a mechanical sound wave to an electrical signal, the decomposition of the wide sound spectrum to narrower bands, and neural processing [1]. This natural scheme is energy- and computationally efficient and is exploited in bio-inspired electronic devices such as hearing aids, cochlear prosthesis implants [2,3,4,5,6,7], and edge AI accelerators [8,9,10,11,12,13,14]. In these devices, the sound wave is converted to a voltage signal by a MEMS transducer and then applied to a set of band-selective filters which divide the sound spectrum into a number of adjacent channels. The channel signals are then shaped and converted into pulses that stimulate the patient’s auditory nerves or drive artificial neural networks in edge devices.

The filter set, referred to as a filter bank, typically contains up to sixteen filters with different frequency and selectivity [15,16]. The parameters are set individually to each filter in a bank depending on the content and dynamics of sound, patient characteristics, etc. Commercial solutions widely use digital filters because their characteristics are practically insensitive to process, voltage, and temperature (PVT) variations. However, research on analog filter banks is still being carried out worldwide [5,6,7,9,10,11,12,13,14,17,18,19,20,21,22,23,24], and in recent years, several solutions have been reported with very competitive performance in terms of power consumption, e.g., [9,10,11,12,13,14]. Thus, analog filters can be energy-efficient, but their limited tunability, relatively high sensitivity to technological imperfections, and limited dynamics at low supply voltage are still a challenge for designers. A supply voltage of, e.g., 0.5–0.6 V [7,10,11,19,22] means in practice that MOS transistors are biased slightly above the triode region. As a consequence, the transistor output resistance is reduced, which limits a filter selectivity (a filter quality factor). Thus, at low supply voltages, additional control circuits are necessary to prevent the transistors from entering the triode region. The tunability problem is related to the fact that known topologies of continuous-time filters [23] feature a not fully independent (separated) control of the filter frequency and quality factor [24]. This fact complicates the tuning of a whole filter bank and makes it more difficult to control the filter characteristics under PVT variations.

The continuous-time filter presented in this paper addresses the requirements of full tunability and low-voltage operation. The solution exploits the new proposed G_m-C schematic of a biquadratic filter with the separate control of the natural frequency (ω₀) and quality (Q) factor. The following sections present the concept, theoretical analysis, transistor-level schematic, and simulation results of the filter designed in the X-Fab 180 nm CMOS process, together with a DLL-based frequency tuning system and circuits controlling the bias and threshold voltage of transistors. An example filter bank is also presented.

2. Filter

Figure 1a shows the G_m-C topology of the proposed filter. The transconductance amplifiers G_m1 and G_m2 together with the capacitors C₁ and C₂ are a second-order, lowpass, and lossless circuit with a natural (resonance) frequency ω₀ [24]. The loss is introduced to the circuit by a negative feedback loop established on the transconductors G_m3 and G_m4.

The input AC voltage V_in is applied to the filter with respect to a common (DC) potential V_cm. The filter’s main output terminal is V_out. The filter’s AC transmittance is

$$H\left(j\omega \right)={\displaystyle \frac{V_{out}\left(j\omega \right)}{V_{in}\left(j\omega \right)}}={\displaystyle \frac{{\omega }_0^2}{-{\omega }^2+j\omega \frac{{\omega }_0}{Q}+{\omega }_0^2}}$$

(1)

where

$${\omega }_0=\sqrt{{\displaystyle \frac{G_{m1}{G}_{m2}}{C_1{C}_2}}},\hspace{1em}Q={\displaystyle \frac{G_{m4}}{G_{m3}}}\cdot \sqrt{{\displaystyle \frac{G_{m1}{C}_2}{G_{m2}{C}_1}}}$$

(2)

To simplify the filter design, G_m1 and G_m2 as well as C₁ and C₂ can be assumed to be equal, i.e., G_m1 = G_m2 = G_m1,2, and C₁ = C₂ = C_1,2. With these assumptions, (2) simplifies to

$${\omega }_0={\displaystyle \frac{G_{m1,2}}{C_{1,2}}},\hspace{1em}Q={\displaystyle \frac{G_{m4}}{G_{m3}}}$$

(3)

The CMOS realization of the G_m-C structure is shown in Figure 2a. The transconductors have an identical topology composed of a differential pair (M₁, M₂) loaded with a current mirror (M₃, M₄). The consecutive differential pairs are biased with the currents I_B1 to I_B4 generated by the transistors M_B1 to M_B4. The transistors M₅, M₆, and additional capacitors of 20 pF over M₅ compose the DC voltage shifters to increase the drain-source voltage of the M₂ transistors [23].

The transconductance of the i-th (i = 1…4) transconductor, G_mi, is equal to the transconductance of the transistors M₁ and M₂ (g_m1 = g_m2 = g_m1,2) in the respective differential pair, i.e., G_mi = (g_m1,2)_i. M₁ and M₂ operate in saturation and weak inversion regions; thus,

$$G_{mi}={\left(g_{m1,2}\right)}_i\cong {\displaystyle \frac{I_{Bi}}{2n{V}_t}}$$

(4)

where i = 1…4, V_t = kT/q is the thermal voltage, and n is a technology-dependent parameter [21,22].

The bias currents I_B1 and I_B2 are equal (I_B1 = I_B2 = I_B1,2), so the natural frequency and quality factor of the filter can be expressed as follows

$${\omega }_0={\displaystyle \frac{G_{m1,2}}{C_{1,2}}}\cong {\displaystyle \frac{I_{B1,2}}{2n{V}_t{C}_{1,2}}},\hspace{1em}Q={\displaystyle \frac{G_{m4}}{G_{m3}}}\cong {\displaystyle \frac{I_{B4}}{I_{B3}}}$$

(5)

As indicated by (5), Q is determined by the ratio of the bias currents I_B4 and I_B3. Therefore, Q can be adjusted by means of a scalable (programmable) current mirror shown in Figure 2b where a current ratio, once programmed, does not change with PVT. However, ω₀ depends on the absolute values of the parameters I_B1,2, n, and V_t, so it varies with process and temperature, and thus, a tuning system based on a PLL or DLL is necessary.

It is worth noting that the filter operates in a unity gain buffer configuration [25]. The filter is covered with a global negative feedback loop (established by connecting a V_out terminal to an inverting input of the amplifier G_m1), which forces V_out to follow V_in at low frequencies. As a result, the filter gain at low frequencies is 1 V/V regardless of mismatch and PVT variations. Note also that at the additional output, V_out,norm, the filter peak gain is unity, as the graph in Figure 1b shows.

The detailed data on the transistor sizes and bias conditions are given in

Table 1. DC operating point simulated at the following: V_dd = 0.5 V, V_cm = 0.4V_dd, V_body = V_dd/3, I_B1 = I_B2 = 10 nA, I_B3 = I_B4 = 30 nA, and T = 27 °C. Nominal corner.

Transistor 1	Size [µm/µm]	IDS [nA]	gm [nS]	|VDS| [mV]	|VDSsat| [mV]
M1	2 × 10/2	5 (20 2)	154 (425 2)	160 (155 2)	47 (47.5 2)
M2	2 × 10/2	5 (20 2)	154 (425 2)	172 (202 2)	47 (47.5 2)
M3	1/2	5 (20 2)	129 (342 2)	182 (217 2)	35 (37 2)
M4	1/2	5 (20 2)	129 (342 2)	170 (170 2)	35 (37 2)
M5	40/0.5	0.25	8.5	200	44
M6	10/6	0.25	8.2	200	48
MB1,2	2 × 10/4	10	282	157	49
MB3*	20 × 1/4	30	740	128	47.5
MB4	20 × 1/4	30	740	127	47.5

¹ The nominal threshold voltages of the transistors are V_Tn = 0.34 V and V_Tp = −0.39 V. ² In the transconductors G_m3 and G_m4.

.

2.1. Effect of Reduced Resistance

With a V_dd of 0.5 V, the transistor drain-source voltages (V_DS) are significantly reduced, so they are only slightly above saturation voltages (V_DSsat). According to detailed data in Table 1, the saturation margin |V_DS| − |V_DSsat| is 80–150 mV across all transistors. The low V_DS voltages result in the reduced output resistance (r_ds) of the transistors. E.g., the output resistance of M₂ is r_ds2 = 980 MΩ at V_DS = 170 mV and would be 1.5 GΩ when assuming V_DS = 270 mV. The reduced transistor resistance causes the actual Q value to be smaller than its ideal value given by (3).

Including the output resistances, the actual ω₀ and Q are

$${\omega }_0={\displaystyle \frac{G_{m1,2}}{C_{1,2}}}\sqrt{1+{\displaystyle \frac{k}{G_{m1,2}{R}_{o1,2}}}+{\left({\displaystyle \frac{1}{G_{m1,2}{R}_{o1,2}}}\right)}^2}\cong {\displaystyle \frac{G_{m1,2}}{C_{1,2}}}$$

(6)

$$Q={\displaystyle \frac{1}{\frac{2}{G_{m1,2}{R}_{o1,2}}+k}}\sqrt{1+{\displaystyle \frac{k}{G_{m1,2}{R}_{o1,2}}}+{\left({\displaystyle \frac{1}{G_{m1,2}{R}_{o1,2}}}\right)}^2}\cong {\displaystyle \frac{1}{\frac{2}{G_{m1,2}{R}_{o1,2}}+k}}$$

(7)

where R_o1,2 = R_o1 = R_o2 = r_ds2 ‖ r_ds4 is the output resistance of the transconductors G_m1 and G_m2, and k is the voltage gain of the VGA,

$$k={\displaystyle \frac{V_{out,norm}}{V_{out}}}={\displaystyle \frac{G_{m3}}{G_{m4}+1/R_{o3}+1/R_{o4}}}$$

(8)

Since the transconductor’s gain (G_m1,2R_o1,2) remains approximately constant and equal to G_m1,2R_o1,2 ≈ 100 over a wide range of I_B1,2, the actual ω₀ is practically equal to its ideal value (3), as indicated by (6). On the other hand, the finite G_m1,2R_o1,2 ≈ 100 reduces Q by 10–30% with respect to its ideal value (3), i.e., Q_actual = 0.7(G_m4/G_m3) for high Q values, and Q_actual = 0.9(G_m4/G_m3) for low Q. Figure 3 presents the simulated filter characteristics where I_B1,2 is set to 5, 10, and 20 nA (the ω₀ adjustment), and I_B4/I_B3 is programmed as 2, 4, 10, and 20 (the Q adjustment). The resulting Q values are reduced by 15–35% with respect to the I_B4/I_B3 ratios, which is caused by the reduced resistances, as mentioned, and in addition by the inequality G_m4/G_m3 ≅ I_B4/I_B3. However, the Q values are well repeatable at different ω₀.

2.2. Bias and Threshold Voltage Control

Due to the low supply voltage, the threshold voltages of the selected transistors are reduced using the body effect. Thus, the bodies of the n-channel devices (M₃, M₄) are connected to the higher potentials at their gates (n-channel transistors on insulated p-wells, available in the X-Fab process, are used). The bodies of the p-channel pairs (M₁, M₂) are connected to the low reference potential V_body. The V_body is regulated depending on the supply voltages V_dd to prevent the forward biasing of the body-source (p-n) junctions in M₁ and M₂. The common potential V_cm is also regulated so that the transistor drain-source voltages (V_DS) are maximized. The simple and effective control scheme with V_body = V_dd/3 and V_cm = 0.4∙V_dd is used in this design. The V_cm and V_body are generated by the active dividers, shown in Figure 2c, that have simple topology and are immune to PVT variations. With this adaptive bias, the transistors are kept in saturation for a wide range of V_dd, from 1.8 V down to 0.4 V. Unfortunately, the simple dividers in Figure 2c transmit AC noise from the V_dd line to the V_body and V_cm lines, which reduces the power supply rejection ratio (PSRR) of the entire filter. However, additional grounded capacitors connected to the V_body and V_cm lines effectively reduce the V_dd noise. Simulations show that the additional capacitors of about 25 pF result in a PSRR of 72 dB and 51 dB at 10 Hz and 1 kHz, respectively (the mismatch of the differential pairs and current mirrors was included in the PSSR simulations). The grounded capacitors can be made from n-channel transistors, as shown in Figure 2c.

3. Frequency Tuning System

Due to PVT variations, continuous-time filters require an automatic frequency tuning system. The most common way to tune Gm-C filters is through a master–slave structure [26,27,28,29,30]. This approach requires a good match between master and slave circuits. To achieve the best match, the proposed tuning system, shown in Figure 4, uses a copy of one of the filters from the filter bank as the master circuit.

The system in Figure 4 is a typical delay-locked loop which utilizes the fact that biquadratic lowpass filters have a phase shift of −90° (−π/2) at ω₀. Thus, the reference sine signal (V_gen) with a frequency of ω_gen is transmitted along two paths: the reference and filter paths. If the signal after passing through the (master) filter is delayed exactly by 90° with respect to the reference path, this means that the natural frequency of the (master) filter is equal to the reference frequency, i.e., ω₀ = ω_gen. If the 90° shift remains constant, then the XOR gate generates a square wave with a constant duty cycle of exactly 50%. As a result, the charge pump equally charges and discharges its capacitor, and consequently, a voltage on the tuning signal line remains constant.

The amplitude of the input reference sine is limited by the dynamics of the filter and is V_gen = 20–50 mV_pp for the filter with Q = 1 and V_dd = 0.5 V. The phase detector, based on a simple digital XOR gate, requires high amplitude signals. Therefore, weak sine signals are amplified by the zero-cross detectors, which convert them to square waves with a rail-to-rail amplitude. The correct system operation requires the cross-detectors to be insensitive to the DC levels at their inputs. Thus, a solution with a decoupling capacitor is used [29], whose schematic is shown in Figure 5a. Other sub-blocks of the tuning system are depicted in Figure 5b–d.

The source followers (SFs) use p-channel transistors biased with 20 nA currents (Figure 5b). The SFs have their threshold voltages reduced by means of the body effect (V_body), resulting in a gain that is not unity. However, both SFs are identical, and therefore, their non-unity gain does not affect the phase shift detection process. The charge pump (Figure 5c) is a bidirectional current source (I_out) controlled by voltage (V_in). Thus, I_out = I_ref at V_in = L (low state), and I_out = −I_ref at V_in = H (high state). Additional capacitors, made of transistors 20 µm wide and 10 µm long (20/10), reduce glitches in the output current caused by commutation. The XOR gate (Figure 5d) is a traditional low-voltage solution with a transmission gate. The transistor body terminals not shown explicitly in the schematics in Figure 5a–d are connected to the V_dd and ground potentials for the p- and n-channel transistors, respectively.

All sub-blocks of the tuning system, including the master filter, operate with the same supply voltage, V_dd = 0.5 V. Assuming an external reference generator, the power consumption of the tuning system is 80 nW, and the occupied silicon area is smaller than two filters in a filter bank.

The master filter is the filter of Figure 2 with C_1,2 = 24 pF and Q = 1. In the ideal case, i.e., no PVT variations, the natural frequency of the master filter is ω₀ = 1 kHz at I_B1,2 = 10 nA and T = 27 °C, as shown in Figure 3. Under PVT variations, the ω₀ changes substantially, from about 400 Hz to 1.2 kHz (changes in the filter quality factor are negligible), as shown in Figure 6a where the following variations are assumed: (P)process across five typical corners, supply (V)voltage from 450 to 550 mV, and (T)temperature from 0 to 50 °C. The tuning system with ω_gen = 1 kHz effectively stabilizes the filter characteristics. The resulting ω₀ deviates by ±2% from 1 kHz, as visible in Figure 6b (note that the tuning system is also under PVT variations).

4. Filter Bank

Table 2. Filter bank example.

ω0 (Hz)	254	320	403	508	640	806	1015	1280	1612	2031	2560	3225	4063	5120	6450	8127
IB1,2	10 nA
C1,2 (pF)	94.19	74.56	59.17	46.97	37.28	29.58	23.48	18.64	14.79	11.74	9.32	7.39	5.87	4.66	3.69	2.93
Power	16∙40 nW at Q = 1 (IB3 = 30 nA, IB4 = 30 nA)
	16∙27 nW at Q = 10 (IB3 = 3 nA, IB4 = 30 nA)

shows an example of 16 filters scaled from 250 Hz to 8 kHz.

The bias current I_B1,2 can be the same for all channels, which simplifies the biasing, scaling, and tuning of the entire bank. The frequencies of the individual channels are then obtained simply by scaling the capacitance C_1,2. Thanks to this, relations between the channels’ frequencies are relatively lowly sensitive to PVT variations. Mismatch, though, affects the bank characteristics, as shown in Figure 7 (for better visualization, six filters selected of the sixteen are plotted). The 1-sigma spreads in ω₀ and Q are 2.2% and 4.4%, respectively, across the entire bank.

The power consumption of the whole bank depends on the programmed value of Q. Assuming the same Q in all channels, the 16-filter bank consumes 16∙27 = 432 nW at Q = 10 and 16∙40 = 640 nW at Q = 1. The lower power consumption can be achieved by reducing the filter bias currents. Unfortunately, lower currents mean larger mismatches between transistor transconductances [31,32] and thus greater spreads in ω₀ and Q.

The typical noise of the individual filter is 18–33 µV_RMS, when referred to the filter input and integrated over the filter band. The total harmonic distortion (THD) parameter is 1% with the input sine excitation with an amplitude of 72 mV_RMS and a frequency of ω₀/5. The 1 dB input-referred compression point is –13.82 dBm (45.5 mV_RMS) with the excitation at a frequency close to ω₀. Thus, the filter dynamics are 66 dB and 62 dB regarding the 1% THD and 1 dB compression point, respectively.

The silicon area occupied by the filters is determined by the area of their capacitors [22,24,25]. E.g., the filter with ω₀ = 1.015 kHz contains two capacitors of 23.48 pF and additionally, three capacitors at M₅ transistors of 20 pF, each. Assuming typical double MIM capacitors of 2.2 fF/µm², the filter area is 48,500 µm² (221 µm × 221 µm). However, using triple-high-capacitance MIMs of 7 fF/µm², also available in the X-Fab process, the filter area reduces threefold, to 15,300 µm² (124 µm × 124 µm).

5. Discussion

Table 3. Continuous-time filter banks published in the last ten years.

Parameter	2014, [17]	2016, [19]	2016, [7]	2017, [20]	2019, [10]	2021, [11]	2021, [5]	2024, [22]	This Work (Simulated)
Application	cochlea	edge	cochlea	edge	edge	edge	cochlea	cochlea	cochlea
Process, nm	350	90	180	350	180	65	180	180	180
Supply, V	3.3	0.5	0.5	2.5	0.6	0.6	1.0	0.5	0.5
Filter type	LPF OTA-C	BPF OTA-C	BPF SF-based	BPF OTA-C	BPF SSF-based	BPF FVF-based	BPF OTA-C	LPF Buffer-based	LPF OTA-C
Bank	64	16	64	12	16	16	12 1	5 2	16
Range, kHz	0.1–20	0.075–5	0.008–20	0.1–5	0.1–5	0.1–5	0.085–6.5	0.5–8	0.3–10
Q	5-bit control	1.3	1.3–39	2	2	2	1–3.7	2–11	1–14
Bank power consumpt.	mW-range	0.3 nW @75 Hz 20 nW @5 kHz	<55/2 µW	150 µW	61.3 nW	14 nW	13.2 nW @950 Hz	2.2–52 nW @1 kHz	640 nW @Q = 1 432 nW @Q = 10
S/N, dB	36–52	40–45	40–55	-	55	-	52	59	62

¹ The simulation results from [6]. ² Simulated.

presents a brief review of the continuous-time filters for auditory and edge devices, published across the last decade. Edge devices typically need filters with a constant Q parameter of low value, e.g., Q = 1.3 [19] or Q = 2 [10,11,20]. Filters with a fixed Q can have simplified, transistorized topology and therefore consume relatively low power, even several nanowatts per a whole filter bank [11]. On the other hand, cochlear implants require filters with precisely controlled frequency, bandwidth, and gain, due to individual patient characteristics [5,7,17,22]. Thus, cochlea-intended filters have more complicated topology and higher power consumption compared to edge filters.

The filter proposed in this work consumes less power than the other cochlea-dedicated filters [5,7,17,22] but still more compared to the simple filters in the edge accelerators [10,11,19,20]. Most of the filter power (75%) is dissipated in the VGA used to adjust Q. Assuming a fixed Q, e.g., 2, the VGA is not needed, and thus, the power of the filter bank can be reduced from 640 nW to 170 nW.

To reduce power consumption, supply voltages of filter banks are reduced when compared to the nominal voltages specified for the CMOS processes in which the filter banks were made. E.g., the filter bank of [20] was developed in a 3.3 V process and is supplied with a 2.5 V voltage. Similarly, the filters developed in 1.8 V processes operate at a supply voltage reduced to 1 V [5], 0.6 V [10], and 0.5 V [7,22], [this work]. Also, the works [19] and [11], made in 1 V processes, use 0.5 and 0.6 V supplies, respectively. In this regard, a typical practical limit of an analog filter supply voltage is about 0.5 V considering many CMOS processes. This practical limit applies to the analog continuous-time filters as well as discrete-time, switched-capacitor ones [12,13,14] (not included in Table 3). A further reduction in a supply voltage is, however, possible through a further reduction in transistor threshold voltages, to below 200 mV. Unfortunately, a significant increase in mismatch and noise is observed at such low threshold voltages, so more sophisticated bias control and tuning systems, based on digital circuits, are required.

6. Conclusions

The novel transconductance-C structure of a lowpass second-order filter with the separate control of the natural frequency and quality factor was proposed. The feasibility of implementing the proposed filter structure in 180 nm X-Fab CMOS technology at a significantly reduced supply voltage was investigated. The advantage of this technology, i.e., the ability to control the body potentials of both p-channel and n-channel transistors (and thus the ability to reduce and control the threshold voltages in both types of transistors), was exploited in order to achieve an optimal operating point at a 0.5 V supply. The impacts of the supply voltage noise, temperature changes, and technological imperfections on the filter’s performance were carefully analyzed. A low-voltage tuning system with a phase detector to stabilize the filter natural frequency was also proposed.