An Enhanced Six-Turn Multilayer Planar Inductor Interleaved Winding Design for LLC Resonant Converters with Low Current Ringing

Abstract

Planar magnetic components have been widely used in high-density power converters and are suitable for various topologies. The application of planar inductors in LLC resonant converters can lead to parasitic capacitance, which causes current ringing and results in EMI issues. To mitigate the impact of current ringing, the parasitic capacitance of the planar inductor needs to be reduced. This paper proposes a new six-turn interleaved winding design. Compared to the previous four-turn interleaved winding design, it maintains low parasitic capacitance while positioning both the input and output terminals of the inductor on the outer turn, further enhancing the integration of high-density power converters. The parasitic capacitance was calculated using theoretical methods and verified through finite element simulations. Experimental validation was conducted using an LLC resonant converter test platform. Compared to the previous four-turn interleaved winding design, the new six-turn interleaved winding design satisfies both the input and output terminals, using an outer turn configuration. Additionally, the new design exhibits reduced parasitic capacitance and is suitable for use in LLC resonant converters, where it also minimizes current ringing.

1. Introduction

To enhance the power density of converters, the use of planar magnetic components significantly reduces the volume of these components in high-density power supplies. Through planar winding design, the winding volume of magnetic components is substantially reduced, resulting in increased power density for the converter. In various industrial applications, planar magnetic components have been widely used in different topologies, achieving high-frequency operation and high efficiency for converters. Planar magnetic components have been extensively applied in various converters. Refs. [1,2,3] utilized LLC resonant topology and employed planar transformers and planar inductors to achieve high-density power converters. For gate-driver power supplies, Ref. [4] designed planar transformers, which were applied in half-bridge converters, active-clamp converters, and inductorless DC–DC converters, achieving high-efficiency energy conversion. Therefore, planar magnetic components have been widely used in converters with different topologies.

Simultaneously, reducing noise sources within the power supply is a crucial design consideration. Minimizing noise is key to reducing electromagnetic interference (EMI). Decreasing internal noise sources in high-density power supply designs is particularly important. Refs. [5,6,7,8] explained that reducing noise was the key to improving EMI design. For power converters, reducing high-frequency current noise is an important means to meet stringent EMI standards. Ref. [9] analyzed how the parasitic capacitance of inductors provided a conduction path for high-frequency current noise. By analyzing the changes in impedance caused by the addition of parasitic capacitance in the circuit, it was concluded that reducing the parasitic capacitance of inductors was a crucial method to reduce high-frequency current noise, helping power converters meet stringent EMI requirements. Another important method for reducing noise is to change the noise conduction path to cancel out the noise. Based on this design concept, references [10,11] applied the winding cancellation technique in the design of planar transformers, which reduced common-mode noise caused by the large parasitic capacitance of planar windings in the converter. Ref. [12] divided a single resonant inductor winding into two windings, forming a common-mode inductor to eliminate common-mode noise in LLC resonant converters. Furthermore, based on the split winding design, refs. [13,14] designed planar transformers with symmetrical primary windings to reduce common-mode noise and verified that reducing common-mode noise helped meet EMI requirements. Addressing the current ringing issue in dual-active bridge converters caused by the parasitic capacitance of inductors, refs. [15,16] analyzed the impact of inductor parasitic capacitance on converter impedance. Therefore, reducing the parasitic capacitance of inductors has been effective in reducing current ringing in dual-active bridge converters. Additionally, Ref. [17] analyzed the effectiveness of reducing inductor parasitic capacitance in lowering current ringing in LLC resonant converters and verified this through experiments. For dual-active bridge converters, Ref. [18] optimized circuit parameters to reduce current ringing, but this method was only applicable to dual-active bridge converters and involved complex calculations. In a summary of the previous research [19] regarding power converters, reducing the parasitic capacitance of the inductor and altering the noise conduction path to counteract noise were the main methods to reduce internal noise in the converter and ensure the converter met stringent EMI standards. In addition to other methods for reducing current ripple, refs. [20,21] proposed a technique that involved operating the inductor in a saturated state to decrease current ripple. However, this method is suitable for converters with lower switching frequencies. Since LLC resonant converters typically operate at frequencies around 100 kHz or even higher, this approach is not applicable in such cases.

In order to reduce the parasitic capacitance of the inductor, the inductor winding design needed to be optimized. Ref. [22] conducted a detailed analysis of the parasitic capacitance of the inductor and optimized the winding design. For planar inductor winding design, ref. [23] compared and calculated three different winding methods: outer connection, intermediate connection, and alternating-layers connection. Experimental validation was also performed. Through comparison, it was found that the alternating-layers connection had the lowest parasitic capacitance among the planar winding designs, but the design could not be directly applied to inductor design for power converters. Ref. [24] further analyzed the parasitic capacitance caused by planar inductor winding design and reduced the parasitic capacitance of the inductor through series and parallel combinations of different windings. The drawback of this method was that it required multiple windings to be combined, increasing the size of the planar inductor. In Ref. [17], an interleaved winding design was applied to reduce the parasitic capacitance of the resonant inductor in comparison to the traditional winding design, thereby reducing current ringing in the LLC resonant converter. However, the output terminal of the winding was on the inner turn. The disadvantage of this design was that it was not conducive to integrating the planar inductor winding with the entire converter on a single PCB. Further design improvements were needed to place both the input and output terminals on the outer turn to better meet the requirements of high-power density converter design.

Based on the current interleaved winding design scheme, we aimed to further improve the winding design of the resonant inductor in the LLC resonant converter. A new winding structure based on the interleaved winding design is proposed. The contents of this paper are arranged as follows: In Section 2, the proposed new design is compared with the previous interleaved winding design, with a detailed introduction and theoretical calculations. Section 3 reports the electromagnetic finite element simulations of the two different interleaved winding designs, which were conducted to verify the calculation results. Section 4 describes the experimental validation of the two different interleaved winding designs. Section 5 summarizes the paper.

2. Theoretical Calculation of Interleaved Windings

To move the winding output terminal from the inner turn to the outer turn, based on the interleaved winding design, we designed a new winding structure by changing the number of winding turns. To clearly represent the winding structure, we drew a 3D structure diagram and a cross-sectional schematic of the winding, as shown in Figure 1.

Figure 1a depicts the previous four-turn interleaved winding design, while Figure 1b shows the improved six-turn interleaved winding design based on the four-turn interleaved winding design. The most noticeable difference is that the output terminal of the four-turn interleaved winding is on the inner turn, whereas in the improved six-turn winding design, both the input and output terminals are on the outer turn while the interleaved winding design is maintained. Specifically, as illustrated in Figure 1a, the four-turn winding involves the input terminal passing through the outer turn of the top layer for one turn, then entering the outer turn of the bottom layer through a via, passing through the inner turn of the bottom layer within the same layer, and finally outputting from the inner turn of the bottom layer through an output terminal. Unlike the design shown in Figure 1a, the improved six-turn design has a different winding method. To ensure that both the input and output terminals are on the outer turn, facilitating circuit design and enhancing converter integration, the number of turns was increased, resulting in the six-turn interleaved winding design. Each winding consisted of a top layer and a bottom layer, with both layers containing three turns each.

To facilitate the description of the winding sequence, the three turns of each single layer are referred to as the inner turn, middle turn, and outer turn, respectively. The winding sequence was as follows: After the input terminal passed through the top layer’s outer turn, it entered the bottom layer’s middle turn through a via, then entered the top layer’s middle turn through another via, completing three turns. Next, it entered the bottom layer’s inner turn through a via, then the top layer’s inner turn through another via, and finally wound through the bottom layer’s outer turn via another via, achieving a six-turn winding. In Figure 1a,b, the switching sequences between different turns of the four-turn and six-turn interleaved windings are shown simultaneously. Based on Figure 1, we drew the models of the top and bottom layer windings used in the interleaved designs of the individual four-turn and six-turn windings, as shown in Figure 2 and Figure 3, respectively. The winding currents of the windings shown in Figure 1, Figure 2 and Figure 3 were all clockwise, and Figure 1 shows the connections between the winding turns.

According to previous research [21], the parasitic capacitance of an individual inductor is related to the overlapping area between its upper and lower turns. For multi-layer conductors, the actual parasitic capacitance should be calculated using interlayer energy considerations. Therefore, the formula for calculating the parasitic capacitance of a winding is given by Equation (1). Here, $C_{stray}$ represents the parasitic capacitance obtained through energy relationships, also known as dynamic capacitance. $V_{L_r}$ represents the voltage across the planar inductor. Specifically, $∆V$ represents the voltage difference between adjacent upper and lower copper layers, while $C$ represents the static capacitance between conductors, determined solely by the dielectric constant, conductor overlap area, and spacing between adjacent conductors. ${\epsilon }_r$ is the relative dielectric constant of the interlayer medium, and ${\epsilon }_0$ is the relative dielectric constant in a vacuum. $A$ represents the overlapping area between adjacent upper and lower copper layers, and $d$ represents the spacing between these layers.

$$C_{stray}={\displaystyle \frac{2\sum _{i=1}^N\left(\frac{1}{2}C·{∆V}^2\right)}{{V_{L_r}}^2}}$$

(1)

$$C={\epsilon }_r{\epsilon }_0{\displaystyle \frac{A}{d^2}}$$

(2)

Therefore, according to Equation (1), the optimal method for reducing the value of stray capacitance $C_{stray}$ was to decrease the $∆V$ between adjacent copper layers. To compare two different designs, we calculated the parasitic capacitance values by designing the overlapping areas of the upper and lower windings to be the same. For planar inductors, in order to fully utilize the copper area on the PCB, the single-turn wire should be made as wide as possible. When the choice of magnetic core is determined, $A$ is also fixed. The spacing between adjacent copper layers is solely determined by the PCB manufacturer, resulting in a fixed value for $d$. Consequently, the most effective method for reducing $C_{stray}$ is to decrease $∆V$. Comparing the parasitic capacitance values of the two designs, we observed that the electrostatic capacitance $C_{stray}$ between the conductors in the two different designs was different only in terms of $∆V$. Since both the four-turn and six-turn windings were implemented using a two-layer PCB structure, we set the wire width of the four-turn winding to 3 mm and the wire width of the six-turn winding to 2 mm. This ensured that the overlapping areas of the top-layer and bottom-layer windings in both designs were considered the same. Under this premise, we further compared the parasitic capacitance of the two designs. Therefore, for the comparative calculations, the adjacent turn spacing within the same layer of the four-turn interleaved winding was designed to be 0.5 mm, and the adjacent turn spacing within the same layer of the six-turn interleaved winding was designed to be 0.33 mm.

Additionally, assuming both inductors were to use the E32 ferrite core, the distance from the inner turn to the center post of the core in both winding designs was 0.5 mm. Therefore, we calculated the lengths of the inner turn and outer turn for the four-turn interleaved winding as follows: the inner turn length was 69.54 mm, and the outer turn length was 99.62 mm, according to the winding width and the turns spacing design. Similarly, for the six-turn interleaved winding, the inner turn length was 65.58 mm, the middle turn length was 89.66 mm, and the outer turn length was 120.62 mm. Considering a single-layer copper thickness of 1/3 oz and an adjacent copper layer spacing of 50 μm, we used polyester as the filling material with a relative dielectric constant of 3.2 for comparative calculations. The parameters for the two different designs are summarized in

Table 1. Different design parameters for the interleaved windings.

Winding Design	Single Turn Width	Adjacent Turn Spacing in the Same Layer	Inner Turn Length	Middle Turn Length	Outer Turn Length
4-turn interleaved winding	3 mm	0.5 mm	69.54 mm	(Without middle turn.)	99.62 mm
6-turn interleaved winding	2 mm	0.33 mm	65.58 mm	89.66 mm	120.62 mm

, and the common parameters are consolidated in

Table 2. Same parameters for the different interleaved windings.

Adjacent Copper Layer Spacing	Single-Layer Copper Thickness	Filling Material
50 μm	1/3OZ	Polyester

.

Considering the limited current capacity of a single planar interleaved winding, the parasitic capacitance of two types of interleaved windings was compared based on a calculation of six planar interleaved windings in parallel. Assuming an input voltage of 20 V applied to the winding, we can use Equation (1) to compute and compare the parasitic capacitance between the two designs. The calculated parasitic capacitance for the four-turn interleaved winding was 145 pF, while for the six-turn interleaved winding, it was 152 pF. Notably, the difference in parasitic capacitance between these two different interleaved winding designs was minimal.

Furthermore, when comparing the winding impedance of the two different interleaved winding designs, previous research [25] indicates that the expressions for the direct current $R_{dc}$ resistance and alternating current $R_{ac}$ resistance of the conductors are given by Equations (3) and (4):

$$R_{dc}=\rho {\displaystyle \frac{l}{A}}$$

(3)

$$\begin{gathered} R_{ac}=R_{skin}+R_{proximity} \\ =R_{dc}\left[{\displaystyle \frac{\mathit{sinh}\xi \left(\eta \right)+\mathit{sin}\xi \left(\eta \right)}{\mathit{cosh}\xi \left(\eta \right)-\mathit{cos}\xi \left(\eta \right)}}+{\eta }^2{\left(2m-1\right)}^2·{\displaystyle \frac{\mathit{sinh}\xi \left(\eta \right)-\mathit{sin}\xi \left(\eta \right)}{\mathit{cosh}\xi \left(\eta \right)+\mathit{cos}\xi \left(\eta \right)}}\right] \\ \xi \left(\eta \right)={\displaystyle \frac{\sqrt[]{\pi }}{2}}{\displaystyle \frac{d}{\delta \left(\eta \right)}} \\ \delta \left(\eta \right)={\displaystyle \frac{1}{\sqrt[]{\pi f{\mu }_0\sigma \eta }}} \\ \eta ={\displaystyle \frac{s}{d}} \end{gathered}$$

(4)

Among the parameters discussed, $R_{dc}$ represents the direct current resistance, $A$ denotes the cross-sectional area of the winding wire, and $\rho$ corresponds to the electrical conductivity of the copper conductor, which is approximately $1.7\times {10}^{-8} \mathsf{\Omega }/\mathrm{m}$. The alternating current resistance $R_{ac}$ is primarily influenced by skin effect and proximity effect. Specifically, $R_{skin}$ and $R_{proximity}$ represent the AC impedance resulting from skin effect and proximity effect, respectively. The coefficient $\eta$ accounts for the relationship between the spacing $s$ of adjacent copper layers and the thickness $d$ of the copper layers. Additionally, $\delta \left(\eta \right)$ signifies the skin depth, $f$ denotes the frequency, ${\mu }_0$ represents the vacuum permeability, $\sigma$ stands for the electrical conductivity of copper, and $m$ corresponds to the number of adjacent copper layers. Calculations revealed that the four-turn interleaved winding had a DC resistance of 27.56 mΩ and an AC resistance of 282.85 mΩ. Similarly, the six-turn interleaved winding had a DC resistance of 71.46 mΩ and an AC resistance of 724.21 mΩ.

Upon calculation, it was found that the parasitic capacitance of the four-turn interleaved winding was very similar to that of the six-turn interleaved winding. Specifically, the parasitic capacitance of the six-turn interleaved winding increased by only 7 pF compared to the four-turn interleaved winding. Notably, both the input and output terminals are located on the outer turn. Due to the longer equivalent length of the winding and the smaller cross-sectional areas of the individual turns, the impedance of the winding has increased.

3. Finite Element Analysis and Simulation Verification of Interleaved Windings

From Section 2, it is evident that the parasitic capacitance of the two designs is very similar according to theoretical calculations. Verifying the parasitic capacitance of multilayer conductors can be effectively achieved through electromagnetic finite element simulations. To further validate the parasitic capacitance resulting from the inductor winding structure, we utilized Ansys Maxwell to create a 3D winding model and perform electromagnetic finite element simulations. Specifically, we chose the Electric solver for computation.

The established 3D simulation models are shown in Figure 4. Figure 4a illustrates the four-turn interleaved winding design, which utilizes six parallel interleaved windings, each consisting of four turns. This design can handle higher currents. Each individual four-turn interleaved winding was composed of a double-layer flexible PCB, resulting in a total of 12 copper layers. To match the practical use of flexible PCBs in planar inductor design, the copper layers in the 3D simulation model of the four-turn interleaved winding had a thickness of 1/3 oz and a spacing of 50 µm. The material filling between the copper layers was set to polyester with a relative dielectric constant of 3.2. For the individual double-layer flexible PCB, the outermost distances from both the top layer to the copper layer and from the bottom layer to the copper layer were 25 µm. By stacking six double-sided flexible PCBs, the spacing between each copper layer was uniform at 50 µm. Figure 4b depicts the six-turn interleaved winding design. Similarly, the winding consisted of 12 copper layers. Each individual six-turn interleaved winding was formed using a double-layer flexible PCB with a single-layer copper thickness of 1/3 oz and a copper layer spacing of 50 µm. The outermost distance from the flexible PCB to the copper layer remained 25 µm, and the material between the copper layers was also polyester.

In the planar winding structures shown in Figure 4a,b, the total thickness is the same, measuring 0.67 mm. Both structures consisted of six individual inductor windings connected in parallel. The windings were constructed using 12 layers of copper, with equal spacing between adjacent copper layers. The overlapping area between adjacent copper layers was also consistent. Each individual winding followed the interleaved winding design. The key difference between the planar winding structures in Figure 4a,b lies in the number of turns for each interleaved winding and the position of the lead-out terminals. In Figure 4a, each interleaved winding has four turns, with the input terminal located at the outer turn of the winding and the output terminal at the inner turn. In contrast, the design in Figure 4b features interleaved windings with six turns, and both the input and output terminals are positioned at the outer turn of the winding. Using the 3D simulation model depicted in Figure 4, by applying the same excitation source, we compared the differences in parasitic capacitance between these two designs.

After creating the 3D electromagnetic finite element simulation models, we set up the solver and excitation source for simulation. Specifically, we employed the Electrical Transient solver, which has the advantage of solving for instantaneous electric field values, used to calculate the parasitic capacitance of multilayer conductors. When using the Electrical Transient solver, we applied the same voltage excitation to the two 3D electromagnetic simulation models shown in Figure 4. The excitation voltage was set to 20 V, and the frequency was set to 750 kHz, to calculate the transient electric field strength between the copper layers. The calculation results were used to compare the parasitic capacitance values of the two interleaved winding designs.

The simulation results of the electric field strength between adjacent copper layers are shown in Figure 5. Figure 5a depicts the electric field strength distribution between adjacent copper layers using a four-turn interleaved winding design. Figure 5b shows the electric field strength distribution between adjacent copper layers with a six-turn interleaved winding design. Comparing Figure 5a,b, it was observed that the electric field strength was highest at the outer turn position. The electric field strength between copper layers at the inner turn position, as shown in Figure 5a, was lower than that at the outer turn position. In Figure 5b, the electric field strength gradually decreases from the middle turn to the inner turn. By calculating the electric field strength distribution between copper layers in the ZY plane, as shown in Figure 6, we obtained multiple adjacent copper layer electric field strengths. Figure 6a represents the electric field strength distribution between adjacent copper layers using a four-turn interleaved winding, while Figure 6b corresponds to the design with a six-turn interleaved winding.

By utilizing the formula relating electric field strength to potential difference, we can convert the electric field strength into potential difference and calculate the interlayer energy. In Equation (3), E is the electric field strength, ∆V is the potential difference, and d is the interlayer distance. Subsequently, using Equation (3), we can compute the parasitic capacitance. Substituting the calculated results into Equation (3), we can determine the parasitic capacitance values for the two inductor designs:

$$E={\displaystyle \frac{∆V}{d}}$$

(5)

Upon calculation, the parasitic capacitance for the four-turn interleaved winding was 145 pF, while for the six-turn interleaved winding, it was 152 pF. The simulated parasitic capacitance values closely aligned with the theoretical calculations from Section 2.

In this part of the study, we established 3D simulation models for the planar interleaved winding and conducted finite element method simulations. From the simulation results, it was evident that the parasitic capacitance of the design using a six-turn interleaved winding was very similar to that of the design using a four-turn interleaved winding. The parasitic capacitance parameters obtained from the simulation closely aligned with the theoretical calculations.

4. Experiment and Verification

To further validate the results obtained from theoretical calculations and electromagnetic finite element simulations, experimental verification was necessary. To experimentally verify the practical effects of using interleaved winding inductors for LLC resonant converters, we manufactured inductor prototypes based on the calculations and simulation models from Section 2 and Section 3. The prototypes of the two different interleaved winding designs are shown in Figure 7. Figure 7a represents a planar inductor design with a four-turn interleaved winding, while Figure 7b depicts a planar inductor designed with a six-turn interleaved winding. The overlapping area between adjacent copper layers in both winding designs was consistent when comparing the impact of the winding design on parasitic capacitance. The winding shown in Figure 7a consisted of six double-sided flexible PCBs, with each individual PCB forming a four-turn interleaved winding. The width of each wire turn was 3 mm. By connecting these six double-sided flexible PCBs in parallel, we created an inductor with a total of 12 copper layers. Similarly, Figure 7b shows an inductor design with a six-turn interleaved winding. Each individual flexible PCB formed a six-turn winding with a wire width of 2 mm. The inductor shown in Figure 7b was also comprised of 12 copper layers. To ensure consistency in comparative experiments, both inductor prototypes used double-layer flexible PCBs of the same thickness, each being 0.11 mm thick. The spacing between adjacent copper layers was 50 μm, and the distance from the flexible PCB edge to the copper layer was 25 μm. When multiple layers of these flexible PCBs were stacked, the spacing between adjacent copper layers remained uniform at 50 μm.

The two different inductor prototypes shown in the figure utilized the same magnetic core specifications and material. Both designs employed E32 cores, and each prototype consisted of two E32 cores. The effective cross-sectional area of the magnetic core was 131 mm². The chosen magnetic core material was DMR50B, with initial permeability of 1400 and saturation magnetic flux density of 380 mT, manufactured by DMEGC in Hengdian, China, and suitable for inductor operation within the frequency range of 100 kHz to 2 MHz. To adjust the inductance value, we manipulated the air gap in the magnetic core. We measured the inductance at different air gap settings and frequencies using a high-precision LCR meter. Specifically, we used a 3532-50 high-precision LCR meter manufactured by HIOKI in Tokyo, Japan.

According to previous research results [17], the parasitic capacitance of resonant inductors can lead to current ringing in LLC resonant converters during operation. To validate the practical effects of using interleaved winding inductors in LLC applications, we established an LLC resonant converter test platform as shown in Figure 8. The depicted inductor prototypes served as resonant inductors for testing. The schematic diagram of the LLC resonant converter test platform is shown in Figure 9. In Figure 9, $S_1$, $S_2$, $S_3$, and $S_4$ represent GaN HEMT switches, specifically GaN System GS66516B switches manufactured by GaN Systems, Ottawa, Canada, capable of handling high-frequency switching requirements. $D_1$, $D_2$, $D_3$, and $D_4$ represent the rectifier diodes, which were SiC diodes Infineon IDL10G65C5 used for rectification for high-frequency testing requirements. $L_r$ represents the resonant inductor, which was the planar inductor prototype under test. Its value was adjusted to 3 μH for LLC resonant operation. The air gap for the inductor prototype shown in Figure 7a was set to 0.4 mm, while the air gap for the inductor prototype in Figure 7b was 1.5 mm. To achieve a resonant capacitance value of 20 nF at high-frequency switching, resonant capacitor $C_r$ consisted of multiple ceramic capacitors, specifically 30 units of C1210X102K102T, each with a capacitance of 1 nF, connected in parallel. This configuration provided a total capacitance close to 20 nF within the frequency range of 750 kHz to 1 MHz. Due to the equivalent series inductance (ESL) of the individual ceramic inductor being approximately 0.5 pH, its impact on the circuit was minimal. Additionally, since multiple ceramic capacitors were connected in parallel, the ESL introduced by the ceramic capacitors can be disregarded. $L_m$ represents the excitation inductor, corresponding to the primary winding inductor value of the transformer, which used a planar transformer with a 1:1 turns ratio to verify the experimental results. The original primary winding inductance was 10 µH. The planar transformer ferrite core was ER51, made of 3F4 material, manufactured by Ferroxcube, with a ferrite core able to operate in the frequency range of 100 kHz to 2 MHz. Input and output filter capacitors were $C_{in}$ and $C_{out}$, each with a value of 450 µF and of type ERF1KM331L20OT, manufactured by AISHI in Mianyang, Sichuan, China.

The actual test platform is shown in Figure 8. The test platform employed a digital DC voltage source and a digital load to serve as the input voltage source and DC load for the LLC resonant converter. Specifically, we used an RD-SD3020 digital DC voltage source, manufactured by Varid in Suzhou, China, to generate a DC voltage as the input voltage $V_{in}$ for the LLC resonant converter test platform, as shown in Figure 8. A digital DC load model IT8512A from ITECH was used to provide the load. A voltage probe was utilized to measure the port voltage, with the measurement location indicated in Figure 8. We used a P5100A voltage probe manufactured by Tektronix. To verify the resonant current waveform, a current probe was employed to measure the resonant current waveform. The current measurement location is also marked in Figure 8, using the CP8030B current probe manufactured by Cybertek in Shenzhen, China. An oscilloscope DSO-X 2024A from Keysight Technologies was used to record the resonant current and port voltage waveforms during testing.

The method for validating the inductor winding design using the LLC test platform was as follows: Under the same switch drive signal, a consistent input voltage to the LLC test platform was set. The resonant inductors with two different winding designs were tested under identical inductance values while varying the load. By comparing the resulting waveforms, we verified the impact of different interleaved winding designs on current ringing. In this study, we set the switch frequency to 750 kHz and the switching dead time to 100 ns. The input DC voltage was 20 V, and we performed comparative tests with loads of 25 Ω, 30 Ω, and 50 Ω.

Figure 10 illustrates the test waveforms of the resonant inductor with a four-turn interleaved winding. Based on Figure 10, the time division value was adjusted to measure the ringing current contained in the resonant current, as shown in Figure 11. Figure 10a shows the port voltage and resonant current waveforms measured with the electric load set to 25 Ω. Channel 1 represents the port voltage waveform with a division value of 20 V/div, and Channel 2 shows the resonant current waveform with a division value of 1 A/div. Both Channel 1 and Channel 2 on the oscilloscope were set to AC coupling. For the port voltage waveform measurement, the switching frequency was 750 kHz, and the peak-to-peak value of the resonant current was 3.26 A with a time division value of 280 ns/div. The measured waveforms when the load was changed to 30 Ω are shown in Figure 10b, with the resonant current peak-to-peak value reduced to 2.89 A. As shown in Figure 10a,b, the four-turn interleaved winding design exhibited high frequency and small amplitude of current ringing.

Figure 11a,b reveal that when the time division value was adjusted from 280 ns/div to 104 ns/div, the resonant current ringing frequency occurred at 16.12 MHz. For the load set at 25 Ω, the amplitude of the current ringing was 160.25 mA, while for the load set at 30 Ω, the current ringing was 120.5 mA. Furthermore, changing the load to 50 Ω and setting the time division value to 280 ns/div, the measured waveform in Figure 10c shows that the resonant current peak-to-peak value was reduced to 2.81 A compared with the 25 Ω and 30 Ω loads. With the time division value changed to 104 ns/div, the current ringing frequency was 16.12 MHz and the current ringing amplitude was 155.75 mA.

To validate the impact of different winding designs on current ringing, we tested a planar inductor with a six-turn interleaved winding design in comparison to a four-turn interleaved winding design. The input voltage of the LLC resonant converter test platform was set to 20 V, and tests were conducted under different loads of 25 Ω, 30 Ω, and 50 Ω. The resulting waveforms are shown in Figure 12 and Figure 13; the time division value was 280 ns/div in Figure 12 and 104 ns/div in Figure 13. Channel 1 represents the port voltage waveform, scaled to 20 V/div, and Channel 2 shows the resonant current waveform, scaled to 1 A/div. Figure 12a shows the waveform when the load was set to 25 Ω; the resonant current peak-to-peak value was 3.22 A while the switching frequency was 750 kHz. Figure 12b shows the waveform when the load was set to 30 Ω; the resonant current peak-to-peak value was reduced to 2.83 A. Figure 12c shows the waveform when the load was set to 50 Ω; the resonant current peak-to-peak value decreased to 2.73 A.

From theoretical calculations in Section 2, we know that the six-turn interleaved winding design exhibited higher DC and AC impedances compared with the four-turn interleaved winding design. As observed in the waveforms, the resonant current peak-to-peak values decreased for different loads when using the six-turn interleaved winding design. The measured ringing frequency was 15.82 MHz. Specifically, when the load was set to 25 Ω, the current ringing amplitude was 167.4 mA. The ringing amplitude was 147.12 mA when the load was set to 30 Ω. When the load was set to 50 Ω, the ringing amplitude was 172.8 mA. As shown in Figure 12 and Figure 13, the six-turn interleaved winding design resulted in a slightly lower current ringing frequency, leading to a very minor increase in current ringing. However, experimental results indicated that the current ringing for both the six-turn and four-turn interleaved winding designs was minimal, suggesting that the performance of both designs was very similar. The experimentally obtained results are summarized in

Table 3. Resonant current measurement results under 750 KHz switching frequency.

Winding Design	Load Resistance	Resonant Current Peak-to-Peak Amplitude	Current Ringing Frequency	Current Ringing Amplitude
4-turn interleaved winding	25 Ω	3.26 A	16.12 MHz	160.25 mA
	30 Ω	2.89 A	16.12 MHz	120.5 mA
	50 Ω	2.81 A	16.12 MHz	155.75 mA
6-turn interleaved winding	25 Ω	3.22 A	15.82 MHz	167.4 mA
	30 Ω	2.83 A	15.82 MHz	147.12 mA
	50 Ω	2.73 A	15.82 MHz	172. mA

.

Based on the experimental test results, we further measured the total harmonic distortion (THD) of the resonant current to validate the impact of using two different winding designs for the inductor in the LLC test platform. THD is a crucial metric that quantifies the distortion caused by harmonics in a voltage or current signal. By comparing the THD values, assessed the effectiveness of the different winding designs, as shown in

Table 4. Resonant current waveform THD value measurement results.

Winding Design	Load Resistance	Resonant Current THD Value
4-turn interleaved winding	25 Ω	5.52%
	30 Ω	7.14%
	50 Ω	10.96%
6-turn interleaved winding	25 Ω	5.86%
	30 Ω	7.22%
	50 Ω	11.8%

.

5. Discussion

Based on the previous content, theoretical calculations, finite element simulations, and experimental validation have shown that there is a minimal difference in parasitic capacitance between two different interleaved winding designs. These designs are suitable for low-current-ringing LLC resonant converters. Considering practical applications, high-power-density LLC resonant converters with high integration use FR-4 as the substrate material for PCBs, whose single copper layer thickness can be 2 OZ or even 3 OZ. To further investigate, we performed theoretical calculations for both interleaved winding designs using a 12-layer copper PCB. Using the 12-layer PCB design with a total thickness of 3 mm, adjacent copper layers spaced 0.2 mm apart, and FR-4 as the substrate material, we compared the two different designs where the single copper layer thickness was 2 OZ. The winding width and spacing between adjacent turns in the same layer were calculated based on the data shown in Table 1. To ensure the current-carrying capacity of the multi-layer planar inductor, we followed the IPC-2221 standard to calculate the current-carrying capacity of the inner PCB layers. The calculation formula, as shown in Equation (6), considers the maximum current (I) that the conductor can withstand, a coefficient $k$, temperature rise $∆T$, cross-sectional area $A$ of the wire, and copper thickness $\delta$. Under room temperature conditions of 25 °C and a temperature rise of 45 °C, the four-turn interleaved winding design was able to withstand a peak current of 30 A, while the six-turn interleaved winding design could withstand a peak current of 24 A.

$$I=k·∆T^{0.44}·A^{0.725}·{\delta }^{0.725}$$

(6)

Furthermore, we compared the parasitic capacitance of two inductor winding designs using a 3 mm thick 12-layer PCB structure. The winding width and spacing were calculated based on the data from Table 1. We used Equations (1) and (2) to compute the parasitic capacitance. The relative dielectric constant ${\epsilon }_r$ changed from the previously calculated value of 3.2 for polyester material to 4.7 for FR-4 material. Assuming an input voltage of 20 V, the calculated parasitic capacitance for the four-turn interleaved design was 78.3 pF, while the six-turn interleaved design had a parasitic capacitance of 82.08 pF. Furthermore, using Equations (3) and (4), we calculated the winding impedance for a 3 mm thick PCB with interleaved windings. The DC impedance for the four-turn interleaved design was 4.59 mΩ, the AC impedance was 36.26 mΩ, and for the six-turn interleaved design, the DC impedance was 11.91 mΩ, and the AC impedance was 92.84 mΩ.

According to the IPC-2221 standard, we can calculate the maximum magnetic flux density $B_{max}$ using Equation (7). In this equation, $L$ represents the inductance value, $I$ is the maximum current, $n$ denotes the number of turns, and $A_c$ represents the cross-sectional area of the magnetic core:

$$B_{max}={\displaystyle \frac{LI}{2n{A}_c}}$$

(7)

For the four-turn interleaved design, the maximum magnetic flux was 85.8 mT. For the six-turn interleaved design, the maximum magnetic flux was 45.8 mT. If we further enhance the current-carrying capacity of the six-turn interleaved design by increasing the PCB copper thickness to 3 OZ, the maximum current it can handle becomes 30 A. In that case, the maximum magnetic flux would be 57.2 mT.

Based on the calculations above, when using a 12-layer PCB with a thickness of 3mm and a copper thickness of 2 OZ to construct a planar inductor, the increase in parasitic capacitance for the six-turn interleaved design compared with the four-turn interleaved design was minimal. However, due to the narrower wire width in a single turn, there would be greater winding losses. Both designs have a maximum magnetic flux significantly below the saturation magnetic flux.

Therefore, in practical applications where the LLC resonant converter is not integrated into a single PCB, the four-turn interleaved design is preferred due to its stronger current-carrying capacity. If the LLC resonant converter is integrated into a single PCB, the six-turn interleaved design is prioritized. For peak currents exceeding 24 A, it is recommended to use a PCB with a copper thickness of 3 OZ.

6. Conclusions

In this study, a new interleaved winding for planar inductors was designed to meet the low current ringing requirements of LLC resonant converters. Compared with the previous four-turn interleaved winding design, its output and input terminals were both on the outer turn, which was more conducive to improving the integration of the power converter. Under conditions including the same overlapping areas of adjacent copper layers, the new interleaved winding design was compared with the previous interleaved winding design. Through theoretical calculations, it was verified that the parasitic capacitance of the two interleaved windings was very similar, and this was confirmed through finite element simulation.

In the experiment, planar inductor prototypes were made according to the two different interleaved winding designs, for experimental verification. The experimental results showed that the effects of the two interleaved winding designs were very similar, and the current ringing was minimal. Under conditions including the same overlapping areas of adjacent copper layers, the DC and AC impedance of the six-turn interleaved winding was almost three times that of the four-turn interleaved winding, resulting in greater winding losses. When using the six-turn interleaved design for the 12-layer planar inductor winding, compared with the four-turn interleaved winding design, the parasitic capacitance increased by 7 pF. For the same load setting, it was verified that the planar inductor using the six-turn interleaved winding design, compared with the four-turn interleaved winding design, had a current ringing frequency that decreased by 0.3 MHz, an amplitude that increased by 7 mA, and a THD that increased by about 0.2%. Therefore, the six-turn interleaved winding also met the low current ringing design requirements. Considering the improvements in the integration of the power converter, the six-turn interleaved winding is a better design compared with the previous four-turn interleaved winding.