State Space Average Modeling, Small Signal Analysis, and Control Implementation of an Efficient Single-Switch High-Gain Multicell Boost DC-DC Converter with Low Voltage Stress

Abstract

This paper presents the closed-loop control of a single-switch high-gain multicell boost DC-DC converter working in a continuous conduction mode (CCM). This converter is particularly designed for applications in photovoltaic systems. One of the main advantages of the proposed converter is that it only employs one active semiconductor switch, which decreases the converter losses and cost, increases the efficiency, and simplifies the control circuit. Moreover, the multicell nature of the proposed converter offers the possibility of obtaining the required voltage gain by selecting the number of cells. State space average (SSA) modeling and small-signal analysis are used to model the switching converter power stages of the proposed converter. The parasitic series resistances of the passive elements of the converter circuit are considered to improve the accuracy of the modeling. Small-signal analysis is used to derive the open-loop transfer functions, input-to-output and control-to-output transfer functions of the proposed converter to examine its dynamic performance. The stability of the converter is analyzed to design the parameters of the voltage controller using the proposed modeling method. The experimental prototype of the proposed single-switch two-cell boost DC-DC converter was implemented. The simulation and experimental results proved the effectiveness of the proposed boost DC-DC converter under different working conditions. It has a fast dynamic response without overshoots. A comprehensive comparison between the proposed converter and previous boost converters is provided. It guarantees a required variable and constant high voltage gain with a wider duty ratio range. It compromises between the required performance, the low number of components, low voltage stress on the components, and cost-effectiveness. The experimental efficiency of the proposed converter is about 96% at a 100 W load.

1. Introduction

The global need for electricity is increasing all the time. Because of the poor supply and high cost of traditional energy sources, there is a growing need to use renewable energy sources (RESs). Among these renewable energy sources, photovoltaics (PVs), wind turbines (WTs), and fuel cells (FCs) have developed rapidly in recent decades. To tie these sources with the utility grid, the low DC output voltage levels produced by them must be boosted to high DC voltage levels. High-voltage gain DC-DC converters are widely utilized in a diversity of applications, such as RESs, uninterruptible power supplies (UPSs), new-energy electric vehicles (NEEVs), aircraft power supply systems, railway energy storage systems, etc. [1,2,3]. High-boosting DC-DC converters are often employed to increase voltage and efficiency in diverse ways, each with its own set of advantages and disadvantages [4].

Non-isolated standard DC-DC converters are characterized by their simple installation, ease of control circuit use, and low cost. But despite these features, they are not suitable for applications that require high voltage gain due to the need to work at large duty cycle values. This, in turn, leads to more switching and conduction losses at constant input voltage, increasing input current ripples and decreasing system effectiveness [5].

Several innovative DC-DC topologies have been developed to accomplish significant extreme voltage gain. Isolated and non-isolated are the types of high-gain DC-DC topologies. Isolated topologies have significant issues, such as heat effects, voltage ripples on the power switches, core saturation, and leakage inductance, and their enormous volume makes them more costly. Non-isolated types are used instead for their better voltage gain; they are more compact and less expensive because no galvanic isolation is required [6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25]. A non-isolated step-up interleaved converter was introduced in [6]. High voltage gain with a minimal switch voltage stress was satisfied, but it has more components and is not suitable for applications that require smaller gain or lighter loads. In [7], a conventional DC-DC boost converter was linked to a switched capacitor and coupled inductor to raise the voltage gain and efficacy. Nevertheless, inductor core losses continue to be affected by excessive input current ripples. To obtain high voltage gain with a moderate duty cycle and increase efficiency, the interleaved boost converter was introduced in [8,9]. However, they have difficulty separating gate signals, raising costs. Furthermore, the voltage gain was like that of a traditional boost converter. Reference [10] proposed a variety of switched capacitor-based DC-DC boost converters, while [11] employed a switched capacitor/inductor. Although high voltage gain was achieved, they had significant conduction losses, severe switching stresses, and complicated circuits. A cascaded boost converter that provides high voltage gain with minimal switching losses and current ripples was employed in [12]. However, drawbacks, such as increased costs, decreased efficiency, and the complexity of the control system, were identified. A single-cell DC-DC topology based on a hybrid switched inductor was introduced in [13]. High voltage gain, low power switching stresses, and high efficiency were satisfied. However, the number of components in this converter diminished efficiency while increasing the circuit’s cost and size. Reference [14] proposed a single-switch DC-DC-boosting topology based on a traditional boost converter, voltage lift method, and a switched capacitor. Also, a single-switch DC-DC converter based on a traditional boost converter and a switched capacitor was suggested in [15]. High efficiency and small voltage stresses through the main switch and diodes were attained, but the voltage gain was still small compared with other topologies, and the number of converter components was large. A non-isolated DC-DC boost converter achieved by merging a dual step-up converter with a switching inductor topology was provided in [16]. High voltage gain, low switching losses, and small voltage stresses across the switches were accomplished, but the large number of components increased the size of the converter. In [17], a DC-DC converter with a voltage multiplier cell (VMC) was described. High voltage gain, minimal voltage stress across the switches, and great efficiency were noted. On the other hand, the large component count increased the topology dimensions and costs. A single-switch DC-DC topology was introduced in [18]. The design of this converter featured a double voltage lift approach, and it comprised a VMC, a super lift Luo converter, and a cascaded step-up topology. Issues relating to high-voltage gain and minimum input current ripples were addressed, but the large number of components reduced the converter efficiency. Reference [19] offered a new SEPIC boost DC-DC topology. The semiconductor switches operated with soft switching, which reduced the converter losses and enhanced the efficiency. Nevertheless, the voltage gain was not very high, and the number of components was large. Other topologies such as quasi-Z-source, quasi-Y-source, or a combination between them were found in [20,21,22,23]. Even though these topologies provide substantial voltage gain with low duty cycles and constant input current, they have restricted duty cycles, severe stresses on the main switch, and complicated driving circuits. Reference [24] developed a DC-DC converter that employed VMC with a voltage extend circuit to increase the voltage gain. It was possible to achieve extreme voltage gain and minimal voltage stresses on the active components. However, the input current was discontinuous since the primary switch was connected directly with the input DC source, and the number of components was large. In addition, as the number of cells increased, converter efficiency fell. The topologies found in [25,26,27,28,29,30] introduced variety of designs based on quad-switched inductors, a combination of boost and SEPIC, switched inductors, or active-passive inductor cells. Although the voltage gain derived from these converters was greater than that from the conventional, some of them had a large number of components [25,27,29,30], and others had a large number of switches [26,28,29], which, in turn, made the control circuit problematic, increased the losses, and raised costs. To address the aforementioned issues, a modified DC-DC step-up converter was developed and presented in [31]. Its characteristics included continuous input current, easy control, extreme voltage gain, and low voltage stress on the active switches. Likewise, cascading extra cells with ultra-high voltage gain can be provided. To model, analyze, and design such converters, developed tools such as state space average (SSA) modeling and small signal analysis were introduced [32,33,34,35,36]. Solving the state space equations of such DC-DC converters is more challenging because the duty cycle serves as the converters’ control input. The behavior of the DC-DC converters is nonlinear and time-varying. However, in order to design the controller, the system must be linear and time-invariant. Therefore, the state space average model (SSAM) and the small signal model (SSM) are used for this purpose. In [32], the SSAM of a boost DC-DC converter considering all the parasitic elements was presented. The transfer functions of a proposed AC-AC converter were derived in [33] using the SSM and the gains of proportional-integral (PI) voltage controller based on the stability analysis using the frequency response method. In [34], small signal analysis and PI controller implementation of a boost converter-fed permanent magnet DC (PMDC) motor for electric vehicle (EV) applications were introduced. In [35], the various principles of SSAM of DC-DC boost converters operating in CCM were presented. The effects of parasitic elements were also included. In [36], a two-loop control strategy for a current-fed half-bridge (CFHB) DC-DC converter was presented. Both the current control loop and the voltage control loop are designed at a phase margin of 60°. The stability of the control system was validated using PSIM software. In [37,38], electrothermal average models of a diode–IGBT switch and a diode-MOSFET switch for modeling the DC-DC converters were introduced, respectively. The equations used in the introduced models allow modeling the converter operation in both CCM and discontinuous conduction mode (DCM). In [39], an average SSM of a conventional boost DC-DC converter in CCM considering the switching power loss was presented. In [40], a reduced average model of a high-voltage gain DC-DC converter with multicell diode-capacitor network considering ideal components was presented to overcome the complexity of the multicell converter modeling. The reduced model was used to simplify the closed-loop controller design.

In this paper, an SSAM and an SSM of a novel single switch high gain multicell boost DC-DC converter are developed considering the series parasitic resistances of the passive elements. With the help of the developed models, an extensive analysis is conducted to investigate the steady state and dynamic characteristics of the proposed converter. A small signal model and the corresponding control-to-output and input-to-output open-loop transfer functions of the proposed topology are presented. The stability analysis of the proposed topology is presented to design the voltage controller of the proposed converter. The validity of the developed SSAM of the proposed converter is emphasized through experimental verification of the proposed single switch two-cell boost DC-DC converter. Different results are presented under different operating conditions.

The advantages of the single switch two-cell boost DC-DC converter are as follows:

• Low voltage stress on the main switch and diodes.
• Simplicity of control due to single-switch topology.
• The structure of the converter can be extended to n cells for high voltage gain.
• Compact size and minimum number of components guarantee a cost-effective converter.
• Good robustness of the closed-loop control under different working conditions.

2. Proposed Converter Topology

Figure 1 displays a new topology for a single-switch multicell step-up DC-DC converter [31]. The proposed converter topology consists of only one semiconductor switch (SW) that controls the power flow from the input side (supply) to the output side (load) through switching on and off, n cells, output diode, and an output capacitor. Each cell of the proposed converter circuit consists of one inductor, one capacitor, and two diodes. In [31], the circuit description and its modes of operation were explained in detail. The steady-state behavior of the proposed converter was analyzed. Also, the voltage gain in continuous conduction mode (CCM) was evaluated. According to this, the voltage gain of n cells is given by the following formula:

$$g={\displaystyle \frac{2-d}{1-d}}+2(n-1)$$

(1)

where $g$ is the voltage gain and d is the main switch duty ratio.

3. State Space Average Modeling

The following assumptions are considered when deriving the SSAM of the proposed topology:

• The semiconductor switch is on (i.e., closed) for a time dT_s and is off (i.e., open) for a time (1 − d)T_s during a switching period time T_s.
• The duty ratio (d) is expressed as the ratio of the time the switch is on (on time) over the switching period time T_s. The switching frequency (F_s) is given as F_s = 1/T_s.
• The converter works in the CCM, considering the design considerations of inductors and capacitors as follows:

  $$\left.\begin{array}{c}{L}_n={\displaystyle \frac{d\left(n+1-d\right)}{{∆}_i{g}^2}}R{T}_s\\ C_n={\displaystyle \frac{g^2{T}_s}{{∆}_{v}R}}{\displaystyle \frac{\left(1-d\right)}{\left(n+1-d\right)}}\\ C_o={\displaystyle \frac{\left(1-d\right)T_s}{{∆}_{v}R}}\left({\displaystyle \frac{g}{\left(n+1-d\right)}}-1\right)\end{array}\right\}$$

  (2)

  where L_n is the inductance of cell n, C_n is the capacitance of cell n, Co is the output capacitance, R is the load resistance, ∆_i is the allowable percentage of the inductor current ripple, and ∆_v is the allowable percentage of the capacitor voltage ripple.
• The semiconductor switch and all diodes are modeled as ideal semiconductor devices.
• The parasitic series resistances of the passive elements (i.e., inductors and capacitors) are taken into consideration.

3.1. On State (0 < t < dT_s)

Figure 2 illustrates the on-state equivalent circuit of the proposed multicell converter. The active and inactive semiconductor devices are shown in Figure 2a, while the analogous circuit diagram of the converter is displayed in Figure 2b. In the on state, the semiconductor switch and all diodes except the output diode (D_o) are closed.

Using Kirchhoff’s voltage law (KVL), the differential equations of each converter cell are derived as

$$v_{in}=i_{Li}{r}_{Li}+L_i{\displaystyle \frac{d{i}_{Li}}{dt}}$$

(3)

$$v_{in}=i_{Ci}{r}_{Ci}+v_{Ci}=r_{Ci}{C}_i{\displaystyle \frac{d{v}_{Ci}}{dt}}+v_{Ci}$$

(4)

where v_in refers to the input voltage, and L_i and r_Li are the inductance and the equivalent series resistances (ESR) of the inductor of cell i, respectively. C_i and r_Ci are the capacitance and the ESR of the capacitor of cell i, respectively, while i_Li and v_Ci are the inductor current and the capacitor voltage of the cell i, respectively.

Using KVL/KCL (Kirchhoff’s current law), the differential equations of the output circuit are derived as

$$i_o=-i_{Co}$$

(5)

where i_o and i_Co are the output current and the current via the output capacitor, respectively. These currents are given as

$$i_o={\displaystyle \frac{v_o}{R}}={\displaystyle \frac{i_{Co}{r}_{Co}+v_{Co}}{R}}$$

(6)

$$i_{Co}=C_o{\displaystyle \frac{d{v}_{Co}}{dt}}$$

(7)

where C_o and r_Co are capacitance and ESR of the output capacitor, respectively. v_o and v_Co are the output voltage and the output capacitor voltage, respectively, and R is the output (load) resistance.

For SSAM, the inductor current for the converter cell i_Li, the capacitor voltage for the converter cell v_Ci, and the voltage across the output capacitor v_Co are considered as state variables. Therefore, for an n cell converter, there are 2n + 1 state variables. Using Equations (3)–(7), the differentiation of the state variables is given as

$${\displaystyle \frac{d{i}_{Li}}{dt}}={\displaystyle \frac{1}{L_i}}{V}_{in}-{\displaystyle \frac{r_{Li}}{L_i}}{i}_{Li}$$

(8)

$${\displaystyle \frac{d{v}_{Ci}}{dt}}={\displaystyle \frac{1}{r_{Ci}{C}_i}}{V}_{in}-{\displaystyle \frac{1}{r_{Ci}{C}_i}}{v}_{Ci}$$

(9)

$${\displaystyle \frac{d{v}_{Co}}{dt}}={\displaystyle \frac{-1}{C_o(r_{Co}+R)}}{v}_{Co}$$

(10)

Since the state space equations in the on state can be given as

$$\dot{x}=A_{1}x+B_{1}u$$

(11)

$$y=C_{1}x+E_{1}u$$

(12)

Therefore:

$$\left[\begin{array}{c}{\displaystyle \frac{d{i}_{L1}}{dt}}\\ {\displaystyle \frac{d{v}_{C1}}{dt}}\\ {\displaystyle \frac{d{i}_{L2}}{dt}}\\ {\displaystyle \frac{d{v}_{C2}}{dt}}\\ ⋮\\ {\displaystyle \frac{d{i}_{Ln}}{dt}}\\ {\displaystyle \frac{d{v}_{Cn}}{dt}}\\ {\displaystyle \frac{d{v}_{Co}}{dt}}\end{array}\right]=\left[\begin{array}{cccccccc}{\displaystyle \frac{-r_{L1}}{L_1}}& 0& 0& 0& 0& 0& 0& 0\\ 0& {\displaystyle \frac{-1}{r_{C1}{C}_1}}& 0& 0& 0& 0& 0& 0\\ 0& 0& {\displaystyle \frac{-r_{L2}}{L_2}}& 0& 0& 0& 0& 0\\ 0& 0& 0& {\displaystyle \frac{-1}{r_{C2}{C}_2}}& 0& 0& 0& 0\\ 0& 0& 0& 0& \ddots & 0& 0& 0\\ 0& 0& 0& 0& 0& {\displaystyle \frac{-r_{Ln}}{L_n}}& 0& 0\\ 0& 0& 0& 0& 0& 0& {\displaystyle \frac{-1}{r_{Cn}{C}_n}}& 0\\ 0& 0& 0& 0& 0& 0& 0& {\displaystyle \frac{-1}{C_o\left(r_{Co}+R\right)}}\end{array}\right]\left[\begin{array}{c}{i}_{L1}\\ v_{C1}\\ i_{L2}\\ v_{C2}\\ ⋮\\ i_{Ln}\\ v_{Cn}\\ v_{Co}\end{array}\right]+\left[\begin{array}{c}{\displaystyle \frac{1}{L_1}}\\ {\displaystyle \frac{1}{r_{C1}{C}_1}}\\ \begin{array}{c}{\displaystyle \frac{1}{L_2}}\\ {\displaystyle \frac{1}{r_{C2}{C}_2}}\\ \begin{array}{c}⋮\\ {\displaystyle \frac{1}{L_n}}\\ \begin{array}{c}{\displaystyle \frac{1}{r_{Cn}{C}_n}}\\ 0\end{array}\end{array}\end{array}\end{array}\right]v_{in}$$

(13)

The output voltage in the on state is given as

$$v_o=\left[\begin{array}{cccccccc}0& 0& 0& 0& \cdots & 0& 0& {\displaystyle \frac{R}{r_{Co}+R}}\end{array}\right]\left[\begin{array}{c}{i}_{L1}\\ v_{C1}\\ i_{L2}\\ v_{C2}\\ ⋮\\ i_{Ln}\\ v_{Cn}\\ v_{Co}\end{array}\right]+\left[0\right]v_{in}$$

(14)

3.2. Off State (dT_s < t < T_s)

Figure 3 illustrates the off-state equivalent circuit of the proposed multicell converter. The active and inactive semiconductor devices are shown in Figure 3a, while the analogous circuit diagram is illustrated in Figure 3b. In the off state, the semiconductor switch and all diodes except the output diode (D_o) are open. Using KVL/KCL, the general differential equation of the multicell converter in the off state is derived as

$$v_{in}=\sum _{i=1}^n\left(i_{Li}{r}_{Li}+L_i{\displaystyle \frac{d{i}_{Li}}{dt}}-i_{Ci}{r}_{Ci}-v_{Ci}\right)+v_o$$

(15)

Since

$$i_{Ci}=-i_{Li}$$

(16)

Therefore,

$$v_{in}=\sum _{i=1}^n\left(i_{Li}\left(r_{Li}+r_{Ci}\right)+L_i{\displaystyle \frac{d{i}_{Li}}{dt}}-v_{Ci}\right)+v_o$$

(17)

Since

$$i_{L1}=i_{L2}=i_{Ln}$$

(18)

Therefore,

$$i_o=i_{L1}-i_{Co}$$

(19)

Using Equations (17)–(19), the differentiation of the state variables is given as

$${\displaystyle \frac{d{i}_{Li}}{dt}}={\displaystyle \frac{1}{{nL}_i}}{v}_{in}+{\alpha }_i{i}_{Li}+{\displaystyle \frac{1}{L_i}}{v}_{Ci}-{\displaystyle \frac{1}{{nL}_i}}\left({\displaystyle \frac{R}{r_{Co}+R}}\right)v_{Co}$$

(20)

where

$${\alpha }_i={\displaystyle \frac{-1}{L_i}}\left(r_{Li}+r_{Ci}+{\displaystyle \frac{r_{Co}R}{n\left(r_{Co}+R\right)}}\right)$$

(21)

$${\displaystyle \frac{d{v}_{Ci}}{dt}}={\displaystyle \frac{-1}{C_i}}{i}_{Li}$$

(22)

$${\displaystyle \frac{d{v}_{Co}}{dt}}={\displaystyle \frac{R}{C_o(r_{Co}+R)}}{i}_{L1}+{\displaystyle \frac{-1}{C_o(r_{Co}+R)}}{v}_{Co}$$

(23)

where i_L1 is the inductor current of cell 1. Since the state space equations in the off state can be given as

$$\dot{x}=A_{2}x+B_{2}u$$

(24)

$$y=C_{2}x+E_{2}u$$

(25)

Therefore:

$$\left[\begin{array}{c}{\displaystyle \frac{d{i}_{L1}}{dt}}\\ {\displaystyle \frac{d{v}_{C1}}{dt}}\\ {\displaystyle \frac{d{i}_{L2}}{dt}}\\ {\displaystyle \frac{d{v}_{C2}}{dt}}\\ ⋮\\ {\displaystyle \frac{d{i}_{Ln}}{dt}}\\ {\displaystyle \frac{d{v}_{Cn}}{dt}}\\ {\displaystyle \frac{d{v}_{Co}}{dt}}\end{array}\right]=\left[\begin{array}{cccccccc}{\alpha }_1& {\displaystyle \frac{1}{L_1}}& 0& 0& 0& 0& 0& {\displaystyle \frac{-1}{{nL}_1}}\left({\displaystyle \frac{R}{r_{Co}+R}}\right)\\ {\displaystyle \frac{-1}{C_1}}& 0& 0& 0& 0& 0& 0& 0\\ 0& 0& {\alpha }_2& {\displaystyle \frac{1}{L_2}}& 0& 0& 0& {\displaystyle \frac{-1}{{nL}_2}}\left({\displaystyle \frac{R}{r_{Co}+R}}\right)\\ 0& 0& {\displaystyle \frac{-1}{C_2}}& 0& 0& 0& 0& 0\\ 0& 0& 0& 0& \ddots & 0& 0& 0\\ 0& 0& 0& 0& 0& {\alpha }_n& {\displaystyle \frac{1}{L_n}}& {\displaystyle \frac{-1}{{nL}_n}}\left({\displaystyle \frac{R}{r_{Co}+R}}\right)\\ 0& 0& 0& 0& 0& {\displaystyle \frac{-1}{C_n}}& 0& 0\\ {\displaystyle \frac{R}{C_o\left(r_{Co}+R\right)}}& 0& 0& 0& 0& 0& 0& {\displaystyle \frac{-1}{C_o\left(r_{Co}+R\right)}}\end{array}\right]\left[\begin{array}{c}{i}_{L1}\\ v_{C1}\\ i_{L2}\\ v_{C2}\\ ⋮\\ i_{Ln}\\ v_{Cn}\\ v_{Co}\end{array}\right]+\left[\begin{array}{c}{\displaystyle \frac{1}{{nL}_1}}\\ 0\\ \begin{array}{c}{\displaystyle \frac{1}{n{L}_2}}\\ 0\\ \begin{array}{c}⋮\\ {\displaystyle \frac{1}{n{L}_n}}\\ \begin{array}{c}0\\ 0\end{array}\end{array}\end{array}\end{array}\right]v_{in}$$

(26)

where α₁, α₂ and α_n are

$${\alpha }_1={\displaystyle \frac{-1}{L_1}}\left(r_{L1}+r_{C1}+{\displaystyle \frac{r_{Co}R}{n\left(r_{Co}+R\right)}}\right)$$

(27)

$${\alpha }_2={\displaystyle \frac{-1}{L_2}}\left(r_{L2}+r_{C2}+{\displaystyle \frac{r_{Co}R}{n\left(r_{Co}+R\right)}}\right)$$

(28)

$${\alpha }_n={\displaystyle \frac{-1}{L_n}}\left(r_{Ln}+r_{Cn}+{\displaystyle \frac{r_{Co}R}{n\left(r_{Co}+R\right)}}\right)$$

(29)

The output voltage in the off state is given as

$$v_o=\left[\begin{array}{cccccccc}{\displaystyle \frac{r_{Co}R}{r_{Co}+R}}& 0& 0& 0& \cdots & 0& 0& {\displaystyle \frac{R}{r_{Co}+R}}\end{array}\right]\left[\begin{array}{c}{i}_{L1}\\ v_{C1}\\ i_{L2}\\ v_{C2}\\ ⋮\\ i_{Ln}\\ v_{Cn}\\ v_{Co}\end{array}\right]+\left[0\right]v_{in}$$

(30)

3.3. Average Model

Since the SSAM expresses the average behavior of the state variables over a switching period, the state space averaged description is given as

$$\dot{x}=Ax+Bu$$

(31)

$$y=Cx+Eu$$

(32)

where the A, B, C, and E matrices are given as

$$A=d{A}_1+\stackrel{‵}{d}{A}_2$$

(33)

$$B=d{B}_1+\stackrel{‵}{d}{B}_2$$

(34)

$$C=d{C}_1+\stackrel{‵}{d}{C}_2$$

(35)

$$E=d{E}_2+\stackrel{‵}{d}{E}_2$$

(36)

where

$$\stackrel{‵}{d}=\left(1-d\right)$$

(37)

Hence

$$A=\left[\begin{array}{cccccccc}{\displaystyle \frac{-r_{L1}}{L_1}}d+{\alpha }_1\stackrel{‵}{d}& {\displaystyle \frac{1}{L_1}}\stackrel{‵}{d}& 0& 0& 0& 0& 0& {\displaystyle \frac{-1}{{nL}_1}}\left({\displaystyle \frac{R}{r_{Co}+R}}\right)\stackrel{‵}{d}\\ {\displaystyle \frac{-1}{C_1}}\stackrel{‵}{d}& {\displaystyle \frac{-1}{r_{C1}{C}_1}}d& 0& 0& 0& 0& 0& 0\\ 0& 0& {\displaystyle \frac{-r_{L2}}{L_2}}d+{\alpha }_2\stackrel{‵}{d}& {\displaystyle \frac{1}{L_2}}\stackrel{‵}{d}& 0& 0& 0& {\displaystyle \frac{-1}{{nL}_2}}\left({\displaystyle \frac{R}{r_{Co}+R}}\right)\stackrel{‵}{d}\\ 0& 0& {\displaystyle \frac{-1}{C_2}}\stackrel{‵}{d}& {\displaystyle \frac{-1}{r_{C2}{C}_2}}d& 0& 0& 0& 0\\ 0& 0& 0& 0& \ddots & 0& 0& 0\\ 0& 0& 0& 0& 0& {\displaystyle \frac{-r_{Ln}}{L_n}}d+{\alpha }_n\stackrel{‵}{d}& {\displaystyle \frac{1}{L_n}}\stackrel{‵}{d}& {\displaystyle \frac{-1}{{nL}_n}}\left({\displaystyle \frac{R}{r_{Co}+R}}\right)\stackrel{‵}{d}\\ 0& 0& 0& 0& 0& {\displaystyle \frac{-1}{C_n}}\stackrel{‵}{d}& {\displaystyle \frac{-1}{r_{Cn}{C}_n}}d& 0\\ {\displaystyle \frac{R}{C_o\left(r_{Co}+R\right)}}\stackrel{‵}{d}& 0& 0& 0& 0& 0& 0& {\displaystyle \frac{-1}{C_o\left(r_{Co}+R\right)}}\end{array}\right]$$

(38)

$$B=\left[\begin{array}{c}{\displaystyle \frac{d}{L_1}}+{\displaystyle \frac{\stackrel{‵}{d}}{{nL}_1}}\\ {\displaystyle \frac{d}{r_{C1}{C}_1}}\\ \begin{array}{c}{\displaystyle \frac{d}{L_2}}+{\displaystyle \frac{\stackrel{‵}{d}}{{nL}_2}}\\ {\displaystyle \frac{d}{r_{C2}{C}_2}}\\ \begin{array}{c}⋮\\ {\displaystyle \frac{d}{L_n}}+{\displaystyle \frac{\stackrel{‵}{d}}{{nL}_n}}\\ \begin{array}{c}{\displaystyle \frac{d}{r_{Cn}{C}_n}}\\ 0\end{array}\end{array}\end{array}\end{array}\right]$$

(39)

$$C=\left[\begin{array}{cccccccc}{\displaystyle \frac{r_{Co}R\stackrel{‵}{d}}{r_{Co}+R}}& 0& 0& 0& \cdots & 0& 0& {\displaystyle \frac{R}{r_{Co}+R}}\end{array}\right]$$

(40)

$$E=\left[0\right]$$

(41)

At steady state,

$$\dot{x}=0$$

(42)

Therefore, the average values of the state variables of the proposed multicell step-up converter are calculated as

$$x=-A^{-1}Bu$$

(43)

4. Small Signal Analysis

Small signal analysis is a useful technique for examining the dynamic performance and stability of power electronics converters. It can be used to determine the transfer functions to examine the output performance of the power electronics converters against disturbances or variations in the input. To obtain the SSM of the proposed single-switch multicell step-up DC-DC converter, a perturbation in all variables of the SSAM is introduced around the steady-state operating point such that

$$x=X+\tilde{x}$$

(44)

$$u=U+\tilde{u}$$

(45)

$$y=Y+\tilde{y}$$

(46)

$$d=D+\tilde{d}$$

(47)

$$\stackrel{‵}{d}=\stackrel{‵}{D}-\tilde{d}$$

(48)

$$\stackrel{‵}{D}=1-D$$

(49)

$$v_{in}=V_{in}+{\tilde{v}}_{in}$$

(50)

$$v_o=V_o+{\tilde{v}}_o$$

(51)

where the capitalized quantities (X, Y, D, V_in, …) are the steady state values (DC values) and the dashed quantities ($\tilde{x}$, $\tilde{y}$, $\tilde{d}$, ${\tilde{v}}_{in}$, …) are small perturbations (AC values). Since the SSAM can be given as

$${\displaystyle \frac{dx}{dt}}=(d{A}_1+\stackrel{‵}{d}{A}_2)x+(d{B}_1+\stackrel{‵}{d}{B}_2)u$$

(52)

Therefore,

$${\displaystyle \frac{d(X+\tilde{x})}{dt}}=((D+\tilde{d})A_1+(\stackrel{‵}{D}-\tilde{d})A_2)\left(X+\tilde{x}\right)+((D+\tilde{d})B_1+(\stackrel{‵}{D}-\tilde{d})B_2)(U+\tilde{u})$$

(53)

Hence,

$$\begin{array}{c}{\displaystyle \frac{d\tilde{x}}{dt}}=\underbrace{(D{A}_1+\stackrel{‵}{D}{A}_2)X+(D{B}_1+\stackrel{‵}{D}{B}_2)U}+\underbrace{(D{A}_1+\stackrel{‵}{D}{A}_2)\tilde{x}}+\underbrace{(D{B}_1+\stackrel{‵}{D}{B}_2)\tilde{u}}\\ +\underbrace{\left(\left(A_1-A_2\right)X+\left(B_1-B_2\right)U\right)\tilde{d}}+\underbrace{\left(\left(A_1-A_2\right)+\left(B_1-B_2\right)\right)\tilde{d}\tilde{x}}\end{array}$$

(54)

The previous equation consists of five terms. The first term is neglected because it is DC (steady state). The fifth term is a second-order term. It is also neglected because the value obtained from multiplication of the two incremental terms (around the equilibrium point) would be very small compared to the first-order terms, while the other three terms are first-order linear terms. Therefore, the state space equations of SSM can be given as

$${\displaystyle \frac{d\tilde{x}}{dt}}=(D{A}_1+\stackrel{‵}{D}{A}_2)\tilde{x}+(D{B}_1+\stackrel{‵}{D}{B}_2)\tilde{u}+\left(\left(A_1-A_2\right)X+\left(B_1-B_2\right)U\right)\tilde{d}$$

(55)

Using the same previous procedure:

$$\tilde{y}=(D{C}_1+\stackrel{‵}{D}{C}_2)\tilde{x}+(D{E}_1+\stackrel{‵}{D}{E}_2)\tilde{u}+\left(\left(C_1-C_2\right)X+\left(E_1-E_2\right)U\right)\tilde{d}$$

(56)

Therefore, the duty cycle to the output voltage (control-to-output) transfer function G_vd(s) of the proposed multicell converter can be given as

$$\begin{array}{cc}\hfill G_{vd}\left(s\right)={\left.{\displaystyle \frac{{\tilde{v}}_o\left(s\right)}{\tilde{d}\left(s\right)}}\right|}_{{\tilde{v}}_{in}\left(s\right)=0}& \\ & =(D{C}_1+\stackrel{‵}{D}{C}_2){(sI-(D{A}_1+\stackrel{‵}{D}{A}_2))}^{-1}(\left(A_1-A_2\right)X\hfill \\ & +\left(B_1-B_2\right)U)+\left(\left(C_1-C_2\right)X+\left(E_1-E_2\right)U\right)\hfill \end{array}$$

(57)

where I is the identity matrix, while the input voltage to the output voltage (input-to-output) transfer function G_vg(s) of the proposed multicell converter can be given as

$$\begin{array}{cc}\hfill G_{vg}\left(s\right)={\left.{\displaystyle \frac{{\tilde{v}}_o\left(s\right)}{{\tilde{v}}_{in}\left(s\right)}}\right|}_{\tilde{d}\left(s\right)=0}& \\ & =(D{C}_1+\stackrel{‵}{D}{C}_2){(sI-(D{A}_1+\stackrel{‵}{D}{A}_2))}^{-1}(D{B}_1+\stackrel{‵}{D}{B}_2)\hfill \\ & +(D{E}_1+\stackrel{‵}{D}{E}_2)\hfill \end{array}$$

(58)

Table 1. Parameters of the proposed single-switch two-cell boost converter.

Parameter	Value
Vin	24 V
Vo	132 V
rLi	0.64 Ω
Li	1.7 mH
rCi	0.12 Ω
Ci	47 µF
rCo	0.12 Ω
Co	47 µF
Fs	5 kHz
R	130 Ω
Diodes	MUR1560
Main switch (SW)	FGH40N60UFD

displays the parameters of the proposed single-switch two-cell boost DC-DC converter that are used for the simulation and experimental purposes.

Using Equation (57), the open-loop control-to-output transfer function G_vd(s) of the proposed two-cell boost converter is determined as

$$G_{vd}\left(s\right)={\displaystyle \frac{-0.2113s^5-7.348\times {10}^4{s}^4-7.793\times {10}^9{s}^3-2.379\times {10}^{14}{s}^2+2.022\times {10}^{18}s+9.906\times {10}^{20}}{s^5+1.783\times {10}^5{s}^4+8.049\times {10}^9{s}^3+8.928\times {10}^{12}{s}^2+1.529\times {10}^{16}s+5.981\times {10}^{18}}}$$

(59)

Using Equation (58), the open-loop input-to-output transfer function G_vg(s) of the proposed two-cell boost converter is determined as

$$G_{vg}\left(s\right)={\displaystyle \frac{26.45s^4+1.095\times {10}^7{s}^3+1.46\times {10}^{12}{s}^2+6.207\times {10}^{16}s+2.854\times {10}^{19}}{s^5+1.783\times {10}^5{s}^4+8.049\times {10}^9{s}^3+8.928\times {10}^{12}{s}^2+1.529\times {10}^{16}s+5.981\times {10}^{18}}}$$

(60)

5. Stability Analysis

As important measures of the converter stability, Figure 4 illustrates the bode plot diagram of the open-loop control-to-output transfer function G_vd(s) of the suggested two-cell boost converter, while the root locus diagram is shown in Figure 5. It is found that the gain margin G_m = −35.2 dB at phase crossover frequency F_cp = 403 Hz and phase margin P_m = −66.2° at gain crossover frequency F_cg = 6220 Hz, which refers to the instability. Also, as shown in Figure 5, there is a zero on the right half side of the s-plane.

Figure 6 illustrates the bode plot diagram of the open-loop input-to-output transfer function G_vg(s) of the proposed two-cell boost converter, while the root locus diagram is displayed in Figure 7. It is found that the phase margin P_m = 14.3° at gain crossover frequency F_cg = 483 Hz, which refers to the stability.

6. Experimental System Setup

To prove the validity of the developed SSAM of the proposed multicell converter, an experimental setup of the presented topology with two cells (n = 2) has been built and its performance has been compared with the simulated performance based on the SSAM of the suggested converter.

Figure 8 shows a photo of the actual experimental setup of the proposed single-switch two-cell boost DC-DC converter. It consists of a DC power supply (24 V, 20 A), a single-switch two-cell proposed boost DC-DC converter, a resistive load, a function generator (AFG-3051, 50 MHz, GW Instek, Taipei, Taiwan), a digital storage oscilloscope (TDS8204, 200 MHz, 2 GSa/s, Owon, Zhangzhou, China), a digital signal processor (DS1104, dSPACE, Paderborn, Germany), a voltage transducer (LV 25-p, LEM, Meyrin, Switzerland), and a drive circuit. The proposed converter is supplied from a DC source 24 V to supply a resistive load of 130 Ω by controlling the power switch pulses that come from the function generator with a switching frequency of 5 KHz. The oscilloscope is used to capture the voltage and current waveforms. The proposed converter circuit is examined in both open-loop and closed-loop operations. The schematic diagram for the experimental setup system is shown in Figure 9. This system shows the system structure for open-loop and closed-loop operations.

7. Open-Loop Performance

The proposed single-switch two-cell boost DC-DC converter is first examined in the open-loop operation. Figure 10 and Figure 11 show the comparison between the experimental and simulated SSAM open-loop performance of the proposed single-switch two-cell boost DC-DC converter at duty cycles D = 0.5 and D = 0.6, respectively. The simulation results are obtained using Matlab R2023b software. The steady-state average values of the variables (V_o, V_C1, i_L1, V_C2, and i_L2) of the SSAM of the suggested topology are compared to the corresponding experimental switching waveforms captured from the actual laboratory setup at steady state at the same input voltage V_in = 24 V. As shown in Figure 10, the SSAM simulation gives a theoretical average output voltage (V_o) of 114.54 V, while the output voltage of the experimental converter oscillates between 113 V and 117 V due to switching (experimental average of (113 + 117)/2 = 115 V). Therefore, the theoretical average (114.54 V) and the experimental average (115 V) of the output voltage are very close, which proves the SSAM validation. Also, the inductor currents (i_L1 and i_L2) are similar in experimental and simulation tests. The steady-state value of the simulated inductor current-based SSAM of the converter has a value of 1.76 A, while the steady-state experimental inductor current (i_L1 or i_L2) oscillates between 1.1 A and 2.6 A (experimental average of (1.1 + 2.6)/2 = 1.85 A). Moreover, the capacitors’ voltages (v_C1 and v_C2) are similar in experimental and simulation tests.

The steady-state simulated capacitor voltage has a value of 23.79 V, while the corresponding steady-state experimental capacitor voltage (v_C1 or v_C2) oscillates between 23.5 V and 24 V. Similar performances are obtained when the converter is operated at duty cycle D = 0.6, as shown in Figure 11. The SSAM smooths out the switching ripple inherent in the state variables of the experimental converter. Moreover, the comparison between the obtained simulation and experimental results validates the developed SSAM of the proposed converter.

8. Closed-Loop Performance

The experimental prototype of the proposed multicell converter (n = 2) is also examined during a closed-loop control. Converter stability and dynamic performance need to be improved by designing the PI controller. Consequently, the phase and gain margins by designing a robust feedback (closed-loop) controller are properly selected. A schematic diagram of the circuit that is utilized to control the output voltage of the proposed converter is shown in Figure 12.

8.1. PI Controller

The transfer function of the PI controller is given as

$$G_{PI}\left(s\right)={\displaystyle \frac{K_{P}s+K_I}{s}}$$

(61)

where K_P and K_I are the parameters of the PI controller. To obtain a stable and well-regulated DC-DC converter, the phase margin of the controlled converter should be greater than 45° [41]. A higher phase margin enhances the transient performance of the converter. A PI controller is designed to regulate the output voltage of the multi-cell DC-DC boost converter against load, input voltage, and reference voltage variations. The PI controller parameters are selected based on the stability analysis using the frequency response technique. The proportional (K_P) and integral (K_I) gains of the PI controller are selected to be K_P = 0.001 and K_I = 0.4 based on the required phase margin of 96.8° and gain margin of 15.3 dB. Figure 13 displays a bode plot of the closed-loop system with the designed PI controller. It is clear from the figure that the designed closed-loop control system is stable.

8.2. Closed-Loop Results

The experimental responses of the proposed multicell converter (n = 2) during closed-loop control are captured. Figure 14 shows the output voltage response starting with changing the reference voltage (V_ref) to 150 V at V_in = 24 V. It is observed that the output voltage signal has a good dynamic response and tracks the reference voltage smoothly without overshoots and undershoots. To examine the robustness of the closed-loop control of the proposed multicell converter (n = 2), Figure 15 demonstrates the output voltage and current responses by changing the resistive value of the load at V_ref = 140 V. Figure 16 presents the output voltage response at V_ref= 145 V by changing the input voltage (V_in) from 31 V → 24 V → 31 V. As obvious, the output voltage signal has a good dynamic response. Also, Figure 17 shows the output voltage response at V_in = 24 V by changing the reference voltage (V_ref) from 125 V → 115 V. The output voltage response tracks the reference voltage smoothly.

9. Comparison with Recent Converters

To evaluate the effectiveness of the single-switch high-gain multicell boost DC-DC converter, a comprehensive comparison between the proposed converter and previous boost converters is provided, as shown in

Table 2. Comparison between the two-cell proposed converter and recent topologies.

Item	Ref. [25]	Ref. [26]	Ref. [27]	Ref. [28]	Ref. [29]	Ref. [30]	The Proposed n = 2
Switch, SW	2	2	1	2	3	1	1
Inductor, L	4	3	4	2	6	3	2
Capacitor, C	1	3	6	2	1	7	3
Diode, D	9	2	3	2	11	5	4
Total Component Count	16	10	14	8	21	16	10
Gain, G	${\displaystyle \frac{(1+3D)}{(1-D)}}$	${\displaystyle \frac{D}{{(1-D)}^2}}$	${\displaystyle \frac{3D}{(1-D)}}$	${\displaystyle \frac{2}{(1-D)}}$	${\displaystyle \frac{(1+5D)}{(1-D)}}$	${\displaystyle \frac{(2+2D)}{(1-D)}}$	${\displaystyle \frac{(4-3D)}{(1-D)}}$
$\mathrm{Normalized}\mathrm{Voltage}\mathrm{Stress}\mathrm{on}\mathrm{the}\mathrm{SW}(V_{SW}/V_{in}$)	${\displaystyle \frac{(G+1)}{2G}}$	${\displaystyle \frac{G}{D}}$	${\displaystyle \frac{(G+3)}{3}}$	${\displaystyle \frac{G}{2}}$	${\displaystyle \frac{(G+2)}{3}}$	${\displaystyle \frac{(G+2)}{4}}$	$(G-1)$
$\mathrm{Normalized}\mathrm{Voltage}\mathrm{Stress}\mathrm{on}\mathrm{the}{D}_{\mathrm{o}}(V_{Do}/V_{in}$)	$G$	${\displaystyle \frac{G}{D}}$	${\displaystyle \frac{(G+3)}{3}}$	$G$	$(G+1)$	${\displaystyle \frac{(G+2)}{4}}$	$(G-1)$
Fs (KHz)	50	60	33	100	20	100	5
Open/Closed Loop	Open-loop	Open-loop	Open-loop	Open-loop	Open/Closed-loop	Open/Closed-loop	Open/Closed-loop
Control Method	n/a	n/a	n/a	n/a	PI Controller	Type III voltage controller	PI Controller
Exp. Efficiency (%) Pout = 100 W	n/a	n/a	93	92	95.6	92.1	96
Type of Load	Grounded	Grounded	Grounded	Grounded	Floating	Floating	Grounded
G at D = 0.4	3.67	1.11	2	3.33	5	4.67	4.67

. The number of components, which include switches, inductors, diodes, and capacitors, are presented for the proposed and other converters. It is obvious that the proposed converter has a smaller number of components compared to previous converters [25,27,29,30] and has an identical number of components as that reported in [26], and more than that in [28], which has the smaller count. Therefore, this converter topology structure contributes to a cost-effective system that is compact and lightweight compared to other topologies.

The table below also shows the relationships between the duty ratio (D) and voltage gain (G), normalized voltage stress on the SW ($V_{SW}/V_{in}$), normalized voltage stress on the D_o ($V_{Do}/V_{in}$), F_s (KHz), open/closed loop, control method, experimental efficiency at 100 W, and G at D = 0.4 for the proposed and other converter topologies. It can be seen that the voltage gain (G) at D = 0.4 gives a higher gain compared to previous works and is identical to that of the converter in [30]. However, the converter in [30] has a larger number of components compared to the proposed converter.

To provide deeper insight into, and analysis of, the proposed converter and previous converter works, Figure 18, Figure 19, Figure 20, Figure 21, Figure 22, Figure 23, Figure 24 and Figure 25 show plots based on the data in Table 2. In Figure 18, the voltage gain (G) under duty ratio changes (D) for the proposed converter and the prior converter topologies are plotted. As obvious, the proposed converter boasts a higher voltage gain compared to previous boosting converters for D ≤ 0.4. Additionally, the proposed converter demonstrates superior voltage gain even at very low duty cycles. This indicates that the suggested boost converter experiences lower switching and conduction losses, resulting in higher efficiency.

Figure 19 shows the normalized voltage stress on the SW ($V_{SW}/V_{in}$) versus the voltage gain. It is observed that the SW in the proposed converter experiences good voltage stress at high voltage gain compared to the power switches in previous converters. It can be seen that the previous converter topologies with low voltage stress have a large number of components, as in [25,27,29,30]. Additionally, the proposed converter topology has a reasonable voltage stress compared to the converters in [26,28], which have nearly the same number of components. In Figure 20, the voltage stress on the diode in the proposed converter has a moderate value compared to the diodes in the previous converters. This comparison proves the improved performance of the proposed converter and stress reduction.

In Figure 21, Figure 22, Figure 23, Figure 24 and Figure 25, the duty ratio is plotted versus gain to total component count ratio (G/N), gain to switch count ratio (G/N_SW), gain to diode count ratio (G/N_D), gain to diode count ratio (G/N_D), gain to inductor count ratio (G/N_L), and gain to capacitor count ratio (G/N_C) for the proposed converter and the prior converter works. As is obvious, the proposed converter exhibits higher gain compared to previous converters concerning the number of components. The proposed converter shows a higher gain compared to previous converter works, particularly for D ≤ 0.5.

Therefore, the proposed converter is appropriate for renewable energy applications that require variable and constant high output voltage with a wider range of duty ratios. This converter topology structure contributes to a cost-effective system that is compact and lightweight compared with other topologies. It compromises between the required performance, the low number of components, low voltage stress on the components, high efficiency, and cost-effectiveness.

10. Conclusions

This paper presented the state space average model of a new single-switch multicell high-gain boost DC-DC converter considering the series parasitic resistances of the passive elements operating in CCM. Based on the state space average model, a small signal model of the proposed converter was introduced. The control-to-input and input-to-output open-loop transfer functions of the offered converter have been derived and presented. The behavior of the proposed topology based on the state space average model was obtained using Matlab R2023b software. The stability analysis of the suggested topology using a bode plot and root locus diagrams was investigated. The PI controller parameters for closed-loop control of the proposed converter were designed. Simulation results of the converter state space average model have been verified by comparing with the corresponding experimental results for actual hardware of the proposed converter with two cells for open-loop and closed-loop operations. It was found that the derived state space average and small signal models of the proposed multicell boost converter are convenient and accurate. These developed models can be considered as effective tools for studying dynamic performance, investigating stability, and designing control of the proposed converter. Based on the experimental results, the proposed converter has a fast dynamic response during starting, load change, input voltage, and reference voltage variations. A comprehensive comparison between the proposed converter and previous converters found that the proposed converter exhibits higher gain compared to previous converters with respect to the number of components. This converter’s topology contributes to a cost-effective system that is compact and lightweight compared with other topologies. It compromises between the required performance, the low number of components, low voltage stress on the components, and cost-effectiveness.