Optimized Preventive Diagnostic Algorithm for Assessing Aluminum Electrolytic Capacitor Condition Using Discrete Wavelet Transform and Kalman Filter

Abstract

Power converters (PCs) are vital elements of critical applications, making their reliable operation crucial. Enhancing PCs’ reliability can be achieved by adding intelligence to the system, enabling it to predict failures and generate early warnings before a failure occurs. In this context, intelligence is integrated into the system through preventive diagnostic algorithms (PDAs) that assess the converter condition. This article introduces a PDA designed to determine the optimal replacement timing for aluminum electrolytic capacitors (AECs) within power converters. AECs, in addition to being a fundamental component of PCs, also represent the most vulnerable element of the PCs’ power section. The aging of AECs is characterized by a decrease in capacitance (C) and an increase in the equivalent series resistance (ESR). Therefore, ESR and C serve as key indicators for assessing the AECs’ health status. One of the most critical functional requirements for designing a PDA is its accuracy, which can be significantly affected by transients. The solution proposed in this paper is resilient to transients, overcoming a common problem in implementing AECs’ PDAs. The proposed algorithm employs discrete wavelet transform (DWT) to extract the converter signal modes. Subsequently, key characteristics of these modes are extracted, enabling the calculation of both ESR and C. Finally, by using the estimated ESR and C values, two fault indicators can be obtained that are resilient to transients. Employing a Kalman filter reduces noise and ensures the indicators’ resilience to transients, making them highly effective for evaluating the AECs’ health status. The proposed PDA was validated through multiple computer simulations conducted in MATLAB/Simulink for a three-phase interleaved boost converter (3ϕIBC), which includes a proportional-integral (PI) controller with anti-windup capability.

1. Introduction

Power electronic converters are essential in various industries, including transportation, energy transmission, and domestic appliances. Reliable operation is critical to maintaining these systems’ functionality [1]. Enhancing reliability often involves using high-quality components, robust converter designs, and integrating fault detection and condition monitoring systems [2]. These procedures ensure consistent and efficient performance across applications.

DC-DC converters are pivotal in energy conversion, extensively used in battery interfacing, solar and wind energy integration, and hybrid systems, highlighting the adaptability of power electronics technology [2,3]. High-step gain DC-DC converters are crucial for integrating renewable energy sources with the grid, as they boost low DC voltages before feeding them into grid-connected inverters [4,5]. In AC motor drive systems powered by batteries, parallel-connected, modular-current-fed, bidirectional DC-DC converters are extensively employed [6,7]. The adoption of battery-powered electrical drives, particularly in electric vehicles (EVs) and servo systems, has surged [8]. Efficient energy systems rely on robust power converters, particularly in renewable energy and hybrid vehicles, where robust control strategies ensure fault-tolerant operation. Interleaving techniques, notably in the interleaved boost converter (IBC), mitigate significant drawbacks, such as voltage and current ripples, enhancing efficiency and reliability [9]. The IBC, comprising multiple parallel-connected boost converters, offers advantages, such as reduced switching losses and compactness, making it suitable for advanced applications [7].

Condition-monitoring techniques for power electronic systems are classified into offline, quasi-online, and online methods. Offline techniques require system interruptions to acquire health indicators, which can be disruptive to normal operations and may lead to downtime. Quasi-online methods, on the other hand, gather health indicators during routine pauses in the system’s operation, minimizing disruption but still causing periodic interruptions [10,11]. Despite their effectiveness, both offline and quasi-online methods can compromise system reliability and efficiency due to these interruptions [12,13]. Online techniques provide continuous monitoring of the system without requiring interruptions, thus maintaining system reliability and operational efficiency. These techniques typically involve the use of specialized electrical circuits that can monitor the health of components, such as AECs, in real time [7,14,15,16]. However, the need for custom-designed monitoring circuits tailored to specific applications can significantly increase the overall system cost.

AECs are essential in power electronic converters, influencing the converter cost, size, and failure rates [2]. AECs are prevalent due to their high energy density and cost-effectiveness [16]. However, AECs are prone to aging and are a leading cause of converter failures. They are commonly employed for regulating input and output power owing to their substantial capacitance, high voltage capacity, and cost-effectiveness [17,18]. Despite their widespread use, AECs are vulnerable components [11,19], prompting extensive research into their condition monitoring. Studies indicate that AEC failure often correlates with doubled equivalent series resistance (ESR) or a 20% decrease in capacitance (C) from initial values [20,21]. ESR is considered a reliable indicator of AEC health, leading to the proposal of various online ESR estimation methods [18,22]. While ESR minimally impacts output voltage at line frequencies, it significantly affects AEC voltage ripple. For example, the authors of [23] correlated sampled switching ripple with capacitor current for ESR estimation, albeit relying on load parameters.

Most proposed approaches for AEC fault diagnostics rely on monitoring ESR and C [24]. Real-time online models for estimating ESR and C are typically based on evaluating the capacitor’s ripple voltage. A condition-monitoring approach for industrial power converters was presented in [25], using an ESR estimation circuit that requires only a few op-amps, passive components, and a low-cost microcontroller. The method for monitoring electrolytic capacitors’ conditions in [26] assessed impedance at double-grid frequency (100 Hz) and was applied to a single-phase grid-connected PV system with grid power fluctuations at double-main-grid frequency. Another approach for fault detection, discussed in [27], used ESR, C, and other parameters.

A technique for detecting capacitor aging in the output stage of a step-down DC-DC converter was proposed in [28], which analyzed the dynamic response of the output voltage concerning capacitance reduction. An online technique for monitoring AEC conditions in a PV system connected to a single-phase network was described in [10]. This method inserted a harmonic frequency current into the network overnight via a solar inverter and measured capacitor impedances at various frequencies. The least mean square (LMS) technique was then used to estimate ESR and C values based on these impedance measurements.

In [29,30], an innovative online system for monitoring C and ESR in the output electrolytic capacitor of a DCM flyback converter was detailed. A non-invasive technique for estimating the output capacitor characteristics of a flyback converter was proposed in [30]. The approach in [31] allowed precise determination of a capacitor’s temperature, applying core temperature and ESR measurements to monitor AEC conditions. An online fault detection technique based on a state observer mechanism was presented in [32], while ref. [33] proposed an online ESR estimation technique for a boost converter’s output capacitor, using only the output voltage ripple and inductor current.

Specific equations for calculating ESR and C of AECs in power converters are often tailored to particular converter topologies, limiting their applicability across different types of converters [28,33]. The online ripple method, which estimates ESR and C by analyzing voltage and current ripples, can be effective but may experience inaccuracies during transients [34].

To address these challenges, this paper proposes a novel fault diagnosis technique (FDT) aimed at overcoming the challenges associated with assessing the health status of AECs in power converters, especially under conditions influenced by transients and noise. The proposed FDT employs the discrete wavelet transform (DWT) to extract the converter signal modes. From these modes, key features are derived, enabling the calculation of both ESR and C. Finally, the estimated ESR and C values are then used to obtain two failure indicators that demonstrate exceptional resilience to transients. Additionally, a Kalman filter is employed to enhance signal fidelity, ensuring robust estimation even in complex scenarios that affect control stability. These precise estimates are crucial for developing reliable preventive diagnostic algorithms (PDAs) that can predict failures and optimize the replacement timing of AECs. The efficacy of the proposed technique is validated through extensive simulations conducted in MATLAB/Simulink on a 3ϕIBC, demonstrating its potential to significantly improve the reliability and efficiency of power electronic systems. The following sections detail the methodology, simulation results, and implications of this research, contributing to the advancement of condition monitoring and fault diagnosis in power electronics.

2. Three-Phase Interleaved Boost Converter (3ϕIBC)

Figure 1 illustrates the proposed three-phase non-isolated interleaved boost converter utilized in this study. The choice of the number of converter phases is crucial for factors such as power conversion efficiency, cost, and control complexity [2].

Opting for a three-phase interleaved boost converter strikes a balance between simplicity and effective power management. The converter input current comprises the sum of each phase current:

$$I_{in}=I_1+I_2+I_3$$

(1)

Referring to Equation (1), the derivative of the converter input current, denoted as ${\displaystyle \frac{d{I}_{in}}{dt}}$, is the summation of the derivatives of each individual phase:

$${\displaystyle \frac{d{I}_{in}}{dt}}={\displaystyle \frac{d{I}_1}{dt}}+{\displaystyle \frac{d{I}_2}{dt}}+{\displaystyle \frac{d{I}_3}{dt}}$$

(2)

Considering the identical characteristics of all phases, the analysis will focus on a single converter phase. During the conduction of the power switch, SW₁, the derivative of the inductor current, represented as ${\displaystyle \frac{d{I}_1}{dt}}$, can be expressed as:

$${\displaystyle \frac{d{I}_1}{dt}}={\displaystyle \frac{V_{in}}{L_1}}$$

(3)

Meanwhile, during the switch’s OFF state, the derivative of the current passing through the inductor, denoted as ${\displaystyle \frac{d{I}_1}{dt}}$, is expressed as:

$${\displaystyle \frac{d{I}_1}{dt}}={\displaystyle \frac{V_{in}-V_{out}}{L_1}}$$

(4)

Considering the ideal model of the interleaved boost converter, the voltage gain can be represented as follows:

$${\displaystyle \frac{V_{in}}{V_{out}}}={\displaystyle \frac{DM}{DM-D}}$$

(5)

where DM represents the period of non-zero inductor current and D denotes the duty cycle. Assuming uniform components across all converter phases, general expressions of the input current derivative can be derived for each interval within a switching period, utilizing Equations (2)–(5). Intervals are defined and bounded considering the number of converter switches simultaneously active. The performance of the used three-phase interleaved boost converter is critically defined by its input voltage (V_in) of 30 V, output voltage (V_out) of 80 V, and a maximum output current (I_out,max) ranging from 1.6 A to 2.6 A, which corresponds to a power output (P_omax) between 128 W and 208 W depending on the load conditions. The converter utilizes inductors with a value of 10 mH, a key component in determining its performance under varying operational scenarios. These parameters are essential for the accurate design and simulation of the converter in models such as Simulink. The converter’s operation is highly sensitive to varying conditions, including changes in load, the health state of input/output capacitors, and fluctuations in the C and ESR of the DC-link capacitor. Under nominal conditions, the converter effectively boosts the input voltage to the desired output, ensuring efficient power delivery. However, variations in load can alter the output current, impacting both the power output and the overall efficiency of the system. Additionally, while capacitors with optimal capacitance and low ESR contribute to minimal voltage ripple and stable energy transfer, degraded capacitors can lead to increased ripple, reduced efficiency, and potential instability. Therefore, regular monitoring and maintenance of these components are crucial to maintaining reliable operation and extending the lifespan of the converter.

3. Signal Modes’ Decomposition

The voltage and current signals within the capacitor play a crucial role in assessing its overall health status [34,35]. These signals can be viewed as a stochastic process, comprising three fundamental components:

• A component that incorporates the signal trend and reflects the DC component of the signal, DC(t). From a practical point of view, this component evolves depending on the operating conditions.
• A component encompassing the repetitive nature of the signal, encapsulating all the diverse frequencies intrinsic to the signal (AC(t)). This component, which can further be divided into N subcomponents (ac_i(t)), is inherently related to the converter’s operating mode and control response.
• A component embodying the random fluctuations within the signal, often denominated as noise (N(t)).

Equation (6) mathematically represents the relationship between the original signal and the three aforementioned components:

$$signal\left(t\right)=DC\left(t\right)+AC\left(t\right)+N\left(t\right)$$

(6)

$$AC\left(t\right)={\sum }_{i=1}^N{ac}_i\left(t\right)$$

The decomposition of signals (DSs) into simpler components, alternatively referred to as signal modes, proves to be fundamental from a systems analysis point of view. The DSs is essential for tasks such as system design, performance optimization, or fault diagnosis.

In order to derive the signal modes, various methods can be employed, with two notable ones being the Fourier transform (FT) and the wavelet transform (WT) [35,36,37,38,39,40,41,42].

3.1. Fourier Transform

The FT, calculated using Equation (7), serves as a mathematical tool for extracting the AC modes within a signal. It accomplishes this by projecting the original signal into an orthogonal system comprising of sines and cosines with different frequencies, often referred to as harmonics. Using this technique, it becomes possible to extract frequency domain information from a signal, including the frequencies present and their associated amplitudes. Yet, the FT lacks the capability to pinpoint the specific times when various frequencies within the signal occur; therefore, this method is best suited for analyzing stationary signals:

$$F_{FT}\left(\omega \right)={\int }_{-\infty }^{+\infty }f\left(t\right)·e^{-i·\omega ·t}dt,\omega \in \mathbb{R}$$

(7)

where $F_{FT}\left(\omega \right)$ represents the frequency representation of the signal $f\left(t\right)$, represented in the time domain, $\omega =2·\pi ·freq$ denotes the angular frequency in radians/s, freq represents the frequency in Hz, and $i=\sqrt{-1}$ [42].

3.2. Short-Time Fourier Transform

Aiming to enhance time resolution, a novel approach, known as the short-time Fourier transform (STFT) was introduced, which offers a combined representation of both time and frequency of the signal. In the STFT, which can be computed through (8), the signal is segmented into small temporal intervals denominated as frame windows. The signal within the frame window (SFW) is derived by multiplying the original signal by a window function, usually the Gaussian window or a Hann window, specifically designed to address the challenges related to spectral leakage [37,38]. Subsequently, the FT is applied exclusively to the SFW. This iterative process is extended to encompass all frame windows within the signal. In practical implementation of the STFT, frame overlap is commonly used, with the hop size directly influencing the temporal resolution of the STFT output [38]:

$$F_{STFT}\left(\tau ,\omega \right)={\int }_{-\infty }^{+\infty }f\left(t\right)·win\left(t-\tau \right)·e^{-i·\omega ·t}dt$$

(8)

where $F_{STFT}\left(\tau ,\omega \right)$ represents the STFT of the signal $f\left(t\right)$ at time $\tau$ and angular frequency $\omega$, and $win\left(t-\tau \right)$ represents the window function [37,38].

The STFT enhances temporal resolution but sacrifices frequency resolution. Additionally, the SFW is regarded as a stationary signal. Hence, determining the window size is crucial for optimizing this method. Wide windows enhance frequency resolution but degrade time resolution, whereas narrow windows enhance time resolution but provide poor frequency resolution. The unpredictable nature of the converter’s operational conditions poses challenges in predicting transient durations, which makes the selection of the ideal window size particularly difficult.

3.3. Wavelet Transform

Heisenberg’s uncertainty principle states that pinpointing exact frequencies at any given instant of time in a signal is impossible [37]. However, the STFT demonstrates that it is viable to recognize the frequency bands within specific time intervals. Hence, optimizing these time intervals, or window lengths, is crucial [39].

On the other hand, it is worth mentioning that in the 3ϕIBC, the capacitor current and voltage waveforms, crucial for evaluating the AEC health status [34,35], consist of high-frequency (HF) and medium-frequency (MF) components. The switching frequency of the transistors, f_SW, contributes to the MF component, whereas the interleaving effect among the three phases contributes to a HF component that is three times f_SW (3 × f_SW).

HF component signals, with their short time duration, demand high temporal resolution, necessitating a narrow window length. Conversely, low-frequency (LF) component signals, characterized by longer durations, require HF resolution, thus necessitating a wide window.

In this context, WT emerges, enabling the analysis of a signal across various frequencies with varying levels of resolution, known as multiresolution analysis [39,40,41].

3.3.1. Wavelet Functions

The essence of WT lies in the utilization of wavelet functions [40]. Unlike the sine and cosine functions employed in the Fourier transform (Figure 2a), which stretch infinitely, wavelet functions represent signals with brief, localized oscillations in time (Figure 2b), making them especially well-suited for non-stationary signals with unpredictable behaviors.

When implementing the WT, a family of wavelets stemming from a single mother wavelet is employed [40]. These wavelets share a common shape but vary in length, as defined in Equation (9). The purpose of the longer wavelets is to capture the signal LF modes, while shorter wavelets are responsible for extracting the signal HF modes:

$${\psi }_{s,\tau }\left(t\right)={\displaystyle \frac{1}{\sqrt{s}}}·\psi \left({\displaystyle \frac{t-\tau }{s}}\right);s,\tau \in \mathbb{R}$$

(9)

where $\psi \left(t\right)$ represents the mother wavelet, ${\psi }_{s,\tau }$ signifies a specific member of the wavelet family, $s$ denotes the scale parameter dictating the width of the wavelet, and $\tau$ serves as the translation parameter determining the wavelet’s position along the time axis [40].

3.3.2. Continuous Wavelet Transform

The continuous WT (CWT) of a signal, $f\left(t\right)$, with respect to a mother wavelet, $\psi \left(t\right)$, can be expressed as:

$$F_{CWT}\left(\tau ,s\right)=〈f,{\psi }_{s,\tau }〉={\displaystyle \frac{1}{\sqrt{\left|s\right|}}}{\int }_{-\infty }^{+\infty }f\left(t\right)·{\psi }^{*}\left({\displaystyle \frac{t-\tau }{s}}\right)dt;s={\displaystyle \frac{2·\pi }{\omega }}$$

(10)

where $F_{CWT}\left(\tau ,s\right)$ represents the CWT coefficients at scale s and translation $\tau$, and ${\psi }^{*}$ denotes the complex conjugate of $\psi \left(t\right)$ [39].

Equations (9) and (10) depict how the different members of the wavelet family ($\left\{{\psi }_{s,\tau }\right\}$) undergo a time axis displacement (τ). Conversely, the family’s different members result from adjusting the scale factor s, enabling the stretching or compression of the mother wavelet. Since s is inversely proportional to frequency, larger values of s produce low-frequency wavelets, while smaller values yield high-frequency wavelets. The inner product (10) measures the similarity between $f\left(t\right)$ and the different members of $\left\{{\psi }_{s,\tau }\right\}$, thereby enabling the extraction of various modes inherent in the original signal ($f\left(t\right)$).

3.3.3. Discrete Wavelet Transform

Yet, computing $F_{CWT}\left(\tau ,s\right)$ for all potential scaling factors poses a significant computational burden [39]. However, if the coefficients s and $\tau$ are discretized, the analysis becomes significantly more computationally efficient, giving rise to the discrete wavelet transform (DWT) [39]. Therefore, DWT is computed by discretizing the coefficients s and $\tau$ of the CWT in powers of 2, which is why it is also known as the dyadic wavelet transform [41,43]. Hence, the DWT of a signal, $f\left(t\right)$, with respect to a mother wavelet, $\psi \left(t\right)$, can be expressed as:

$$F_{DWT}\left(j,k\right)={\displaystyle \frac{1}{\sqrt{2^j}}}{\int }_{-\infty }^{+\infty }f\left(t\right)·{\psi }^{*}\left({\displaystyle \frac{t-{k·2}^j}{2^j}}\right)dt;$$

(11)

where $j$, $k$, and ${\psi }^{*}$ represent the scaling parameter, translation parameter, and the complex conjugate of $\psi$ [43].

Equation (11) defines a dyadic-orthonormal wavelet transform, which serves as the foundation for multiresolution analysis (MRA), which is the framework for examining signals at different levels of detail (resolution) [41,43].

3.3.4. Multiresolution Analysis (MRA)

In MRA, the original signal, x[n], can be decomposed into its approximations, represented by a scale function, ${\varphi }_{j,k}\left(t\right)$, and its details, represented by a wavelet function, ${\psi }_{j,k}\left(t\right)$ [43]:

$${\varphi }_{j,k}\left(t\right)=2^{-{\displaystyle \frac{j}{2}}}\varphi \left(2^{-j}t-k\right)$$

(12)

$${\psi }_{j,k}\left(t\right)=2^{-{\displaystyle \frac{j}{2}}}\psi \left(2^{-j}t-k\right)$$

(13)

where $j$ and $k$ are integers.

The scaling function is associated with a low-pass filter (LPF), while the wavelet function is related to a high-pass filter (HPF). Both filters are constructed from ${\varphi }_{j,k}\left(t\right)$ and ${\psi }_{j,k}\left(t\right)$ [43]. Therefore, it can be concluded that the DWT allows for the decomposition of a signal, x[n], into various frequency bands through the use of LPF (h[n]) and HPF (g[n]), as illustrated in Figure 3 [39,41]. This process is referred to as analysis.

Figure 3 shows that, during the analysis stage, the DWT generates both LF and HF information. The first approximate to the original signal and, therefore, are referred to as approximation coefficients (CA). Conversely, the HF information captures the details of the original signal, and hence is denominated as detail coefficients (CD).

The MRA can be depicted as a series of successive, hierarchically arranged filter banks (Figure 3). By utilizing MRA, the CA (a_j,k) and CD (b_j,k) between two adjacent levels can be computed, as follows [43]:

$$a_{j,k}={\sum }_{n}h\left[n-2k\right]a_{j-1,n}$$

(14)

$$d_{j,k}={\sum }_{n}g\left[n-2k\right]a_{j-1,n}$$

(15)

where $a_{j,k}$ and $d_{j,k}$ represent the CA and CD of the signal at level j.

Hence, the original signal can be reconstructed, as follows [44]:

$$x\left(t\right)={\sum }_{k\in N}{a}_{J,k}{\varphi }_{J,k}\left(t\right)+{\sum }_{j\le J}{\sum }_{k\in N}{d}_{j,k}{\psi }_{J,k}\left(t\right)$$

(16)

where N represents an integer, $a_{J,k}$ represents CA, $d_{j,k}$ signifies the CD, ${\varphi }_{J,k}\left(t\right)$ denotes the scaling function, and ${\psi }_{J,k}\left(t\right)$ represents the wavelet function.

As previously mentioned, the decomposition process is iterative (Figure 3), with the upstream CA_i breaking down into a downstream CA_i+1 and CD_i+1. This decomposition into a tree represents a set of bandpass filters, with the frequency bands illustrated in Figure 4.

From Figure 4, it can be inferred that CD_N contains the signal mode corresponding to the HF within the interval [2^−(N+1) × f_s, 2^−N × f_s] Hz, where f_s represents the sampling frequency. Conversely, CA_N contains the LF components of the signal within the interval [0, 2^−(N+1) × fs] Hz.

4. Preventive Diagnostic Algorithm

As discussed in the introduction, AECs are among the most vulnerable components in power converters. Therefore, it is crucial to develop preventive diagnostic algorithms (PDAs) that can evaluate the AECs’ health status during the converter’s operation.

AECs can experience two types of failures: catastrophic and parametric [2]. Catastrophic failures result in the complete destruction of the capacitor, manifesting as either a short circuit or an open circuit, which significantly impacts converter performance.

Parametric failures occur before catastrophic ones and are noticeable by an increase in the capacitor’s internal resistance (ESR) and a decrease in capacitance (C). The likelihood of a catastrophic failure rises sharply if the ESR or C values reach critical limits. These critical limits are defined as twice the ESR value of a sound (healthy) capacitor (ESR_sound) or 80% of its original capacitance (C_sound). Thus, it is crucial to estimate both the ESR and C values of the capacitor during converter operation.

4.1. Fault Indicators

It is important to note that diagnosing the health status of AECs does not require highly precise estimations of the ESR and C parameters. The key functional requirement is the accuracy of the relationship between the estimated values for sound and aged capacitors. These relationships can be represented as follows, with ESR_tC and C_tC being the current values of ESR and C, respectively:

$${Ratio}_{ESR}={\displaystyle \frac{{ESR}_{tC}}{{ESR}_{sound}}}$$

(17)

$${Ratio}_C={\displaystyle \frac{C_{tC}}{C_{sound}}}$$

(18)

where ${Ratio}_{ESR}$ represents the relationship between the current estimated ESR value and the ESR value of a sound capacitor, with ${Ratio}_C$ representing the same relationship for the capacitance value.

Failure indicators (17) and (18) were proposed, taking into account the criteria that define the AEC end-life limit suggested by manufacturers [45]. Therefore, if Ratio_ESR exceeds 2 or Ratio_C falls below 0.8, it indicates that the critical limit has been reached. Consequently, the probability of a catastrophic failure increases significantly, and it is advisable to replace the AEC.

4.2. Capacitor Impedance

The equivalent circuit of an AEC consists of an ideal resistance (ESR), an ideal capacitor (C), and an ideal inductance (ESL), all in series. Typically, the ESL value can be neglected because its effect is negligible at the converter’s operating frequency, leaving ESR and C as the primary components [23]. Hence, the capacitor impedance (Z_AEC) can then be calculated, as follows:

$$Z_{AEC}=\sqrt{{ESR}^2+{X_C}^2}=\sqrt{{ESR}^2+{\left({\displaystyle \frac{1}{w·C}}\right)}^2}$$

(19)

In order to illustrate how the Z_AEC changes with frequency, a graph is presented in Figure 5 showing the capacitor impedance evolution for a sound capacitor (C = 330 µF and ESR = 0.2 Ω).

Figure 5 shows that at LF, the X_C value is the primary contributor to Z_AEC, while at HF, the ESR becomes the dominant factor. This observation formed the foundation for developing the offline measurement technique proposed in [46], which can simultaneously estimate the AEC ESR and C by measuring just Z_AEC.

The solution proposed in this article builds upon the solution presented in [46], making the necessary modifications for online application.

At a higher level of abstraction, the proposed PDA utilizes the WT to filter the voltage and current signals in the capacitor at HF and MF. Following this, the capacitor impedance is computed at HF and MF frequencies. Finally, by using the HF impedance and MF impedance, together with the corresponding frequencies, it is possible to estimate the AEC ESR and C values.

Before explaining the computation of both ESR and C, it is important to define how capacitor impedance is determined. As mentioned in the previous section, the current and voltage waveforms in the capacitor are initially filtered using the WT, so it is crucial to identify the frequency ranges for which this filtering occurs.

Figure 4 illustrates the frequency bands where WT performs filtering. Therefore, using Figure 4 and knowing the value of the converter’s switching frequency (f_sw = 5 kHz), it is possible to identify the detail coefficient 5 (CD5) as the one that covers the MF signal mode. However, in a 3ϕIBC, the frequencies that appear at the converter output are multiples of the f_SW, notably the 3 × f_SW. The 3 × f_SW frequency results from phase interleaving, which reduces the output voltage ripple and enhances the converter’s overall performance. Therefore, the HF signal mode will be captured by the detail coefficient 3 (CD3) since it includes the 3 × f_SW (3 × f_SW = 15 kHz) frequency.

Following this, the frequency bands corresponding to each of the mentioned detail coefficients are presented:

$${CD}_i\in \left[{\displaystyle \frac{f_s}{2^{i+1}}},{\displaystyle \frac{f_s}{2^i}}\right]\Rightarrow \left\{\begin{array}{c}{CD}_3\in \left[{\displaystyle \frac{f_s}{2^4}},{\displaystyle \frac{f_s}{2^3}}\right]\\ {CD}_5\in \left[{\displaystyle \frac{f_s}{2^6}},{\displaystyle \frac{f_s}{2^5}}\right]\end{array}\right.$$

(20)

The capacitor current and voltage signal sampling frequency, f_S, was 200 kHz. Consequently, the corresponding frequency bands are:

$$\left\{\begin{array}{c}{f}_s=200\mathrm{kHz}\\ {CD}_3\in \left[{\displaystyle \frac{\mathrm{200,000}}{16}},{\displaystyle \frac{\mathrm{200,000}}{8}}\right]=\left[12.5\mathrm{kHz},25\mathrm{kHz}\right]\\ {CD}_5\in \left[{\displaystyle \frac{\mathrm{200,000}}{64}},{\displaystyle \frac{\mathrm{200,000}}{32}}\right]=\left[3.125\mathrm{kHz},6.25\mathrm{kHz}\right]\end{array}\right.$$

(21)

Once the frequency bands have been identified, it is possible to calculate the frequency corresponding to a specific band by calculating the average:

$$f_3={\displaystyle \frac{\frac{f_s}{2^4}+\frac{f_s}{2^3}}{2}}={\displaystyle \frac{25\mathrm{kHz}+12.5\mathrm{kHz}}{2}}=18.75\mathrm{kHz}$$

(22)

$$f_5={\displaystyle \frac{\frac{f_s}{2^6}+\frac{f_s}{2^5}}{2}}={\displaystyle \frac{6.25\mathrm{kHz}+3.125\mathrm{kHz}}{2}}=4.6875\mathrm{kHz}$$

(23)

Finally, the impedance is calculated, as follows:

$$Z_{AEC3}=Z_{AEC}\left(f_3\right)={\displaystyle \frac{RMS\left(V_{DC3}\right)}{RMS\left(I_{DC3}\right)}}$$

(24)

$$Z_{AEC5}=Z_{AEC}\left(f_5\right)={\displaystyle \frac{RMS\left(V_{DC5}\right)}{RMS\left(I_{DC5}\right)}}$$

(25)

where RMS represents the root mean square value, $V_{DC3}$ and $V_{DC5}$ represent the CD3 and CD5 of capacitor voltage, and $I_{DC3}$ and $I_{DC5}$ represent the CD3 and CD5 of capacitor current, respectively.

4.3. Computing ESR and C from Capacitor Impedance

After determining the impedance and frequency, the ESR and C values can be calculated using two different algorithms: Algorithms 1 and 2.

The first and simplest solution, Algorithm 1, assumes that X_C is negligible at f₃ (f₃ = 18.75 kHz). Hence, ESR and C can be calculated, as follows:

$$ESR=Z_{AEC3}$$

(26)

$$C={\displaystyle \frac{1}{2·\pi ·f_5·\sqrt{{Z_{AEC5}}^2-{Z_{AEC3}}^2}}}$$

(27)

The second solution, Algorithm 2, does not consider X_C negligible at f₃, and ESR and C can be calculated, as follows:

$$ESR=\sqrt{{\displaystyle \frac{{\left(\frac{Z_{AEC3}}{2·\pi ·f_5}\right)}^2-{\left(\frac{Z_{AEC5}}{2·\pi ·f_3}\right)}^2}{{\left(\frac{1}{2·\pi ·f_5}\right)}^2-{\left(\frac{1}{2·\pi ·f_3}\right)}^2}}}$$

(28)

$$C=\sqrt{{\displaystyle \frac{{\left(\frac{1}{2·\pi ·f_5}\right)}^2-{\left(\frac{1}{2·\pi ·f_3}\right)}^2}{{\left(Z_{AEC5}\right)}^2-{\left(Z_{AEC3}\right)}^2}}}$$

(29)

4.4. Methodology for Implementing the Proposed Solution

Before delving into the detailed description of the proposed solution, it is essential to present the general scheme of the proposed PDA, which will serve as a reference point going forward (Figure 6).

Following this, a more detailed description of the methodology used to implement the proposed PDA will be provided.

Initially, it was necessary to obtain the voltage and current waveforms in the capacitor. Consequently, several simulations of a 3ϕIBC were conducted on the MATLAB/Simulink platform. Each simulation represented the scenarios outlined in

Table 1. Test scenarios.

Scenarios	Vref (V)	ESR (Ω)	C (µF)	Load Variation
				ILoad (A) [t < t1]	ILoad (A) [t > t1]
1	80	0.2	330	1.6 A (t1 = 2 s)	2.4 A (t1 = 2 s)
2		0.4	264
3		0.2	330	0.8 A (t1 = 2 s)
4		0.4	264
5		0.2	330	1.07 A (t1 = 2 s)	1.7 A (t1 = 2 s)
6		0.4	264
7		0.2	330	0.64 A (t1 = 2 s)
8		0.4	264
9		0.1	1100	1.6 A (t1 = 1.5 s)	2.4 A (t1 = 1.5 s)
10		0.15	950
11		0.2	800

, reflecting the converter operation represented in Figure 6, which included a PI controller with anti-windup capability.

The scenarios presented in the previous table considered sound AECs (ESR_Sound and C_Sound), AECs with intermediate aging (1.5 × ESR_Sound and 0.86 × C_Sound), AECs at their useful life limit (2 × ESR_Sound and 0.8 × C_Sound), and AECs whose useful life limit was exceeded (2 × ESR_Sound and 0.73 × C_Sound).

Figure 7, Figure 8, Figure 9, Figure 10 and Figure 11 show the voltage and current waveforms in the capacitor as well as the load current for the eleven scenarios depicted in Table 1.

By analyzing the previous figures, it is evident that the control system responded adequately to load requests. It is important to note that estimating the AEC’s health condition becomes particularly critical during the converter’s transient periods, as demonstrated in [35]. Therefore, the proposed solution will be evaluated not only during the steady-state regime [14] but also during the transient regime, including one of the most critical scenarios: the converter startup.

After the signal acquisition, the next step involved raw data processing, commencing with the application of the wavelet transform (WT) to the raw data. In this research, the parameters required for processing DWT included the mother wavelet DB30 (Figure 2b) and a decomposition level of five. When choosing the mother wavelet, consideration was given to three types (Daubechies, Coiflets, and Symlets), as well as the number of vanishing moments. After conducting multiple tests on the analyzed signals, it was determined that DB30 exhibited superior performance compared to the other mother wavelets.

Subsequently, it was proceeded to the analysis stage in order to obtain the detail coefficients from 2 to 5 of capacitor voltage and current waveforms (Figure 6—DWT filtering module). Once the analysis stage was completed, the synthesis stage was carried out in order to obtain MF and HF signals modes. As explained in Section 4.2, the MF modes were obtained exclusively using CD5, which is why the other detail coefficients were cancelled (Figure 6—DWT filtering module). A similar procedure was applied to the HF mode signals, only retaining CD3 (Figure 6—DWT filtering module).

The output signals of the DWT filtering module contain the spectral components of interest. Therefore, the next step was to extract the relevant information from these signals. Hence, the temporal scope of signal analysis was defined with a window size (WS) of 1000 samples and a hop size (HS) of 500 samples. The combination of a WS of 1000, representing a window with 25 signal periods, and an HS of 500, allowing 2 consecutive windows to overlap, increased the PDA resilience to transients.

Afterwards, for each frame window, the root mean square (RMS) value was calculated:

$${RMS}_j=\sqrt{{\displaystyle \frac{1}{WS}}{\sum }_{i=\left(j-1\right)\times WS}^{\left(WS-1\right)\times j}{\left(signal\left[i\right]\right)}^2}$$

(30)

where j represents the window number, indicating its position along the time axis.

It is important to highlight that selecting the fs involves balancing multiple factors, including the detail level of high-frequency modes, the need for capturing two distinct detail coefficients (one for f_sw and other for 3 × f_sw), as well as the computational efficiency and speed of the DWT algorithm. Conversely, varying fs requires corresponding adjustments to the values of WS and HS to ensure greater resilience to transients and to reduce the computational cost of the proposed solution.

Following this, using Equations (22)–(25), it was possible to compute the capacitor impedance, as well as the corresponding frequency. This information will serve as input for Algorithms 1 and 2, enabling the calculation of the AEC ESR and C values. After calculating the RatioESR and RatioC, the PDA (Figure 6) determined whether the AEC needed to be replaced. However, regarding the final RatioC, the value must first be pre-processed. Initially, the original RatioC value was constrained to the range of 0 to 2. This processed value acted as the measured input to the Kalman filter, which combined it with the previous RatioC to compute the current RatioC. The current RatioC was then compared to the threshold of 0.8. If it falls below this threshold, replacing the AEC should be considered promptly. In the final stage of PDA implementation, employing a Kalman filter was crucial for mitigating noise and transient effects in RatioC estimation, particularly during converter startup.

5. Evaluating the Preventive Diagnostic Algorithm (PDA)

In order to assess the performance of the proposed PDA, it was applied to the eleven scenarios outlined in Table 1. Therefore, after conducting the scenario simulations, with raw data depicted in Figure 7, Figure 8, Figure 9, Figure 10 and Figure 11, the capacitor current (IC) and voltage (VC) were pre-processed using DWT, in order to obtain the MF (CD5) and HF (DC3) signal modes. Figure 12, Figure 13, Figure 14, Figure 15 and Figure 16 display the output of the DWT filtering module, illustrated in Figure 6, for the eleven scenarios described in Table 1.

The signals shown in the previous five figures contain the modes of interest: CD3, representing HF mode, and CD5, representing MF mode. Following this, based on the previous signals (Figure 12, Figure 13, Figure 14, Figure 15 and Figure 16), the RMS values were calculated using a WS of 1000 samples and a HS of 500 samples, as can be seen in Figure 17, Figure 18, Figure 19, Figure 20 and Figure 21.

Using Figure 17, Figure 18, Figure 19, Figure 20 and Figure 21 and Equations (24) and (25), the capacitor impedance was calculated. Subsequently, both Algorithms 1 (sol1) and 2 (sol2) were employed to determine the capacitor ESR and C values for the eleven scenarios, along with the RatioESR and RatioC values.

Figure 22, Figure 23, Figure 24, Figure 25 and Figure 26 present the AEC ESR and C values calculated for the eleven scenarios, along with the associated errors, using sol1 and sol2.

By analyzing the previous figures, and considering just the ESR estimation, it can be concluded that sol1 (Algorithm 1) produced a maximum error of 1.5%, while sol2 (Algorithm 2) reduced the error to values below 1%. In the two algorithms, a strong resilience to transient phenomena was observed even during the converter startup, which demonstrated that the proposed solution was quite accurate when it came to ESR estimation. An error of 1% is negligible, considering that AEC’s end-of-life is defined by a 100% increase in its ESR.

The same conclusions did not apply to C estimation, where the error ranged from 5% to 15%, which is relatively high, considering that the AEC’s end-of-life is defined by a 20% reduction in its C value. Furthermore, both algorithms did not present complete resilience in the calculation of C during the converter startup, manifesting a short peak during this stage.

The larger error observed in predicting C compared to predicting ESR is attributed to the very low capacitive reactance in this frequency range, as illustrated in Figure 5 and in the studies conducted in [25,35].

In order to address the limitations of the proposed algorithms regarding the estimation of C, the indicators RatioESR and RatioC were introduced. These indicators compare the current estimated values of ESR and C with the corresponding ones of a sound capacitors. Figure 27, Figure 28, Figure 29, Figure 30 and Figure 31 display the calculations of both indicators (RatioESR and RatioC) for the eleven scenarios listed in Table 1.

When computing the RatioESR and RatioC indicators, described by Equations (17) and (18), the ESRsound and Csound values were taken to be equal to the estimated average value for the corresponding sound capacitor scenarios.

The thick dashed lines indicate the exact values of the ratio indicators for each of the scenarios. The preceding figure clearly demonstrates that the RatioESR indicator accurately tracked the exact ratio values within the respective scenario. Hence, it can be concluded that RatioESR serves as a valuable failure indicator, showcasing both accuracy and resilience to transients, including those occurring during converter startup.

On the other hand, Figure 27, Figure 28, Figure 29, Figure 30 and Figure 31 illustrate that the impact of the C estimation errors was similar across different scenarios (sound and aged AEC), highlighting the effectiveness of the RatioC fault indicator. However, although RatioC accurately tracked the exact ratio values, it showed significant noise and lacked resilience to transients, particularly during converter startup. At this stage, RatioC could briefly reach very high values, as depicted in Figure 32.

In order to address the aforementioned issue, initially, the RatioC value was capped at a maximum of 2. Subsequently, the new RatioC values, limited to a maximum value of 2, were processed through a Kalman filter, which enabled the derivation of a smooth and accurate indicator estimate, even during the startup of the converter. The update of the Kalman filter gain in each iteration accounted for the uncertainty in both the estimation and measurements, making it especially effective in noisy and dynamic scenarios [47], such as the problem being analyzed.

Figure 33, Figure 34, Figure 35, Figure 36 and Figure 37 show the evolution of RatioC for the 11 scenarios under analysis after applying the Kalman filter.

The previous figures show that the Kalman filter effectively reduced noise and made the RatioC estimation resilient to transients, particularly during converter startup. On the other hand, after applying the Kalman filter, it was observed that RatioC1 and RatioC2 exhibited identical trends. This indicates that both algorithms (Algorithms 1 and 2) can be used effectively for calculating RatioC in the context of implementing PDA.

Hence, based on the various scenarios analyzed, both the RatioESR and RatioC indicators can be effectively used to evaluate AEC’s status.

6. Conclusions

Power converters (PCs) are widely used in critical applications, such as aerospace systems, medical systems, transportation vehicles, and more, due to their ability to control and transform electrical energy efficiently and reliably. Therefore, a fundamental aspect in the design of PCs is to ensure their reliable performance. One way to achieve the reliability of these systems is to incorporate intelligence into the system, allowing it to predict failures and generate advance warnings before failures occur.

Aluminum electrolytic capacitors (AECs) are crucial components in the design of power converters. However, they are remarkably susceptible, highlighting the need to find solutions to assess their health status. The aging of AECs manifests itself through changes in certain characteristics resulting from the electrolyte loss. These changes become more evident through the reduction in capacitance (C) and the increase in the equivalent series resistance (ESR) of the AECs.

This paper presented a preventative diagnosis algorithm (PDA) capable of determining the ideal time to replace the AEC presented in the output filter of a three-phase interleaved boost converter. The PDA employed discrete wavelet transform (DWT) to extract the current and voltage modes of the AEC. Following this, the key features of these modes were derived using a combination of signal windowing and root mean square value computation. These features enabled the estimation of capacitor impedance at medium and high frequencies, thereby facilitating the estimation of ESR and C values. While the estimation of ESR was reliable, accurate, and particularly robust against transients, the same was not true regarding C estimation. For this reason, two indicators were introduced, the RatioESR and RatioC. These indicators represent the relationship between the ESR and C values of the current AEC and their respective values for a sound AEC. The RatioESR could be used just as effectively as the ESR value, as the proposed solution estimated the ESR value with an error of less than 1%. Regarding RatioC, it exhibited significant noise and low resilience to transients, especially those arising from the converter startup. Therefore, it was necessary to process the RatioC value using a Kalman filter to enhance its robustness against transients and reduce noise.

The proposed solution was validated using a simulated three-phase interleaved boost converter on the MATLAB/Simulink platform, which included a PI controller with anti-windup capability. It is worth noting that this solution can be easily applied to other converters as long as the current and voltage across the capacitors are accessible.