Complementary Polarizer SOT-MRAM for Low-Power and Robust On-Chip Memory Applications

Abstract

Complementary polarized spin-transfer torque magnetic random-access memory (CPSTT-MRAM) has been proposed to address the sensing reliability issues caused by the single-ended sensing of STT-MRAM. However, it results in a three-fold increase in the free layer (FL) area compared to STT-MRAM, leading to a higher write current. Moreover, the read and write current paths in this memory are the same, thus preventing the optimization of each operation. To address these, in this study, we proposed a complementary polarized spin-orbit torque MRAM (CPSOT-MRAM), which tackles these issues through the SOT mechanism. This CPSOT-MRAM retains the advantages of CPSTT-MRAM while significantly alleviating the high write current requirement issue. Furthermore, the separation of the read and write current paths enables the optimization of each operation. Compared to CPSTT-MRAM, the proposed CPSOT-MRAM achieves a 4.0× and 2.8× improvement in write and read power, respectively, and a 20% reduction in layout area.

1. Introduction

Spin-transfer torque magnetic random-access memory (STT-MRAM) has garnered considerable interest for future CPU caches and embedded memories because of its promising attributes, including high integration density, nonvolatility, and compatibility with CMOS processes [1,2,3]. The MTJ is the storage element in STT-MRAM, and it comprises two ferromagnetic layers that are separated by a tunneling oxide layer (e.g., MgO). The magnetization of one of the ferromagnetic layers, known as the pinned layer (PL), remains fixed, whereas that of another ferromagnetic layer, the free layer (FL), can be altered upon the flow of an electrical current. The FL magnetization consists of two stable states relative to the PL magnetization: parallel (P state) or anti-parallel (AP state). The P state has a lower resistance compared to the AP state, such that a read operation can be executed by passing a small current through the MTJ and sensing the voltage difference to determine the binary state. Given the nonvolatile nature of MTJ, STT-MRAM can reduce the overall power consumption by eliminating leakage power.

Despite its desirable attributes, there are three major design issues associated with STT-MRAM. First, achieving a high-speed write operation requires the application of a large electrical current to the MTJ, resulting in significant write power consumption and subjecting the tunnel junction to high-stress conditions. Second, as shown in Figure 1a, the path of the read current is the same as that of the write current, leading to a tradeoff between the read stability and the write-ability [4,5,6,7]. The last design issue is associated with the use of a single-ended sensing scheme by read operations, which might not be sufficiently robust against process variation. These design issues of STT-MRAM will be discussed in more detail later.

To overcome the issue of a single-ended sensing scheme, an STT-MRAM structure with complementary polarizers STT-MRAM (CPSTT-MRAM) has been proposed (Figure 2) [8]. By exploiting two complementary polarized PLs and one FL structure, the proposed memory enables a self-reference differential sensing scheme, resulting in a higher sensing margin than a conventional single-ended sensing scheme. However, CPSTT-MRAM is still plagued by issues associated with high write power and oxide reliability. Particularly, the write power consumption of CPSTT-MRAM is worse than that of STT-MRAM because the enlargement of the MTJ FL is required to implement two complementary PLs in an FL. Moreover, the write process cannot be easily performed since the write current in CPSTT-MRAM does not uniformly pass through the MTJ FL, as we will discuss later.

To resolve these problems, we proposed a complementary polarizer spin-orbit torque-MRAM (CPSOT-MRAM). Our proposed CPSOT-MRAM bit-cell employs spin-orbit torque-induced switching, which can perform write operations in smaller currents, owing to the high spin current injection efficiency of the device. Additionally, the CPSOT-MRAM does not require a high-stress condition across the tunnel junction for writing as the write current flows through heavy metal (HM) instead of the tunnel junction. Compared to CPSTT-MRAM, in our proposed CPSOT-MRAM, spin-polarized electrons in the HM are uniformly injected into the MTJ FL. Furthermore, the CPSOT-MRAM not only addresses the design issues of CPSTT-MRAM but also maintains its advantages, such as self-reference differential sensing operations, thus increasing the commercialization potential of CPSOT-MRAM-based MRAM.

2. STT-MRAM Design Issues

Despite the advantages of STT-MRAM, which make it a promising alternative to conventional volatile on-chip memories, it is plagued with three major design issues that limit its widespread commercialization. First, STT-MRAM requires a large write current density of >3.9 × 10¹¹ A/m², resulting in significant write power consumption [9]. Moreover, for the switching mechanism of STT-MRAM, known as the spin-transfer torque (STT) effect, the efficiencies in P-to-AP switching differ from that in AP-to-P switching, as the P-to-AP switching requires a higher write current than AP-to-P switching [10]. This imbalance in write efficiencies further increases the write power consumption of STT-MRAM.

Second, there are difficulties in simultaneously improving the read–disturb margin and write-ability of STT-MRAM. Particularly, given that the read and write current paths of the STT-MRAM are the same, it is challenging to meet different requirements for read and write (Figure 1a). For example, increasing the width of the access transistor for reliable write operations inadvertently results in bit flips during read operations (Figure 1b). In addition to the access transistor width, oxide barrier thickness also affects the read/write operations, as the scaling down of the oxide barrier thickness is required to support a smaller MTJ cross-section [11,12,13]. However, while a smaller oxide barrier thickness can improve write performance, it increases the current flowing in read operations, which may eventually lead to data flipping due to a reduced read–disturb margin.

Lastly, the use of a single-ended sensing scheme in STT-MRAM results in low read stability. Compared to the differential sensing scheme, the single-ended sensing scheme is highly affected by process variation, which reduces the read margin. For example, as shown in Figure 1c, if the reference current (I_REF) is 30 µA (i.e., a P-state current (I_{READ_P}) lower than 30 µA or AP-state current (I_{READ_AP}) larger than 30 µA), the purple boxed range in the figure cannot be accurately sensed. Hence, owing to the process variation of MTJ tunneling oxide between the global reference cell and the local data cell, it is difficult to secure sufficient reading margins.

3. CPSTT-MRAM Structure

Figure 2a shows the structure of a complementary polarized magnetic tunnel junction (CPMTJ) device. The CPMTJ comprises two PLs and one FL separated by a tunneling oxide barrier (e.g., MgO). In the CPMTJ, one of the PLs functions as a reference (PL_REF), while the other functions as a data (PL_DATA). Both PL_REF and PL_DATA have opposite magnetization directions, and the width of FL is three times that of a single PL dimension, enabling its encompassment of both PL_REF and PL_DATA with a single cell. In addition, the CPMTJ device features three terminals (T₁~T₃), as shown in Figure 2a, such that two access transistors are required to prevent the flow of the sneak current.

The structure of a CPSTT-MRAM unit cell is depicted in Figure 2b. Compared to the conventional STT-MRAM unit cell, which uses a single bit line (BL), the CPSTT-MRAM unit cell employs two BLs running in a vertical direction. One BL (BL_REF) is connected to the access transistor of PL_REF, whereas the other (BL_DATA) is connected to the access transistor of PL_DATA. The two access transistors connected to T₁ and T₂ are controlled by the same word line (WL), and the T₃ of the CPSTT device is connected to the source line (SL) running in the horizontal direction.

The CPSTT-MRAM uses the spin-transfer torque-based FL switching mechanism, where writing is performed by passing a current through the CPMTJ device. For a write ‘1’ operation, as illustrated in Figure 2c and Figure 3a, BL_REF is grounded and V_WRITE is applied to SL. Thereafter, the WL is set high to activate both access transistors, enabling the flow of current from SL to BL_REF. It should be noted that BL_DATA is biased to V_WRITE to prevent a current between BL_DATA and SL. Then, the FL aligns its magnetization direction parallel to PL_REF and antiparallel to PL_DATA, resulting in a ‘1’ being stored. A write ‘0’ operation can be performed by setting the relationship between PL_DATA and FL to the P state while setting the relationship between PL_REF and FL to the AP state. As shown in Figure 2c and Figure 3b, BL_DATA is grounded and V_WRITE is applied to SL to flow a write current from SL to BL_DATA. Then, the FL aligns its magnetization direction parallel to PL_DATA and antiparallel to PL_REF, leading to the storage of a ‘0’.

In Figure 3a,b, the section highlighted with a blue gradient on the FL indicates the write current density during write operation. In the blue gradient, a darker shade of blue indicates a higher current density, whereas a lighter shade indicates a lower current density. During the write ‘1’ operation, the current in the FL is skewed towards T₁, whereas it is skewed towards T₂ during the write ‘0’ operation. Thus, as shown in the figure, CPSOT-MRAM has the drawback of a non-uniform write current density across the FL.

For the read operation, as shown in Figure 2c and Figure 3c, SL is grounded and a small read voltage (V_READ) is applied to both BL_REF and BL_DATA, causing the read current to flow from both BLs to the SL, as illustrated in Figure 3c. Thereafter, the difference between the two currents is compared. Compared to conventional STT-MRAM, which compares the read current with the reference current from a global reference cell, CPSTT-MRAM employs a differential sensing scheme, comparing the difference between I_{READ_REF}, which is the read current generated in BL_REF, and I_{READ_DATA}, which is the read current generated in BL_DATA. If I_{READ_REF} > I_{READ_DATA}, it indicates that the relationship between PL_DATA and FL has a higher resistance than the relationship between PL_REF and FL, resulting in a ‘1’ being stored in the MRAM unit cell. In contrast, if I_{READ_REF} < I_{READ_DATA}, it indicates that the relationship between PL_DATA and FL has a lower resistance than the relationship between PL_REF and FL, resulting in a ‘0’ being stored.

CPSTT-MRAM offers several advantages over the conventional STT-MRAM. First, the complementary polarizer structure of the device and the use of a differential sensing scheme significantly enhance the read margin compared to conventional STT-MRAM. Additionally, compared to conventional STT-MRAM that utilizes a single-ended scheme, which compares the read current with the current level in the average state of the AP state and the P state, CPSTT-MRAM always compares two complementary current levels, thereby enhancing the read margin.

Second, CPSTT-MRAM is robust against process variations. In the case of the conventional STT-MRAM, the data cell is compared to the global reference cell, making it highly susceptible to process variations owing to the physical distance between the data cell and the global reference cell. In contrast, CPSTT-MRAM is structured such that a single-oxide barrier is shared by two PLs, thereby minimizing process variation between the reference part and the data part.

Third, as AP-to-P switching requires lower critical current, CPSTT-MRAM leverages this efficiency by writing both data ‘0’ and ‘1’ in the CPMTJ device exclusively through AP-to-P switching. Regardless of the data being used, the write current always flows from the FL towards the two PLs. Consequently, its write efficiency is significantly higher than that of conventional STT-MRAM because write operations are performed only through parallelized switching, regardless of whether data 1 or data 0 is being written.

Fourth, CPSTT-MRAM significantly improves the read–disturb margin compared to conventional STT-MRAM. During the read operation of CPSTT-MRAM, AP and P states are read simultaneously in a single CPMTJ cell, where the simultaneous application of spin in opposite directions to the FL cancels each other out, thus significantly enhancing the read–disturb margin to nearly infinite levels.

Although CPSTT-MRAM benefits from the high STT efficiency of the AP-to-P switching, the three-fold increase in the FL area results in a significantly higher write current compared to that of conventional STT-MRAM, thereby increasing the write power. Furthermore, as mentioned previously, the write current is injected non-uniformly into the FL, and this lengthens the time required for switching the magnetization direction of the FL, thus reducing the write speed and increasing both the write power and the write error rate. Moreover, in CPSTT-MRAM, the read and write current paths remain the same, making it impossible to optimize each operation individually. As mentioned previously, increasing the oxide barrier thickness to optimize the read operation will degrade the write performance.

4. Proposed CPSOT-MRAM

To address the aforementioned issues with CPSTT-MRAM, we propose CPSOT-MRAM. Figure 4a shows the structure of our proposed four-terminal CPSOT device. Our proposed CPSOT device consists of the CPMTJ device with a heavy metal (HM), which is in direct contact with the FL of the CPMTJ device. In the CPSOT device, the read operation is performed by the complementary polarizer structure, and the write operation is performed by the current flowing through the HM, facilitating switching via the spin-orbit torque (SOT) mechanism, as shown in Figure 4b. Additionally, a spin sink layer (SSL), which can reduce the backflow of spin current by addressing the effect of the spin accumulation at the bottom surface of the HM, was implemented [14].

As the HM has two terminals at its ends, resulting in the four-terminal structure (T₁~T₄) of the CPSOT device, three transistors are required to prevent leakage current. Among these three access transistors, two read transistors (TR₁ and TR₂) gated by a read word line (RWL) are connected to the two complementary polarized PLs. The read transistors are connected to read BL_REF (RBL_REF) and read BL_DATA (RBL_DATA), running in a vertical direction, as shown in Figure 5a. The write transistor (TR₃) gated by the write world line (WWL) is connected to one end of the HM. The vertically routed write BL (WBL) is connected to the write transistor, and the opposite terminal of HM is connected to the SL, running in the horizontal direction.

The switching mechanism of CPSOT-MRAM is shown in Figure 4b. When a charge current flows in the −x direction, the spin-orbit coupling in the HM deflects spins in the +y and −y directions to the bottom and top surfaces of the HM, respectively. The accumulated spins on the top surface of HM exert STT, thus switching the FL magnetization to the −y direction. The spin current generated by the injected charge current can be expressed as follows [15,16]:

$$I_s={\displaystyle \frac{A_{MTJ}}{A_{HM}}}{\theta }_{SH}\left(1-\mathrm{sech}\left({\displaystyle \frac{t_{HM}}{{\lambda }_{sf}}}\right)\right)I_e$$

(1)

where ${\lambda }_{Sf}$ is the spin-flip length, $A_{MTJ}$ and $A_{HM}$ are the cross-sectional area of the MTJ and heavy metal, respectively, and ${\theta }_{SH}$ is the spin-hall angle of HM, which is defined as the ratio of spin-hall conductivity to electrical conductivity and is used as an indicator to quantitatively confirm the effect of SOT [x1,x2]. In Equation (1), the spin current injection efficiency, which is defined as the ratio of the injected spin current ($I_s$) to charge current ($I_e$), depends on the cross-sectional area ratio between the MTJ and HM. The appropriate sizing of the cross-sectional area ratio of the MTJ to the HM can result in a spin current injection efficiency above 100% owing to the passage of a single electron through the HM, transferring multiple units of angular momentum [15,17,18]. Therefore, compared to the STT mechanism, the SOT mechanism enables switching operations with higher efficiency. Further, the addition of the SSL to our proposed CPSOT-MRAM device structure significantly reduces the backflow of the spin current. An assumption of a perfect SSL allows us to assume a value of ${\lambda }_{sf}$ close to zero, making the second term ($\mathrm{sech}(t_{HM}/{\lambda }_{sf})$) in Equation (1) negligible. Consequently, the introduction of the SSL further enhances the spin current injection efficiency. The proposed CPSOT-MRAM was implemented using a perpendicular magnetic anisotropy (PMA) MTJ with an external field to break the in-plane symmetry of the magnetization direction.

The write ‘1’ operation can be performed by applying V_WRITE to WBL, and SL grounded and WWL are set high, such that a write current flows from WBL to SL. During write operations, RWL is grounded to turn off the two read transistors. Thereafter, the magnetization direction of the FL, owing to the SOT mechanism under the influence of an external field, aligns parallel to the PL_REF and antiparallel to the PL_DATA, leading to a ‘1’ being stored. The write ‘0’ operation can be performed by applying the write current in the opposite direction of the write ‘1’ operation. Please note that the SL, arranged horizontally, as shown in Figure 5, remains fixed at G_ND. Thus, to create current in the opposite direction as in the write ‘1’ operation, a negative voltage (V_NEG) is applied to the WBL.

The application of a negative voltage to BL needs careful transistor biasing for reliable operation. To prevent unwanted writing due to the negative BL voltage, our proposed CPSOT-MRAM biased the WWL with a negative voltage, V_NEG, when the associated transistor is not selected for access. This approach prevents leakage current through unselected transistors by ensuring that V_GS remains under 0 V, even when the associated WBL voltage is negative.

A read operation can be performed by applying a small read voltage (V_READ) to both RBLs, and the SL is grounded, as illustrated in Figure 5b. When V_DD is applied to RWL to turn on the read access transistors, I_{READ_REF} and I_{READ_DATA} flows from RBL_REF and RBL_DATA to SL, respectively. If I_{READ_REF} > I_{READ_DATA} during a read, then the relationship between PL_DATA (PL_REF) and FL is in an AP (P) state. This indicates that data ‘1’ is stored in the CPSOT-MRAM unit cell. In contrast, if I_{READ_REF} < I_{READ_DATA}, the relationship between PL_DATA (PL_REF) and FL is in a P (AP) state, thus storing ‘0’. During the read operation, WWL is grounded to turn off the write access transistor.

Compared to the STT mechanism, the SOT mechanism enables the separate optimization of read and write stability because the read current path and write current paths are decoupled. As shown in Figure 4a, the write current flows exclusively through the HM and does not directly pass through the oxide barrier, whereas a smaller read current flows through the oxide barrier [19]. Therefore, for the read operation, the oxide layer can be made sufficiently thick to improve the read margin and read power consumption without affecting the write operation. Moreover, CPSOT-MRAM addresses the issue of non-uniform current injection into the FL during the write operation, which is a drawback of CPSTT-MRAM. This is achieved by the SOT mechanism, which ensures uniform current injection into the FL, improving the write performance and reducing the write power consumption.

The proposed CPSOT-MRAM retains all the advantages of the aforementioned CPSTT-MRAM. Additionally, given its complementary polarized PLs and differential sensing structure, it significantly improves the read margin compared to conventional STT-MRAM. Our proposed memory senses stored data through the two PLs in a single CPSOT cell rather than a global reference cell, making it robust against process variations. Additionally, as the AP state and P state are read simultaneously during the read operation, the opposing spins applied at the same time cancel each other out, thus significantly increasing the disturb margin.

5. Simulations and Results

To evaluate the performance of the proposed CPSOT-MRAM, we conducted comparative simulations with STT-MRAM and CPSTT-MRAM. The spintronic device models used in our simulations were based on the SPICE model shown in [20,21], which consists of subcircuits that calculate the resistance of MTJ, heat diffusion, and dynamic spin motion using the Landau–Lifshitz–Gilbert (LLG) equation [20,21], with modifications made to accommodate the proposed CPSOT-MRAM. The parameters used in the simulation were assigned uniformly across the three types of MRAM devices to ensure a fair comparison. The spintronic device models were combined with a 45 nm CMOS transistor model to create the complete memory unit cell structure.

The size of the STT-MRAM device was 60 nm × 60 nm × 1 nm, and those of the CPSTT- and CPSOT-MRAM devices were both set at 60 nm × 180 nm × 1 nm, which was three times larger than that of STT-MRAM. The estimated resistance-area product (RA) value for the MTJ oxide barrier was five in both the CPSTT-MRAM and STT-MRAM to enable FL switching under the identical condition of the supply voltage of 1.10 V (45-nm CMOS process) and a 30 ns switching time. In contrast, CPSOT-MRAM, whose write operation was not affected by the MTJ resistance as its write operation was performed by a current through HM, was optimized for improved read margin and read power by selecting a higher RA. Information on other parameters related to MTJ and Spin Hall Metal (SHM) for SOT is summarized in

Table 1. Parameters of the Spintronic devices.

MTJ Parameters
MTJ type	Crystalline perpendicular
Free layer dimensions, $L_m\times W_m\times t_m$	60 nm × 180 nm × 1 nm (CPSTT, CPSOT) 60 nm × 60 nm × 1 nm (STT)
Saturation magnetization constant, $M_s$	1185 emu/cc
Crystal anisotropy constant, $K_P$	7.9 × 106 erg/cc
Damping constant, $\alpha$	0.02
Polarization factor, P	0.9
RA $(\Omega ·{\mathsf{\mu }\mathrm{m}}^2$)	5 (CPSTT, STT) 10 (CPSOT)
Spin Hall Metal (SHM) Parameters
SHM dimensions, $L_{SHM}\times W_{SHM}\times t_{SHM}$	140 nm × 180 nm × 1 nm
Bulk spin hall angle, ${\theta }_{SHE0}$	0.4
SHM resistivity	2000
SHM spin polarization factor, $P_{SHE}$	1.55

.

The simulation results are presented in

Table 2. Simulation results.

	STT	CPSTT	CPSOT
Tx Width ($W_N$)	115 nm	390 nm	300 nm (write) 120 nm (read)
Area	0.0768 μm2	0.2070 μm2	0.1656 μm2
Write Voltage	1.10 V	0.80 V	0.45 V/−0.30 V
Read Voltage	0.20 V	0.20 V	0.20 V
Write Power	123.88 μW	210.33 μW	52.96 μW
Read Power	14.68 μW	23.86 μW	8.55 μW
Read Margin	37.30%	67.09%	55.86%
Read–disturb Margin	52.66%	-	-

. As listed in Table 2, CPSOT-MRAM exhibited the lowest write power, followed by STT-MRAM and CPSTT-MRAM. As expected, the comparison between CPSOT-MRAM and CPSTT-MRAM revealed that the write power of CPSOT-MRAM was 4.0× lower than that of CPSTT-MRAM owing to the SOT write mechanism. Additionally, the comparison between CPSTT-MRAM and STT-MRAM revealed that CPSTT-MRAM exhibited significantly higher write power consumption owing to the three-fold increase in the FL dimension in CPSTT, with the write power being 1.7× higher than that of STT-MRAM. Further, the comparison between CPSOT-MRAM and STT-MRAM revealed that despite the larger FL dimension of CPSOT-MRAM, it exhibited a 2.3× improvement in write power consumption compared to STT-MRAM, and this was attributed to the utilization of the SOT mechanism, which enabled the high efficiency of the spin current injection, by the CPSOT-MRAM. Furthermore, the write current path was through the HM with relatively low resistance, thus enabling sufficient write current with a low write voltage requirement.

We performed read simulations under the same condition of 0.2 V read voltage for a fair comparison. For CPSTT-MRAM and STT-MRAM with identical read/write current paths, the access transistor size was determined for the write operation. In contrast, CPSOT-MRAM has separate read and write current paths, enabling the optimization of the tunneling oxide barrier resistance (RA) independently of the write operations. As depicted in Table 2, the results of the read simulation revealed that CPSOT-MRAM exhibited a 2.8× lower read power than CPSTT-MRAM. Even compared with STT-MRAM, our proposed memory could achieve a 1.7× higher read power efficiency.

To verify the enhanced read performance of our proposed CPSOT-MRAM, we calculated the read margin, defined as the difference between the unit cell read current and the reference read current $((I_P-I_{REF})/I_{REF})$). In STT-MRAM, the read margin was small at 37.30%, as it compares the bit cell read current with the read current of a reference cell, which has the average resistance of the AP and P states. However, CPSOT-MRAM employs a differential sensing scheme that compares the currents of the AP and P states directly, resulting in a read margin of 55.86%, which is a 33% improvement over that of STT-MRAM.

As shown in Table 2, the read power of CPSOT-MRAM is approximately 2.8× lower than that of CPSTT-MRAM, and the read current is also reduced by more than 2×. The read margin, calculated from the difference between the two read currents, decreased slightly for CPSOT-MRAM compared to CPSTT-MRAM due to the resistance of HM. However, CPSOT-MRAM’s read margin showed a substantial improvement over STT-MRAM’s read margin of 37.30% [x3]. This enhancement sufficiently addresses one of the design issues of STT-MRAM, namely the small read margin problem due to the single-ended sensing scheme.

The read–disturb margin, defined as $(I_C-I_R)/I_C$, where $I_C$ is the critical write current and $I_R$ is the read current, of STT-MRAM was calculated. In the case of STT-MRAM, the read–disturb margin was achieved at 52.66%. Meanwhile, the read–disturb margin of CPSTT-MRAM and CPSOT-MRAM could be considered infinite. This is because both structures feature one FL attached to two PLs, causing the simultaneous injection of oppositely oriented spins from each PL, canceling each other out, thus not affecting the FL magnetization disturbance during the read.

Lastly, unit cell areas of the layout designs of the three different memory devices were compared. Figure 6 shows the layout of the fingered STT-MRAM, CPSTT-MRAM, and the proposed CPSOT-MRAM, designed based on the lambda rule [22,23]. To ensure a minimum area for the increased transistor size, the STT-MRAM layout was designed with a two-fingered configuration, and the layout of CPSTT-MRAM is a reconfiguration based on the layout presented in [8]. Owing to its 1T1M structure, STT-MRAM had the most advantageous area compared to CPSTT-MRAM, which employs a three-terminal structure with two transistors, and CPSOT-MRAM, which employs a four-terminal structure with three transistors. Additionally, compared to CPSOT-MRAM, which enables switching with small currents owing to the spin hall effect, CPSTT-MRAM required significantly higher currents owing to the three-fold increase in the FL size compared to STT-MRAM, necessitating larger access transistors. Therefore, the width of the write access transistor of CPSOT-MRAM was 23% smaller than that of CPSTT-MRAM, such that CPSOT-MRAM achieved a 20% smaller area compared to CPSTT-MRAM. These results indicate that the proposed CPSOT-MRAM exhibited superiority in terms of area, power, and speed, demonstrating the potential to become a future memory cell.

6. Conclusions

Given the inherent drawbacks of conventional STT-MRAM, such as large write power consumption, read-write design conflict, and high possibility of sensing failure due to the use of a single-ended sensing scheme with global reference, CPSTT-MRAM has been proposed to overcome these limitations. This study proposes the use of HM in conjunction with CPSTT-MRAM, forming a four-terminal CPSOT-MRAM. The presented CPSOT-MRAM utilizes HM for writing and performs differential sensing by adopting the complementary polarized structure. Our simulation results revealed that the proposed CPSOT-MRAM demonstrated a 2.3× lower write power consumption compared to STT-MRAM owing to the incorporation of the spin hall effect mechanism. Additionally, through the optimization of both the read and write processes, it exhibited a 1.7× lower read power consumption compared to STT-MRAM. The differential sensing scheme of CPSOT-MRAM resulted in a read margin that was 33% higher than that of STT-MRAM, and the read margin of CPSOT-MRAM could be considered nearly infinite.