Picowatt Dual-Output Voltage Reference Based on Leakage Current Compensation and Diode-Connected Voltage Divider

A picowatt CMOS voltage reference with dual outputs is proposed and simulated in this paper based on a standard 65 nm process. To compensate for the leakage current caused by parasitic reverse-biased PN junctions, an approach employing gate leakage transistors is proposed. Maintaining a maximal temperature coefficient (TC) of 20.40 ppm/${}^{\circ }$C across an extended temperature range of −10∼155 ${}^{\circ }$C is achieved. Additionally, a voltage divider consisting of diode-connected NMOS transistors is introduced to obtain a lower voltage output without shunting the original branch or utilizing operational amplifiers. Moreover, a novel trimming block is utilized to optimize TC across different process corners. Simulation results demonstrate that a minimum power consumption of only 53.83 pW is achieved and the line sensitivity is 0.077%/V with 0.45 V to 2.5 V supply. The power supply rejection ratio of −76.70 dB at 10 Hz and $V_{DD}$ = 1.8 V is obtained.