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Volume 13
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Article

Estimation of Void Area and Position in Solder Layer of Power Semiconductor Devices Based on Temperature Distribution Characteristics

by
Wang Guo
1,*,
Xingang Chen
1,2,*,
Zheng Tang
3,
Xingmou Liu
4,
Zhipeng Ma
1,
Xiangtao Xu
5 and
Daquan Xia
5
1
School of Electrical and Electronic Engineering, Chongqing University of Technology, Chongqing 400054, China
2
Chongqing Engineering Research Center of Energy Interconnection, Chongqing 400054, China
3
College of Materials Science and Engineering, Chongqing University of Technology, Chongqing 400054, China
4
Key Laboratory of Industrial Internet of Things & Networked Control, Ministry of Education, and Chongqing Key Laboratory of Complex Systems and Bionic Control, Chongqing University of Posts and Telecommunications, Chongqing 400065, China
5
Chongqing Pingwei Enterprise Co., Ltd., Chonqing 405200, China
*
Authors to whom correspondence should be addressed.
Electronics 2024, 13(17), 3544; https://doi.org/10.3390/electronics13173544
Submission received: 11 August 2024 / Revised: 2 September 2024 / Accepted: 4 September 2024 / Published: 6 September 2024
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Abstract

Solder layer voids have a significant impact on the thermal performance of a device, which is a key cause of the thermal failure of the device. In this paper, the area and location of solder layer voids are calculated by combining finite element modeling and experimental measurements. Specifically, by analyzing the path of heat dissipation in the device, an equivalent thermal resistance network is constructed to calculate the area and location of the solder layer voids, and the calculation results show that the increment of the path thermal resistance depends on the void area; almost independently of the location, the temperature distribution of the device changes due to the phenomenon of heat accumulation in the voids. Further, in order to calculate the position of the solder layer voids, a point thermal resistance network matrix model is proposed based on the temperature distribution characteristics of the device surface. The validity of the proposed model is verified by comparing the calculation results of the junction temperature, void area, and location with the measurement results based on experimental platforms.
Keywords: device thermal reliability; solder layer voids; thermal resistance network modeling; void area and location calculation device thermal reliability; solder layer voids; thermal resistance network modeling; void area and location calculation

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MDPI and ACS Style

Guo, W.; Chen, X.; Tang, Z.; Liu, X.; Ma, Z.; Xu, X.; Xia, D. Estimation of Void Area and Position in Solder Layer of Power Semiconductor Devices Based on Temperature Distribution Characteristics. Electronics 2024, 13, 3544. https://doi.org/10.3390/electronics13173544

AMA Style

Guo W, Chen X, Tang Z, Liu X, Ma Z, Xu X, Xia D. Estimation of Void Area and Position in Solder Layer of Power Semiconductor Devices Based on Temperature Distribution Characteristics. Electronics. 2024; 13(17):3544. https://doi.org/10.3390/electronics13173544

Chicago/Turabian Style

Guo, Wang, Xingang Chen, Zheng Tang, Xingmou Liu, Zhipeng Ma, Xiangtao Xu, and Daquan Xia. 2024. "Estimation of Void Area and Position in Solder Layer of Power Semiconductor Devices Based on Temperature Distribution Characteristics" Electronics 13, no. 17: 3544. https://doi.org/10.3390/electronics13173544

APA Style

Guo, W., Chen, X., Tang, Z., Liu, X., Ma, Z., Xu, X., & Xia, D. (2024). Estimation of Void Area and Position in Solder Layer of Power Semiconductor Devices Based on Temperature Distribution Characteristics. Electronics, 13(17), 3544. https://doi.org/10.3390/electronics13173544

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