Design of an Internal Asynchronous 11-Bit SAR ADC for Biomedical Wearable Application

Abstract

This paper introduces a fully differential asynchronous successive approximation register analog-to-digital converter (SAR ADC) designed for biomedical signal processing. By extending the tracking time and utilizing fully differential inputs in the analog front-end circuit, the signal-to-noise ratio is enhanced in the system. Using an asynchronous clock can reduce power consumption across a wider range of sampling frequencies. In comparison to conventional architecture in high-speed SAR ADC, using an internal clock generator can operate at lower frequencies. A fully differential input can eliminate the DC offset of the analog front-end circuit and reduce the adverse effects of process variation, voltage variation, and temperature variation. The chip is implemented by TSMC 0.18 $\mathsf{\mu }$m complementary metal-oxide-semiconductor (CMOS) technology, and the chip area is 0.680 mm² (including ESD I/O PAD). At a 1.2 V supply, the maximum sampling rate is 10 Kilo Samples per second (KSps). The implemented ADC has an 11-bit resolution, while the input voltage range is 300∼900 mV. The total power consumption is 1.7 $\mathsf{\mu }$W, with the core power consumption at 932 nW.

1. Introduction

The coronavirus disease 2019 (COVID-19) pandemic has not only prompted people to pay more attention to their own health but also to focus on how to effectively use technology to combat the epidemic. It has prompted governments of various countries to actively invite industry and academia to conduct relevant research and development work during the epidemic. In order to allocate all medical resources to epidemic prevention, reducing the waste of medical resources and unnecessary contact between doctors and patients during the epidemic is crucial. The integration of biomedical wearable devices and telemedicine services has emerged as a prevailing trend. With the popularization of mobile smart devices, wearable devices such as hats, glasses, earphones, watches, clothes, bracelets, and belts have been integrated with smart devices and seamlessly incorporated into people’s daily lives. In addition to medical wearable devices that focus on professional medical applications, biomedical wearable devices primarily measure biomedical information such as heart rate, blood oxygen, blood pressure, temperature, and respiration. The reliability of the data is relatively limited, providing only reference value. However, these devices are more suitable for everyday use by the general public. Therefore, with the evolution of technology and the increasing requirements for wearable devices in the medical field, the “definition” of wearable devices has evolved. Traditionally, wearable devices refer to “items” worn on the body, such as fitness trackers, earphones, and intelligent watches. However, with the growing demand from consumer electronics, the definition of “wearable devices” has expanded to include devices that can be used interactively with all portable devices. The biggest challenge in implementation is low power consumption and high-resolution chip design technology.

These devices are commonly used to detect and monitor biomedical signals, such as electrocardiogram (ECG) and photoplethysmography (PPG). Most biomedical signals are typically slow and have a limited dynamic range [1]. As shown in Figure 1, a complete biomedical signal detection system can be divided into a biosensor, analog front-end circuit, analog-to-digital converter (ADC), and digital signal processing. The Biomedical signal is converted into an electrical signal using a biosensor. An analog front-end (AFE) circuit is used to amplify and filter the output signal of biosensor. The analog signal of AFE output is converted into a digital signal by an ADC and then analyzed through the digital processing unit. Biomedical signals are typically processed by ADC with medium resolution (8∼12 bits) and sampling rates (1∼1000 kSps) [2]. Low power consumption is a crucial design consideration in the development of wearable devices, making the power efficiency of the ADC a significant challenge. SAR ADC offer power efficiency advantages over other ADC architectures, such as delta-sigma ADC. In addition, SAR ADC has two main advantages: (1) SAR ADC is mainly composed of digital circuits and operates faster; (2) SAR ADC is an operational amplifier-free architecture. Therefore, the operational amplifier, which has high gain and high bandwidth, is unnecessary to ensure linearity. Typically, a high-efficiency operational amplifier consumes large amounts of power, which is not conducive to the application of wearable devices.

In this paper, we present an 11-bit fully differential asynchronous successive approximation register analog-to-digital converter (SAR ADC) with an internal clock generator that can achieve high resolution, high signal-to-noise ratio (SNR), and low power consumption. The chip design utilizes TSMC 0.18 $\mathsf{\mu }$m CMOS technology, with a chip area of 0.680 mm² (including ESD I/O PAD) and a power supply voltage of 1.2 V. This design uses asynchronous logic to extend the tracking time of the amplifier, significantly reducing power consumption and increasing the effective number of bits (ENOB). The asynchronous clock generator uses different design approaches to increase ENOB and decrease power consumption. It has comparable performance with advanced technology, reducing chip area and increasing resolution.

2. ADC Architecture for Biomedical Signal Detection

2.1. Delta-Sigma ADC

The basic architecture of a delta-sigma modulator (DSM), as shown in Figure 2A [3,4,5], consists of three parts: an integrator; a quantizer, which consists of a comparator and a latch; and a digital-to-analog converter (DAC). As the first stage of the delta-sigma ADC, the integrator is utilized to compute the integral of the difference between the input signal $V_{in}$, which is the output of the AFE, and the DAC output signal. This operation establishes the basis for the error feedback mechanism. Moreover, the integrator deliberately decreases the signal’s rate of change, thus enhancing the converter’s resolution at lower frequencies. As the core of the feedback loop, the DAC converts the digital signal output by the comparator into an analog signal. Subsequently, it compares this analog signal with the input signal to convert the quantization error into negative feedback. The quantizer comprises a comparator and a latch. The comparator primarily converts the output signal of the integrator into a binary signal by comparing it with a reference voltage. It can be considered as a 1-bit ADC. By using oversampling and noise shaping, we can obtain the transfer function Equation (1).

$$D_{out}=e_n\left({\displaystyle \frac{f_s}{1+f_s}}\right)+V_{in}\left({\displaystyle \frac{1}{1+f_s}}\right)$$

(1)

Among them, $f_s$ represents the sampling frequency and $e_n$ represents quantization noise. As far as quantization noise is concerned, the feedback architecture has a high-pass filter effect, so the quantization noise is shifted to the high-frequency region. Then, a low-pass filter is used to eliminate high-frequency noise in the signal band and retain only the quantization error within the signal bandwidth. This process reduces the overall quantization error in the output signal $D_{out}$, thereby improving the resolution and dynamic range of the system. A complete ADC must also include a decimation filter. This digital filter has a dual purpose. It suppresses out of band quantization noise from the delta-sigma ADC, enabling the filtering out of high-frequency noise. Additionally, it reduces the excessively high sampling frequency resulting from oversampling to aid in signal processing. This process, known as decimation, aims to enhance the SNR.

Delta-sigma ADC has the advantage of high resolution. It obtains more data points by oversampling at a rate higher than the Nyquist rate. This increased sampling rate allows the ENOB to exceed what traditional sampling achieves, resulting in high resolution. Noise reduction is another advantage of delta-sigma ADC. It employs noise shaping to shift the majority of quantized noise to high frequencies, thereby confining only a portion of the quantized noise within the bandwidth. This process substantially enhances the SNR. Delta-sigma ADC is distinguished by its high resolution and SNR, making it particularly well-suited for applications in medical imaging that demand high levels of resolution and SNR. However, a delta-sigma ADC needs to undergo sampling, noise shaping, and decimation steps. The analog-to-digital-conversion operation speed is slower than that of an SAR ADC, and the complex circuit architecture increases implementation difficulties. This complexity introduces latency into the conversion process, and filtering and down-conversion during the decimation stage add further latency. Biomedical wearable devices do not require high resolution and sampling ratio. However, their high latency makes them unsuitable for real-time monitoring. Complex operating procedures and excessive resolution will increase power consumption, which is incompatible with the low power of wearable devices. Due to these differing consumption requirements, they are not the primary choice for biomedical wearable device applications.

2.2. SAR ADC

The basic architecture of a successive approximation register ADC (SAR ADC) is shown in Figure 2B [6]. Its architecture includes a sample-and-hold circuit, a comparator, a digital-to-analog converter (DAC), and a successive approximation register logic (SAR logic). As the primary circuit of the SAR ADC, the sample-and-hold circuit is functionally divided into two steps: sampling and holding. First, the input voltage is sampled; then, the sampled voltage is maintained until the conversion is completed. The held voltage is directly related to the accuracy of the SAR ADC. The comparator is used to evaluate whether the held voltage is higher than the reference voltage. The output result is a 1-bit digital signal used to determine the SAR logic operation, which in turn affects the voltage approximation result. Its accuracy will affect the judgment of the least significant bit (LSB). The function of the DAC is to generate a reference voltage, which is controlled by SAR logic to produce a new reference voltage based on the comparator output. The DAC is also a key component that influences the power consumption and operating speed of the architecture. Typically, it is implemented using a capacitor architecture. As the core component of SAR ADC, the SAR logic embodies the essence of a binary-weighted progressive algorithm. It adjusts the current bit after each comparison, starting from the most significant bit (MSB) and ending with the LSB, until the reference voltage approaches the held voltage.

The SAR ADC utilizes a binary-weighted algorithm. The basic operational method is as follows: first, set the MSB to 1 and leave the other bits as 0. Conduct the initial comparison. If the reference voltage is lower than the held voltage, keep the MSB as 1; otherwise, if the reference voltage is higher than the held voltage, set the MSB to 0. Repeat these steps until the LSB is determined. In principle, an N-bit ADC necessitates conducting N comparisons, and the cumulative duration needed for the sampling and holding processes is called the conversion cycle. It is noteworthy that the conversion cycle of the SAR ADC is intricately linked to the ADC resolution. With an escalation in resolution, there is a corresponding rise in the requisite number of bits, leading to an increase in conversion time, all while the clock pulse remains constant. Consequently, the design of SAR ADC must strike a delicate equilibrium between the demands of resolution and speed.

It is established from the operational characteristics that the resolution of an SAR ADC exhibits an inverse relationship with the conversion speed. With an increase in resolution, there is a proportional increase in the number of bits needed, leading to a decrease in conversion speed. Consequently, the ADC’s performance in high-resolution applications will be constrained by its operating speed. The system specs of common biomedical wearable devices include resolution (8∼12 bits) and sampling rate (1∼1000 kSps). SAR ADC is renowned for its high performance at medium to high resolution and medium speed. The binary-weighted algorithm iteratively evaluates each bit to increase accuracy, and the single comparator architecture significantly reduces the power consumption of the ADC, allowing the SAR ADC to strike a balance between resolution, sampling rate, and low power consumption. This makes it very suitable for biomedical wearable device applications. However, linearity errors will affect the accuracy of the SAR ADC during implementation. The nonlinearity of the DAC introduces errors during the conversion process, thereby reducing accuracy. The architecture lacks noise reduction processing and is more sensitive to noise, so the DAC’s performance directly determines the performance of the SAR ADC.

2.3. Comparison of Differential Switch Capacitor Method

The comparator, sample-and-hold (S/H) circuit, capacitor array, and progressive approximation register are basic components of a successive approximation analog-to-digital converter, as shown in Figure 3A [7,8]. This ADC uses differential signals, so the operation on both sides is complementary. During the sampling phase, the negative pole of the capacitor is charged to $V_{ip}$ and the positive pole is reset to a common-mode voltage $V_{cm}$. In the next phase, the other capacitors are switched to ground except for the largest capacitor $C_1$, which is switched to $V_{ref}$. Subsequently, the comparator performs the first comparison. If $V_{ip}>V_{in}$, the most significant bit (MSB) $D_1$ is set to 1; otherwise, it is set to 0 and the largest capacitor is reconnected to ground. The second largest capacitor $C_2$ is switched to $V_{ref}$ and the comparator compares again. This process is repeated until the least significant bit (LSB) is determined. While the trial-and-error method is straightforward, it necessitates more capacitors and switches, leading to higher power consumption during conversion, as illustrated in Equation (2).

$$E_{conv}=\sum _{i=1}^n{2}^{n+1-2i}\times (2^i-1)C{V}_{ref}^2$$

(2)

Figure 3B [9] is a $V_{cm}$-based switching mode. Compared with the above modes, during the sampling phase, the positive pole of the capacitor is charged to $V_{ip}$ and the negative pole is reset to the common mode voltage $V_{cm}$. After that, turning off the $V_{ip}$ switch to floating, the voltages across the comparator are $V_{ip}$ and $V_{in}$. The comparator can be compared directly without switching any capacitor, which would produce extra consumption. If $V_{ip}>V_{in}$, the most significant bit (MSB) $D_1$ is set to 1; otherwise, it is set to 0. The maximum capacitance $C_1$ of the positive pole is then switched to $V_{ref}$, and the negative pole is grounded. The subsequent process is similar to the above, and it is repeated until the LSB is confirmed. This switching mode requires fewer capacitors and switches compared to the above modes. It can reduce power consumption by the capacitive switches in direct comparison after the initial sampling, as shown in Equation (3).

$$E_{vcm-based}=\sum _{i=1}^{n-1}{2}^{n-3-2i}\times (2^i-1)C{V}_{ref}^2$$

(3)

Reducing the number of capacitors and power consumption of switching improves performance in biomedical applications. However, the switching of the capacitors will cause the voltage at both sides of the comparator to change simultaneously, increasing the probability of comparator errors caused by process variation. Therefore, the accuracy of the capacitor array will need to be more strictly controlled. Generally, biomedical signals have characteristics of low amplitude and low frequency, making a high-precision SAR ADC particularly important for detecting such weak signals. The capacitor array and the comparator circuit are the main factors that affect the accuracy of an SAR ADC. Hence, it is beneficial to avoid changing the voltages of both nodes of the comparator simultaneously, as this will significantly enhance the accuracy of signal conversion.

3. Proposed ADC Implementation

This design is utilized in biomedical wearable devices, where various biomedical signals have distinct requirements regarding sampling rates. Consequently, the focus of this research is not only to satisfy the demands for low power consumption and high SNR in wearable devices but also to ensure compatibility with two analog front-end circuits (AFEs) that operate at different sampling rates: one at a low speed of 400 samples per second (Sps) and the other at a high speed of 10 KSps. The system specs of the two AFEs are presented in

Table 1. Specifications of analog front-end circuit.

	fL(Hz)	fH(Hz)	CL(pF)	VSwing(V)
Low Speed	50	200	40	1.0
High Speed	1	5 K

. With the same capacity load ($C_L=40$ pF) and output swing ($V_{Swing}=1.0$ V), the low-speed bandwidth ranges from 50 to 200 Hz, while the high-speed bandwidth spans from 1 to 5 kHz. In this context, $f_L$ denotes the low cutoff frequency and $f_H$ represents the high cutoff frequency.

Figure 4 illustrates the architectural diagram of the continuous SAR ADC proposed in this design. To achieve low power consumption within the capacitor switching architecture, this article employs a relatively mature monotonic switching architecture, which can reduce power consumption by approximately 81% compared to traditional architectures [10]. The DAC switch, as one of the primary power-consuming components of the SAR ADC, has consistently been a focal point of research. However, it is important to note that the DAC switch accounts for only about 30% of the total power consumption of the SAR ADC; the remaining power consumption arises from the comparator and SAR logic. In terms of SNR processing, there is currently no noise shaping technology comparable to that of delta-sigma ADC. The SNR is primarily enhanced by minimizing the errors introduced by components during the conversion process. This discussion can be divided into three parts: first, the sample-and-hold circuit operating in hold mode, which introduces errors due to leakage current; second, the differential nonlinearity (DNL) [11] and integral nonlinearity (INL) [12] of the DAC; and, finally, the errors caused by capacitive coupling at the comparator input, known as kickback noise [13]. This article will address and propose improvements for the factors that affect SNR in subsequent chapters.

This article examines the relationship between the operating speed and resolution of SAR ADC, as discussed in the previous sections. An N-bit resolution necessitates N comparisons, and the number of switches required varies depending on the input signals; each switch operation corresponds to a capacitance. Consequently, an increase in the number of switch operations results in a longer conversion time. A synchronous clock has a consistent holding time, primarily determined by the signal that requires the longest conversion time. The holding time is mainly based on the signal that takes the longest to process. In contrast, an asynchronous clock adjusts the holding time based on different input signals. Consequently, the asynchronous conversion cycle is generally shorter than that of a synchronous clock. Figure 5 illustrates the timing diagram of SAR ADC. The internal clock generator operates asynchronously with the sampling clock. Therefore, when the positive edge of $CL{K}_E$ is detected, the sample-and-hold circuit holds the voltage while waiting for the internal clock generator to complete its cycle and proceed to the conversion phase. After the signal conversion is completed, the sample-and-hold circuit deactivates and the capacitor array begins tracking the input voltage until the next positive edge of $CL{K}_E$ is detected.

3.1. Capacitor Array

Monotonic switching mode is analogous to the previously described $V_{cm}$-based switching mode, as illustrated in Figure 6 [9]. In this mode, the comparator can perform direct comparisons without the need for a switching capacitor during the initial step. The key difference is that the positive pole of the capacitor is charged to $V_{ip}$, while the negative pole is returned to the common-mode voltage $V_{ref}$. The largest capacitor on the high-potential side is grounded based on the output of the comparator, whereas the capacitor on the opposite side remains unchanged. For instance, consider the first comparison: if $V_{ip}>V_{in}$, the positive side capacitor $C_1$ is grounded and the negative side capacitor retains the voltage $V_{ref}$. This process is repeated until the LSB is reached. In this mode, only one capacitor is switched per cycle, which reduces the charge transfer within the capacitor array and, consequently, lowers power consumption. As previously mentioned, the voltages on both sides of the comparator change simultaneously in Vcm-based switching mode. Any mismatch in the capacitor array on either side can lead to errors in the comparator’s output.

The flowchart of the monotonic switching method is illustrated in Figure 7A. After each comparison, only one voltage is altered, thereby reducing the error caused by the mismatch in the capacitor array. The switching logic of the capacitor can operate in either up-mode or down-mode. In the literature [8], down-mode is employed to accelerate the discharge of an n-type metal-oxide-semiconductor (NMOS). However, since the operational speed of this system is slower than that described in [8], there is no significant difference in the performance of a p-type metal-oxide-semiconductor (PMOS) and NMOS at low speeds. Nevertheless, when considering the input capacitor of the comparator, utilizing an N-type comparator with up-mode switching can minimize the size of the input capacitor. Therefore, we employ up-mode switching logic, and the simulation results are presented in Figure 7B, where the yellow signal represents $V_{ip}$ and the black signal represents $V_{in}$. Besides, we utilize a bootstrap sample-and-hold circuit, which can enhance the settling speed and input bandwidth. The power consumption of the monotonic switching method is presented in Equation (4). This consumption is slightly higher than that of the $V_{cm}$-based method, as the positive terminal of the capacitor is connected to $V_{ref}$ at the outset. This architecture offers the advantages of reducing the number of capacitor switches and minimizing comparator errors, as illustrated in

Table 2. Specifications of differential switching capacitor method.

	Conventional	Vcm-Based	Monotonic
No. of switches	6 n + 2	6 n + 2	4 n + 2
No. of capacitors	$2^n$	$2^{n-1}$	$2^n$− 1
Switching power	(2)	(3)	(4)

.

$$E_{mono}=\sum _{i=1}^{n-1}{2}^{n-2-i}C{V}_{ref}^2$$

(4)

3.2. Comparator

In this paper, we propose a dynamic comparator that utilizes the architecture of an n-type StrongARM latch, as illustrated in Figure 8 [14]. The dynamic comparator operates without quiescent current, resulting in lower average power consumption compared to a static comparator. A Monte Carlo analysis of the comparator’s offset voltage is presented in Figure 9A. To mitigate the impact of kick-back noise on the DAC signal, we incorporated resistor $R_0$ to limit the comparator’s slew rate. Although this addition slightly increases power consumption, it enhances overall performance by reducing power consumption, area, and noise from the preamplifier. To simulate the state of the capacitor array when the sampling circuit is deactivated, we added a large resistor and an appropriate capacitor to the comparator’s input. The simulation results, shown in Figure 9B, demonstrate the improvement in kick-back noise achieved by $R_0$, with the peak-to-peak value of the kick-back noise reduced by approximately half.

3.3. Clock Generator

Since this design pertains to biomedical wearable electronics, low power consumption is the most critical consideration. In this design, we will not utilize the traditional asynchronous delay path of SAR ADC. Given the low operational speed of this system, we will employ minimum-sized capacitor switches. This approach necessitates a longer delay path to accommodate the charging and discharging of the capacitors. Therefore, we propose using a controllable ring oscillator along with a buck converter and frequency divider circuit to create the required delay path for the capacitor’s charge and discharge, utilizing only a few components. The architecture of the clock generator circuit is illustrated in Figure 10, where the red frame indicates the buck area. The $M_P$ transistor is turned off when the ring oscillator is in sleep mode to prevent the stabilizing capacitor ($C_P$) from being overcharged by $V_{DD}$, which would lead to unnecessary power consumption. The bootstrap inverter increases the output voltage to mitigate leakage-related power loss in the subsequent stage of the circuit [15]. The Ready Detector is employed to verify the stability of the output signal, ensuring that an unstable clock signal does not adversely affect the circuit. The transistor ($M_P$) and resistor ($R_P$) work together to reduce power consumption, with RP serving as a reduction resistor. According to Equations (5) and (6), we can derive Equation (7). In Equation (7), the supply voltage is treated as a constant, allowing the oscillator’s output swing to be limited by $R_P$, thereby reducing power consumption.

$$Q=fC{V}_{swing}=It$$

(5)

$$I={\displaystyle \frac{1}{t}}CV=fC{V}_{swing}$$

(6)

$$P=I{V}_{DD}=fC{V}_{swing}{V}_{DD}$$

(7)

If the $M_P$ is removed from the circuit, $V_D$ will quickly charge to $V_{DD}$, resulting in unnecessary power consumption in the subsequent cycle. This is because the ring oscillator enters sleep mode without consuming current. The simulation results indicate that adding $M_P$ can reduce power consumption by approximately 7.5%, as illustrated in Figure 11.

3.4. Bootstrap Sample-and-Hold Circuit

Although the $V_{gs}$ of the transistor switch is zero, it still experiences leakage current at the drain. The sample-and-hold circuit struggles to maintain voltage, particularly at the FF 125 °C. Furthermore, when the ADC sampling rate is low, the sample-and-hold circuit must hold the voltage for an extended period, making leakage current a significant concern. To address this issue, we employ a bootstrap sample-and-hold circuit. In the hold mode, a negative $V_{gs}$ is applied to minimize the transistor’s leakage current. The output swing of the bootstrap inverter circuit ranges from $-\beta V_{DD}$ to ($\beta +1$) $V_{DD}$, as illustrated in Figure 12 [15], where $\beta$ represents the boosting efficiency, as defined in Equation (8).

$$\beta ={\displaystyle \frac{C_{Boost}}{C_{Boost}+C_{node}}}$$

(8)

Among them, $C_{Boost}$ refers to the boost capacitors ($C_{BP}$ and $C_{BN}$), while $C_{node}$ represents the total capacitance of the nodes ($N_{BP}$ and $N_{BN}$). The operation of the circuit is as follows: when the input transitions from low to high; $M_{P1}$ and $M_{N2}$ are turned off; and $IN{V}_N$, $C_{BN}$, and $M_{N1}$ form a charging path that charges $C_{BN}$ to $\beta V_{DD}$. At this point, the output voltage is equal to the $N_{BP}$ node, which is ($\beta +1$)$V_{DD}$. Conversely, when the input transitions from high to low, the charging path is similar to the one described above, consisting of $M_{P1}$, $C_{BP}$, and $IN{V}_P$. This configuration also charges $C_{BP}$ to $\beta V_{DD}$, but with the opposite polarity to $C_{BN}$. Consequently, the output voltage becomes -$\beta V_{DD}$, which pushes the sampling switch transistor into the cutoff region, thereby limiting leakage current. The total harmonic distortion (THD) simulation of the sample-and-hold circuit is illustrated in Figure 13. Even in the worst-case scenario, the performance of an 11-bit ADC still meets the specification requirements.

4. Simulation and Measurement

4.1. Simulation

The characteristics of an ADC can be categorized into static and dynamic components. Each category has specific parameters used to assess the performance of an ADC. In static analysis, differential nonlinearity (DNL) and integral nonlinearity (INL) are critical metrics. The comparator may introduce random offsets, leading to uneven quantization, which should be considered as additional noise at the input of the ADC. To evaluate the impact on SNR, we assume that the input signal is a full-swing sine wave with a resolution of N bits. The relationship between DNL and SNR is expressed in Equation (9) [11]. Here, $SN{R}_{(Q+DNL)}$ represents the SNR that includes both quantization noise and DNL. For instance, when DNL is set to 0.5 LSB, the SNR decreases by 3.04 dB. According to the design specifications of this study, DNL must be less than 0.5 LSB. The simulation results are illustrated in Figure 14. When simulating INL, a full-swing sine wave is utilized as the input signal, and the output code from the ADC is employed to sample the INL. It is well established that if the conversion function is not straight, harmonic distortion will present. Consequently, the relationship between INL and total harmonic distortion (THD) can be expressed in Equation (10) [12], where $P_{INL}\left(i\right)$ represents the ith harmonic power of INL in the power spectrum, H denotes the number of harmonics, and A indicates the full-scale range of the ADC. As illustrated in Figure 14, the distribution of INL across each corner is less than 1 LSB in both pre-simulation and post-simulation analyses.

$$SN{R}_{Q+DNL}=6.02N+1.76-10log(1+4DN{L}^2)$$

(9)

$$THD={\displaystyle \frac{8}{A^2}}\sum _{i=2}^H{P}_{INL}\left(i\right)$$

(10)

The dynamic characteristics of the ADC differ from its static characteristics. The performance of the ADC varies with changes in signal frequency. To effectively observe the influence of frequency, the signal must undergo Fast Fourier Transform (FFT) conversion to obtain a spectrum diagram, as illustrated in Figure 15. Under the simulation conditions, with a sampling rate of 10 KSps, the SNR obtained are 66.47 dB (pre-simulation) and 66.2 dB (post-simulation). The THD are −90.73 dB and −72.93 dB. The Spurious-Free Dynamic Range (SFDR) measures 86.6 dBc and 76.08 dBc. The Signal-to-Noise and Distortion Ratio (SINAD) is 66.45 dB and 65.36 dB. Finally, the ENOB is 10.75 bits and 10.56 bits.

The simulation results at various temperatures and corners are presented in

Table 3. The performance of SAR ADC @ 10 KS/s.

	Pre-Simulation			Post-Simulation
	FF	TT	SS	FF	TT	SS
$V_{DD}$ (V)	1.32	1.2	1.08	1.32	1.2	1.08
Temp. (°C)	0	25	80	0	25	80
Input Freq. (Hz)	72.02
${DNL}_{MAX}$ (LSB)	0.503	0.252	0.252	0.494	0.494	0.262
${INL}_{MAX}$ (LSB)	0.534	0.44	0.408	0.735	0.528	0.598
THD (dB)	−77.44	−90.73	−82.6	−74.67	−72.93	−76.74
SNR (dB)	66.49	66.47	66.48	66.28	66.2	66.17
SFDR (dBc)	77.84	86.6	83.14	76.25	76.08	77.61
SINAD (dB)	66.16	66.45	66.38	65.69	65.36	65.81
ENOB (Bits)	10.7	10.75	10.73	10.62	10.56	10.64

. Simulations were conducted under the conditions of TT${25}^{°}$C, FF$0^{°}$C, and SS${80}^{°}$C, all of which comply with the system specs outlined in this study for biomedical wearable devices. Both SNR and the SINDR must exceed 60 dB, the THD must be less than −60 dB, and the ENOB must be greater than 9 bits. Figure 16 displays the chip layout along with actual photographs. The chip area measures 823 × 826 $\mathsf{\mu }$m² (including ESD I/O), while the core area is 418 × 389 $\mathsf{\mu }$m² (excluding ESD I/O).

4.2. Measurement

In medical applications, wearable devices must process multiple biomedical signals that operate at different rates. Therefore, we propose an SAR ADC capable of functioning at sampling rates of 400 Sps and 10 KSps. For measurement purposes, we utilized the Audio Precision SYS-2722 to generate a stable low-frequency input signal. The output signal was observed and exported using the Agilent DSO9104A oscilloscope and, subsequently, analyzed and plotted in MATLAB R2024a. To mitigate potential failures of the internal clock generator, we employed the MOTECH FG708S external signal generator for assistance. The block diagram of the measurement setup is illustrated in Figure 17. To avoid mismatches in the differential output cable and to minimize the impact of high-frequency noise during the Audio Precision measurements, we used the AD8138 differential amplifier to convert the input signal from single-ended to differential, as shown in Figure 18A. To ensure that the main signals within the bandwidth are not filtered out, the cutoff frequency of the low-pass filter is set to approximately 50 KHz. The Bode plot of the low-pass filter is presented in Figure 18B, indicating a gain of −6.2 dB and a cutoff frequency of 46.8 KHz.

Figure 19A presents the measurement results of the chip’s internal clock generator. The input signal frequency is 70.02 Hz. The yellow and blue signals represent the differential output signals $V_{ip}$ and $V_{in}$ of the AD8138, respectively. The green signal indicates the peak-to-peak voltage of $V_{DDA}$, which is marked within a green box at approximately 4.1 mV_PP. In the clock generation circuit depicted above, the transistor $M_P$ serves to stabilize the voltage at the $V_D$ terminal, thereby reducing energy consumption. Figure 19A provides a zoomed-in view. To facilitate the observation of the digital output results, the signals are arranged from top to bottom as follows: $CL{K}_I$, $CL{K}_E$, and $D_{out}$. The conversion process occurs during the $CL{K}_E$ duty cycle, and the maintenance time is adjusted in conjunction with the internal EN signal.

Figure 20 and Figure 21 illustrate the spectrum analysis of the chip using MATLAB at a specific sampling frequency. The test signal is provided by Audio Precision. Sine waves of 10.08 Hz and 72.02 Hz are utilized for different sampling rate modes. THD is measured at −73.79 dB, and the peak-to-peak voltage is 355 mV. At a sampling rate of 400 Sps, the THD is −64.31 dB, SFDR is 72.2 dBc, and the ENOB is 9.27 bits. In the sampling rate mode of 10 KSps, the THD is −66.26 dB, the SFDR is 78.88 dBc, and the ENOB is 9.2 bits.

5. Conclusions

In this paper, an 11-bit fully differential asynchronous successive approximation register analog-to-digital converter is implemented using TSMC 0.18 $\mathsf{\mu }$m CMOS technology. The supply voltage is 1.2 V, and the input voltage range is from 300 mV to 900 mV. The converter demonstrates strong performance with a sampling rate ranging from 400 Sps to 10 KSps. All data are suitable for applications involving biomedical wearable devices and can accommodate most biomedical signals through two different sampling rates. Notably, in the low-speed mode of 400 Sps, the power consumption is only 36.5 nW, which is favorable when compared to existing literature. This performance is attributed to the internal clock generator design, which effectively reduces power consumption. Additionally, the DNL is 0.256 LSB and the INL is 0.459 LSB, both of which demonstrate commendable performance, as illustrated in

Table 4. Comparison with the most advanced SAR ADC.

	[16]	[17]	[18]	[19]	[20]	[21]	This Work
$V_{DD}$ (V)	1.0	0.6	0.8	1.8	1.0	1.0	1.2
CLK Mode	Syn.	Asyn.	Syn.	Asyn.	Syn.	Syn.	Asyn.
Technology (nm)	130	65	65	180	130	180	180
Sampling Rate (Hz)	1 K	500	10 K	2 K	10 K	100 K	400	10 K
Resolution (Bits)	10	8	14	16	12	10	11
${DNL}_{MAX}$ (LSB)	0.61	1.0	2.2	0.7	0.41	0.33	0.256
${INL}_{MAX}$ (LSB)	0.46	1.8	2.2	3.65	0.74	0.25	0.459
SFDR (dBc)	67.6	-	88.8	98.2	64.8	54.14	72.2	78.9
ENOB (Bits)	9.13	7.14	12.5	13.8	10.5	8.84	9.27	9.2
Power (W)	53 n	1.8 n	1.98 $\mathsf{\mu }$	7.93 $\mathsf{\mu }$	110 n	0.67 $\mathsf{\mu }$	36.5 n	932 n

. In the future, the SNR can be enhanced through noise shaping techniques. During measurements, the use of an external power supply generates unnecessary noise on the PCB, leading to poor SINAD and consequently affecting the ENOB. To address this issue, a Bandgap voltage reference circuit can be implemented to minimize noise generated during wiring, thereby improving ENOB performance.