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Electronics
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Analog and Mixed-Signal Circuit Designs and Their Applications
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Analog and Mixed-Signal Circuit Designs and Their Applications

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: 15 November 2024 | Viewed by 3227

Special Issue Editors

Dr. Hyuntak Jeon

E-Mail Website
Guest Editor
School of Electronics Engineering, Chungbuk National University (CBNU), 1 Chungdae-ro, Seowon-Gu, Cheongju 28644, Republic of Korea
Interests: mixed-signal circuit designs for sensor interface IC; electrical system designs for guided ballistic missile systems
Dr. Soon-Jae Kweon

E-Mail Website
Guest Editor
School of Information, Communications and Electronics Engineering, The Catholic University of Korea, 43 Jibong-ro, Bucheon-si 14662, Gyeonggi-do, Republic of Korea
Interests: analog and mixed-signal ICs; low-power sensor interface ICs; biomedical circuits and systems; wireless communication ICs

Special Issue Information

Dear Colleagues,

The advancement of digital integrated circuits has undoubtedly driven the development of various hardware design technologies, including the field of artificial intelligence.

However, as systems have become more sophisticated, there has been a growing need to design analog and mixed-signal integrated circuits optimized for various application domains.

Therefore, in this Special Issue, we will cover various techniques for the design of analog and mixed-signal integrated circuits and their diverse applications, aiming to explore various circuit design techniques for emerging application areas.

Dr. Hyuntak Jeon
Dr. Soon-Jae Kweon
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • analog integrated circuits
  • mixed-signal integrated circuits
  • power management integrated circuits
  • sensor interface integrated circuits
  • analog-to-digital converter
  • digital-to-analog converter

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Published Papers (4 papers)

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Research

20 pages, 3808 KiB  
Article
Design of an Internal Asynchronous 11-Bit SAR ADC for Biomedical Wearable Application
by Muh-Tian Shiue, Yu-Fan Lo and Chih-Yao Jung
Electronics 2024, 13(17), 3549; https://doi.org/10.3390/electronics13173549 - 6 Sep 2024
Viewed by 468
Abstract
This paper introduces a fully differential asynchronous successive approximation register analog-to-digital converter (SAR ADC) designed for biomedical signal processing. By extending the tracking time and utilizing fully differential inputs in the analog front-end circuit, the signal-to-noise ratio is enhanced in the system. Using [...] Read more.
This paper introduces a fully differential asynchronous successive approximation register analog-to-digital converter (SAR ADC) designed for biomedical signal processing. By extending the tracking time and utilizing fully differential inputs in the analog front-end circuit, the signal-to-noise ratio is enhanced in the system. Using an asynchronous clock can reduce power consumption across a wider range of sampling frequencies. In comparison to conventional architecture in high-speed SAR ADC, using an internal clock generator can operate at lower frequencies. A fully differential input can eliminate the DC offset of the analog front-end circuit and reduce the adverse effects of process variation, voltage variation, and temperature variation. The chip is implemented by TSMC 0.18 μm complementary metal-oxide-semiconductor (CMOS) technology, and the chip area is 0.680 mm2 (including ESD I/O PAD). At a 1.2 V supply, the maximum sampling rate is 10 Kilo Samples per second (KSps). The implemented ADC has an 11-bit resolution, while the input voltage range is 300∼900 mV. The total power consumption is 1.7 μW, with the core power consumption at 932 nW. Full article
(This article belongs to the Special Issue Analog and Mixed-Signal Circuit Designs and Their Applications)
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16 pages, 15653 KiB  
Article
A Low-Power Continuous-Time Delta-Sigma Analogue-to-Digital Converter for the Neural Network Architecture of Battery State Estimation
by Muh-Tian Shiue, Yang-Chieh Ou and Guan-Shum Li
Electronics 2024, 13(17), 3459; https://doi.org/10.3390/electronics13173459 - 30 Aug 2024
Viewed by 432
Abstract
Electric vehicle systems and smart grid systems are setting stringent development targets to respond to global trends in energy saving, carbon reduction, and sustainable environmental development. In the field of batteries, there has been extensive discussion on the estimation of battery charge. In [...] Read more.
Electric vehicle systems and smart grid systems are setting stringent development targets to respond to global trends in energy saving, carbon reduction, and sustainable environmental development. In the field of batteries, there has been extensive discussion on the estimation of battery charge. In battery management systems (BMSs) and charging/discharging systems, the accuracy of the measurement of battery physical parameters is critical, as it directly affects the system, alongside the algorithm’s estimation and error correction. Therefore, this paper proposes incorporating a low-power continuous-time delta-sigma analogue-to-digital converter into a battery measurement system to support deep learning algorithms for battery state estimation. This approach aims to maintain the accuracy of battery state estimation while reducing latency and overall system power consumption. Implemented using the UMC 0.18 μm CMOS 1P6M process, the proposed design achieves a measured signal-to-noise distortion ratio (SNDR) of 78.42 dB, an effective number of bits (ENOB) of 12.73 bits, and a power consumption of approximately 15.97 μW. The chip layout area is 0.67 mm × 0.56 mm. By applying delta-sigma modulators to energy management systems, this solution aims to increase the total number of battery monitoring units while reducing overall power consumption and construction costs. Full article
(This article belongs to the Special Issue Analog and Mixed-Signal Circuit Designs and Their Applications)
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17 pages, 1577 KiB  
Article
Readout Circuit Design for RRAM Array-Based Computing in Memory Architecture
by Xingjie Xu, Aili Wang and Yuhang Shui
Electronics 2024, 13(13), 2478; https://doi.org/10.3390/electronics13132478 - 25 Jun 2024
Viewed by 796
Abstract
In recent advancements, the traditional von Neumann architecture has been challenged by the computational needs of AI. This is due to its high power and data transfer costs. As a solution, the computing-in-memory (CIM) architecture, which combines storage and computation, has gained attention [...] Read more.
In recent advancements, the traditional von Neumann architecture has been challenged by the computational needs of AI. This is due to its high power and data transfer costs. As a solution, the computing-in-memory (CIM) architecture, which combines storage and computation, has gained attention for its superior computational power and energy efficiency. Within CIM, using resistive random access memory (RRAM) arrays, the readout circuit, which converts analog outputs from multiply–accumulate operations into digital signals, faces limitations due to its area and power consumption. There are mainly two types of CIM readout circuits for analog types: the traditional ADC type and the non-traditional type. This paper presents two types of readout circuit designs. The first is a low-power, compact successive approximation register (SAR) analog-to-digital converter (ADC) readout circuit. The core circuit is an 8-bit SAR ADC operating at 70 MS/s. It incorporates a linearity-improved bootstrapped switch to minimize leakage and enhance linearity, whose spurious-free dynamic range (SFDR) has been improved by 10.1 dB from 76.78 dB to 86.88 dB, and whose signal-to-noise and distortion ratio (SNDR) has increased by 4.56 dB from 75.13 dB to 79.69 dB. The delay of a transconductance-enhanced dynamic comparator is reduced from 184 ps to 149 ps, presenting a performance improvement of approximately 20%. Concurrently, the energy consumption decreased from 178 μm to 132 μm, attaining an improvement of roughly 26%. A “sandwich” capacitor structure is used that reduces the overall area of the layout. After layout and post-simulation, this circuit occupies only 49.6 μm × 51.5 μm, consumes 553 μW power, has a SINAD of 46.22 dB, and has an SFDR of 57.21 dB. The second is a current controlled oscillator (CCO)-type readout circuit, which comprises a CCO oscillator with low process-sensitivity. The readout circuit also utilizes an op-amp and current mirrors for a negative feedback loop, ensuring a constant voltage across the RRAM arrays. The frequency generated through the CCO is controlled by the current, and quantified by a counter, supporting different weights quantification per ReRAM column without additional digital weighting. This circuit achieves 95-level resolution, 5.2 μs delay, and an average consumption of 183.1 μW. A comparative analysis highlights that traditional ADC readout circuits offer high resolution and speed but are limited by their high power and area costs, often overshadowing CIM arrays’ benefits. Thus, for applications with more lenient resolution and speed requirements, non-traditional readout circuits present considerable advantages. Full article
(This article belongs to the Special Issue Analog and Mixed-Signal Circuit Designs and Their Applications)
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14 pages, 3439 KiB  
Article
Baseline Calibration Scheme Embedded in Single-Slope ADC for Gas Sensor Applications
by Jang-Su Hyeon and Hyeon-June Kim
Electronics 2024, 13(7), 1252; https://doi.org/10.3390/electronics13071252 - 28 Mar 2024
Viewed by 1018
Abstract
This paper introduces a single-slope analog-to-digital converter (SS ADC) with an embedded digital baseline calibration scheme designed to improve the accuracy and reliability of gas sensor measurements. The proposed SS ADC effectively leverages an up/down counter mechanism to ensure stable signal extraction from [...] Read more.
This paper introduces a single-slope analog-to-digital converter (SS ADC) with an embedded digital baseline calibration scheme designed to improve the accuracy and reliability of gas sensor measurements. The proposed SS ADC effectively leverages an up/down counter mechanism to ensure stable signal extraction from gas sensors, despite variations in the baseline distribution. The proposed SS ADC initiates with a down counting operation to capture the initial output value of the gas sensor, which, after A/D conversion, is stored as a reference point for future readings. Subsequent gas sensor output values are derived by performing an up counting operation from this baseline reference. This approach allows for real-time correction of the baseline during the SS A/D conversion process, obviating the need for complex post-processing and baseline correction algorithms. The proposed SS ADC with the baseline calibration scheme was designed using a 0.18 μm standard CMOS process to confirm its feasibility. It demonstrated a signal-to-noise and distortion ratio (SNDR) of 57.56 dB and a spurious-free dynamic range (SFDR) of 59.02 dB, resulting in an effective number of bits (ENOB) of 9.27 bits in the post-simulation level. The proposed SS ADC has a total power consumption of 1.649 mW. This work offers an efficient solution to the baseline distribution problem in gas sensors, facilitating more reliable and accurate gas detection systems. Full article
(This article belongs to the Special Issue Analog and Mixed-Signal Circuit Designs and Their Applications)
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