A Fully Synthesizable Fractional-N Digital Phase-Locked Loop with a Calibrated Dual-Referenced Interpolating Time-to-Digital Converter to Compensate for Process–Voltage–Temperature Variations

Abstract

This paper presents advancements in the performance of digital phase-locked loop (DPLL)s, with a special focus on addressing the issue of required gain calibration in the time-to-digital converter (TDC) within phase-domain DPLL structures. Phase-domain DPLLs are preferred for their simplicity in implementation and for eliminating the delta–sigma modulator (DSM) noise inherent in conventional fractional-N designs. However, this advantage is countered by the critical need to calibrate the gain of the TDC. The previously proposed dual-interpolated TDC(DI-TDC) was proposed as a solution to this problem, but strong spurs were still generated due to the TDC resolution, which easily became non-uniform due to PVT variation, degrading performance. To overcome these problems, this work proposes a DPLL with a new calibration system that ensures consistent TDC resolution matching the period of the digitally controlled oscillator (DCO) and operating in both the foreground and background, thereby maintaining consistent performance despite PVT variations. This study proposes a DPLL using a calibrated dual-interpolated TDC that effectively compensates for PVT variations and improves the stability and performance of the DPLL. The PLL was fabricated in a 28-nm CMOS process with an active area of only 0.019 mm², achieving an integrated phase noise (IPN) performance of −17.5 dBc, integrated from 10 kHz to 10 MHz at a PLL output of 570 MHz and −20.5 dBc at 1.1 GHz. This PLL operates within an output frequency range of 475 MHz to 1.1 GHz. Under typical operating conditions, it consumes only 930 µW with a 1.0 V supply.

1. Introduction

In wireless communication systems, the demand for high-performance PLLs to generate carrier frequencies is increasing due to advancements in technologies such as Wi-Fi and cellular networks. Following the publication of research on SSPLL architectures, recent PLL studies have shown a preference for analog PLLs that utilize analog voltage sampling methods [1,2,3]. Conversely, in the era of the Internet of Things (IoT), where protocols such as Bluetooth low energy (BLE), Zigbee, and LoRa are widely used, low power consumption is emerging as a more crucial factor than high performance. In response to these requirements, digital phase-locked loops (DPLLs) remain an attractive choice. DPLLs feature a digital-intensive design, allowing for miniaturization. As the primary circuits are digitized, they consume minimal switching power, resulting in low power consumption. Additionally, DPLLs possess programmable features, making them easily adaptable to various applications. They also offer strong resilience against process, voltage, and temperature (PVT) variations, ensuring stable performance. These attributes make DPLLs a key technology in the advancement of modern electronic devices.

In DPLL design, various components present challenges, with the time-to-digital converter (TDC) being particularly significant. Designing the TDC with appropriate resolution is crucial, which is why vernier-type TDC structures are often adopted for linear TDC design [4,5]. However, vernier-type TDCs require calibration using complex circuits like delay-locked loops (DLLs) due to variations in delay cell values across process corners and different chips. Additionally, to cover the quantization error (QE) noise of the delta–sigma modulator (DSM) typically used in standard DPLL structures, a TDC with a wide range is necessary, which introduces further complications.

To mitigate these issues, the phase-domain DPLL architecture can be utilized among various fractional-N DPLL structures [6,7]. Figure 1 shows the circuit diagrams of a conventional phase-domain DPLL. In a phase-domain DPLL, the periods of the digitally controlled oscillator (DCO) are counted during one reference period, and the digitized DCO frequency value is then compared with the frequency command word (FCW). The phase-domain DPLL does not require a delta–sigma modulator module for fractional adjustment, thereby eliminating the quantization noise associated with DSM and achieving superior noise performance at high-frequency out bands. Furthermore, the absence of a digital-to-time converter (DTC) for removing DSM quantization noise simplifies the overall structure. However, the phase-domain DPLL imposes stringent requirements on the TDC, such as high linearity, fine resolution, and a wide conversion range that matches the DCO period, in order to achieve accurate and precise digitization. As a result, this can easily lead to the degradation of the quantization performance, linearity, and time resolution (T_RES) of the TDC. Degradation in TDC performance can introduce spurious tones during the frequency synthesis process of the PLL, significantly impacting the quality of the output signal of the PLL. Spurious tones arise from frequency errors caused by the inability of TDC to accurately measure time intervals, leading to an increase in phase noise and a reduction in the spectral purity of the output signal. TDCs are particularly susceptible to PVT (process, voltage, temperature) variations, which can exacerbate these performance degradations. As a result, unwanted frequency components may be introduced into the output signal, causing adjacent channel interference or signal distortion. This can compromise the reliability of data transmission in communication systems, particularly in applications that require high performance and precision. Therefore, maintaining stable TDC performance is crucial to ensuring the overall reliability and effectiveness of the PLL. Therefore, for TDC gain normalization, it is essential to match the total conversion range of the TDC to one cycle of the DCO using additional circuit techniques for TDC gain matching. This necessitates a complex gain calibration system [8].

To address these challenges, prior work [9,10] proposed the dual-referenced interpolating TDC (DI-TDC). This design leverages the advantages of a digital-intensive approach, making nearly all blocks synthesizable. The dual-referenced interpolating technique enables the implementation of the TDC transfer function without the need for precise TDC gain matching. This enables approximate matching without the need for deeply designed delay cells in nearby frequency bands. However, if the TDC gain is not accurately matched, it can result in significant spurs. In applications requiring coverage of wide frequency bands, such as LoRa (470 to 928 MHz) or Zigbee (868 to 915 MHz), it is essential to design delay chains specific to each frequency band. Additionally, there is a need to address variations due to process, voltage, and temperature (PVT) changes.

This paper proposes a low-power DPLL for IoT applications, such as LoRa and Zigbee, operating in the 475 MHz to 974 MHz band. In the phase-domain DPLL architecture using a DI-TDC, a method is presented that allows the TDC resolution to be precisely matched to the DCO cycle. This ensures that the TDC resolution is optimized for any given band. The technique proposed in this paper enables the DI-TDC performance to remain stable across various conditions, effectively mitigating the spurs identified as problematic in previous research.

2. System Architecture

Figure 2 illustrates the circuit diagram of fractional-N digital PLL with the proposed calibrated DI-TDC. Fundamentally, the phase-domain PLL operates by measuring the phase of the DCO output at each reference clock and comparing it in the phase domain [11]. In the work described in this paper, a differentiator has been added to the design for obtaining frequency error during the locking process as needed. The phase information of the DCO is obtained using a rotational counter and a TDC. The rotational counter detects the integer part of the phase, while the TDC detects the finer fractional phase. The most critical component determining the overall jitter performance of the PLL is the TDC, which detects fine phase variations.

In this work, a DI-TDC structure is utilized for the TDC [9]. In phase-domain PLLs, TDC gain matching is essential, meaning that the TDC’s conversion range must precisely match the DCO period. Failure to meet this condition results in in-band level degradation and spur tone deterioration, critically impacting performance. Consequently, phase-domain PLLs typically require TDC gain compensation circuits. However, the DI-TDC does not require additional compensation circuits. The DI-TDC is basically used with a multi-phase DCO, interpolating phase information between adjacent DCO phases based on the rising edge of the reference clock, and automatically performing first-order compensation. Therefore, even if the delays of the delay cells composing the TDC do not exactly match one DCO period, the DI-TDC can still maintain effective resolution to some extent.

However, even when using the DI-TDC, each delay cell in the TDC must have a delay time that ensures optimum performance based on the target T_DCO. If the reference delay chain is synthesized as in previous papers and the actual delay values significantly deviate from the optimum delay, there will be substantial degradation in both in-band performance and spur performance. As a result, optimal performance cannot be guaranteed. To address this, this paper proposes a calibration circuit that covers a wide band from 475 MHz to 974 MHz, is insensitive to PVT variations, and ensures optimal in-band phase noise performance for any DCO frequency target. The calibrated reference delay chain shown in Figure 2 adjusts the delay of the buffers generating each reference delay phase through calibration, ensuring that the reference delay phases of DI-TDC precisely match the current T_DCO. Consequently, the DI-TDC always maintains the appropriate conversion range and accurate Δt_tdc. This calibration is initially performed in the foreground before the PLL begins operation and continues periodically in the background while the PLL is operating, thereby ensuring optimal DI-TDC performance despite environmental changes.

3. Delay Calibrated Dual-Referenced Interpolating TDC

Figure 3 and Figure 4 show the circuit diagrams of the calibration loop and one of its components, the digitally controlled delay inverter (DCDI), respectively, as proposed in this paper. In prior research, the delay chain used in DI-TDCs was composed of nine buffers, each consisting of two synthesized standard cell inverters. This configuration generated delayed reference phases that determined the TDC resolution (Δt_tdc). Consequently, the propagation delay (t_pd) of the inverters determined the Δt_tdc, resulting in a TDC conversion range independent of the DCO oscillation frequency. This characteristic made the delay chain in the DI-TDCs used in previous studies inherently susceptible to PVT variations, leading to poor linearity and non-uniformity in Δt_tdc, which consequently caused spurs that degraded PLL performance. To address these issues, this paper proposes a delay calibrated DI-TDC that includes a calibrated reference delay chain. The calibrated reference delay chain has been designed with eight buffers, each composed of two DCDIs, and an additional DCDI for load matching. Therefore, the calibrated reference delay chain generates the eight reference delay phases, which are calibrated to have a conversion range that precisely matches each phase of the five-phase DCO. The calibrated reference delay chain is calibrated through a calibration loop. The calibration loop consists of a replica DCO that is identical to the calibrated reference delay chain, except for the connection between the input and output to enable oscillation, along with a counter, differentiator, comparator, and binary search engine.

In the calibrated reference delay chain, the inverters that make up the buffers generating the delayed reference phases are designed as DCDIs to allow digital control of the Δt_tdc of the reference delay chain. The t_pd of the DCDI is determined by a 6-bit binary digital control code, refd_ctr, making it suitable for ensuring that the DI-TDC operates with the Δt_tdc precisely matching the oscillation period of DCO.

The primary goal of the calibration loop is to ensure that the DI-TDC within the PLL maintains precise time resolution (T_RES), even in the presence of environmental variations such as temperature changes or supply voltage fluctuations. To achieve this, the calibration loop continuously monitors and adjusts the frequency of the replica DCO. The replica DCO is a critical component that mirrors the behavior of the actual DCO within the PLL. It is constructed using the same DCDIs as those used in the calibrated reference delay chain, ensuring that both operate under identical conditions.

The calibration process begins with the differentiator, which measures the number of rising edges of the replica DCO within a single cycle of the reference clock. This count effectively represents the frequency of the replica DCO. The measured frequency is then compared with the target frequency codeword (N.f_TARGET), which is a predefined value corresponding to the desired operating frequency of the DI-TDC. For example, if the target frequency codeword is set to 1 GHz, the differentiator checks if the replica DCO is oscillating at 1 GHz by counting the number of edges. Any deviation from this target frequency indicates that the replica DCO is not perfectly aligned with the desired operating conditions, triggering further calibration steps.

The binary search engine then plays a crucial role in refining the frequency of the replica DCO to match the target frequency. This engine operates using a successive approximation register (SAR) algorithm, starting with an initial frequency adjustment value. Starting from this initial value, it halves the frequency difference to find the appropriate correction value, which is then sent to the replica DCO for frequency adjustment. It assesses whether the frequency of replica DCO is higher or lower than the target using a comparator. If the frequency is too high, the engine reduces the adjustment value by half; if too low, it increases it by half. This process repeats, halving the adjustment step size each time, until the frequency is sufficiently close to the target frequency. For instance, if the initial frequency difference is 10 MHz, the first adjustment might reduce this to 5 MHz, then to 2.5 MHz, and so on, until the difference becomes negligible.

Once the binary search engine converges on the correct frequency adjustment, it generates a control signal, referred to as refd_ctr, which directly influences the DCDIs in the calibrated reference delay chain. This control signal ensures that the delay time Δt_tdc produced by the DCDIs matches the target frequency of the PLL. As a result, the delayed reference phases generated in the DI-TDC are precisely aligned with the DCO period of PLL. This alignment is critical because it ensures that the DI-TDC can accurately measure time intervals with the desired resolution. The entire process, from frequency measurement to binary search adjustment, is repeated periodically to compensate for any environmental changes, such as temperature variations, that could affect the frequency of DCO. This continuous calibration guarantees that the PLL remains stable and the TDC operates with high accuracy, even in varying environmental conditions. The f_{Replica_DCO} is calculated to ensure that the DI-TDC has the desired Δt_tdc, using the following equation:

$${\mathrm{f}}_{\mathrm{R}\mathrm{e}\mathrm{p}\mathrm{l}\mathrm{i}\mathrm{c}\mathrm{a}\_\mathrm{D}\mathrm{C}\mathrm{O}}={\displaystyle \frac{1}{{\mathrm{N}}_{\mathrm{D}\mathrm{C}\mathrm{D}\mathrm{I}}·2·{\mathrm{t}}_{\mathrm{p}\mathrm{d}\_\mathrm{D}\mathrm{C}\mathrm{D}\mathrm{I}}}}$$

which is derived by modifying the formula for calculating the oscillation frequency of the ring oscillator. In the equation, N_DCDI represents the number of DCDIs, and t_{pd_DCDI} represents the propagation delay of the DCDI. When the replica DCO frequency locks to the f_{Replica_DCO} after inputting the corresponding N.f_TARGET, the resulting refd_ctr digital signal directly controls the reference delay chain. Through this process, the Δt_tdc of the DI-TDC, resulting from the calibrated reference delay chain, is adjusted to match the DCO period of the PLL, ensuring that the TDC operates robustly even with environmental changes.

Figure 5 illustrates the timing diagram of the calibrated DI-TDC, providing a visual representation of the phases involved in the calibration process. In this diagram, T_DCO produces five distinct phases. The time interval between these phases, denoted as ΔΦ, is calculated by dividing the T_DCO by 5. This precise division ensures uniform calibration across all phases. The effectiveness of calibration loop is demonstrated by how it adjusts the delay time Δt_tdc of each buffer in the calibrated reference delay chain to match ΔΦ/8, ensuring that the conversion range of the DI-TDC aligns perfectly with the T_DCO. Since the calibration loop has completed its operation, the delay time of each buffer in the calibrated reference delay chain, Δt_tdc, is precisely equal to ΔΦ divided by 8. Consequently, the conversion range of the DI-TDC, determined by the eight rising edges of the refd, is exactly ΔΦ. The loop adjusts the DI-TDC to obtain the appropriate time resolution (T_RES) through foreground calibration before the PLL begins operation. During PLL operation, periodic background calibration is performed based on a reference signal selected within the 100 Hz to 50 kHz range, ensuring that the TDC maintains its performance despite ongoing environmental changes.

Figure 6 shows the measured results of the calibrated reference delay chain. As the refd_ctr code increases, the PMOS R_ON resistance of the DCDI decreases, reducing the RC time constant and thereby decreasing the delay corresponding to 2·t_{pd_DCDI}. Additionally, three distinct delay characteristics are observed through manual coarse band-selection voltage adjustments. By adjusting the band-selection voltage, which is the supply voltage for the delay chain, according to the output frequency of the main DCO, the delay chain can be made to operate within the desired band. The blue band (band-selection voltage: 0.8 V) indicates a delay range of approximately 37.6 ps to 52.6 ps, which covers the f_DCO range of 475 MHz to 665 MHz. Similarly, the green band (band-selection voltage: 1.0 V) shows a delay range of 30 ps to 40.5 ps, covering the f_DCO range of 618 MHz to 831 MHz. The red band (band-selection voltage: 1.2 V) represents a delay range of 25.6 ps to 35 ps, covering the f_DCO range of 712 MHz to 974 MHz. This enables the selection of the optimal TDC resolution for DCO outputs ranging from 475 MHz to 974 MHz.

4. Experimental Results

Figure 7 and Figure 8 illustrate the PLL performance based on the delay time of the TDC reference delay chain at a 570 MHz DCO output frequency. The DI-TDC achieves optimum performance when Δt_tdc equals the time Δt, which is obtained by dividing one period of the DCO by the five DCO phases and further dividing by the eight phases of the delay chain. Therefore, if Δt_tdc is either smaller or larger than this value, conversion range of the DI-TDC becomes unmatched to the T_DCO, resulting in degraded PLL performance. In Figure 8, when the phase noise level is compared with the calibrated optimum level, it can be observed that if the refd_ctr is either larger or smaller, the in-band level decreases by approximately 5 dBc/Hz, and the spur increases due to errors introduced by Δt_tdc, leading to a degradation in PLL performance. Figure 8 shows the measured PLL RMS jitter performance as a function of refd_ctr. Consistent with previous results, the PLL exhibited optimum performance at refd_ctr = 10, where Δt_tdc had the correct value. As Δt_tdc deviated from this value, either becoming smaller or larger, the PLL performance progressively worsened.

Figure 9 shows the phase noise performance variations at a 1.1 GHz DCO output frequency based on different Δt_tdc values. In Figure 9, (a) shows the phase noise level when refd_ctr = 0, while (b) shows the phase noise level when refd_ctr = 32, both compared against the calibrated performance. The RMS jitter and IPN corresponding to the calibrated performance are highlighted in panel (a). Comparing the in-band levels, it can be observed that the performance improvement due to the calibrated DI-TDC is approximately 10 dBc/Hz relative to (a). Additionally, a reduction in spur is also evident. Similar to the observations at the 570 MHz band, the PLL achieved optimal performance in all aspects, including in-band level and spurs, when Δt_tdc was accurately calibrated according to the calibrated reference delay chain.

Table 1. Performance comparisons with previous RO-based fractional-N frequency synthesizers.

	This Work	ISSCC’17 [12]	JSSC’19 [13]	JSSC’19 [14]	JSSC’22 [15]	ISSCC’20 [16]
Technology	28 nm	28 nm	28 nm	40 nm	65 nm	40 nm
Architecture	Phase-domain DPLL	DPLL	Phase-domain DPLL	Phase-domain ADPLL	DPLL	DPLL
Fractional-N support	Yes	Yes	Yes	Yes	Yes	No
PVT compensation	Yes	No	No	No	No	No
Fref (MHz)	50	250	24 **	37.5	24	21
Frequency out (GHz)	1.1	1	0.646 **	0.6	1	5.25
Frequency range (GHz)	0.625 (0.475–1.1)	0.75 (0.25–1)	0.167 ** (0.479–0.646)	X	0.37 (0.79–1.16)	X
Power (mW)	0.93	15.2	0.669 **	1.55	3.36	9.01
Area (mm2)	0.019	0.0047	0.0043	0.0166	0.075	0.161
Power efficiency (mW/GHz)	0.845	15.2	1.035 **	3.11	1.55	1.72
Integ. phase noise (dBc)	−20.55 (10 k to 10 M)	-	-	-	−38.8 (10 k to 10 M)	−26.84 (1 k to 100 M)
Integ. RMS jitter (ps)	19.0 (10 k to 10 M)	3.3 (1 k to 100 M)	9.45 **	-	2.55 (10 k to 10 M)	1.95 (1 k to 100 M)
FoMPN * (dB)	−214.7	−218	−222.2	−208.5	−226.6	−224.6

* $\mathrm{F}\mathrm{o}{\mathrm{M}}_{\mathrm{P}\mathrm{N}}=10·\mathrm{l}\mathrm{o}\mathrm{g}\left(\mathsf{\sigma }{\left(\mathrm{s}\right)}^2·\mathrm{P}\left(\mathrm{m}\mathrm{W}\right)\right)$, ** Measured at supply voltage 0.6 V.

compares the performance of the proposed digital phase-locked loop (DPLL) with existing ring oscillator-based PLLs, highlighting the advantages of the phase-domain DPLL architecture chosen for this design. The proposed DPLL is designed to support fractional-N operation, which provides finer frequency resolution and enables greater flexibility in frequency synthesis. A key differentiator of this work compared with other existing solutions is the novel calibration mechanism implemented in the calibrated DI-TDC. This calibration ensures robust performance against process, voltage, and temperature (PVT) variations, a common challenge in PLL design that can significantly affect the stability and accuracy of the output frequency. The proposed DPLL operates with a reference clock (Fref) of 50 MHz, providing a stable foundation for frequency synthesis. The frequency range of operation spans from 0.475 GHz to 1.1 GHz, covering a relatively wide range of 625 MHz. This wide operational range enhances the versatility of the DPLL, enabling it to be used in various applications that require different frequency bands. Power efficiency is another standout feature of this DPLL. At its maximum operating frequency of 1.1 GHz, the DPLL consumes only 0.93 mW of power. When expressed as power efficiency in mW/GHz, this DPLL demonstrates superior performance compared to other designs. Such high power efficiency is critical in IoT applications, where low power consumption is a key requirement due to the limited energy resources typically available.

The proposed DPLL outperforms existing ring oscillator-based PLLs by offering a combination of fractional-N capability, PVT compensation, a wide operational frequency range, and exceptional power efficiency. These features make it an ideal candidate for various applications, particularly in the IoT domain, where reliability, flexibility, and low power are paramount.

5. Conclusions

Figure 10 shows the photograph and layout of the implemented chip die. The photograph was taken during the chip-on-board (COB) work. The PLL was fabricated using a 28-nm CMOS process through MPW (multi-project wafer) in an active area of only 0.019 mm². This area excludes the size of IO pads and the bypass capacitor for VDD and VSS power stabilization, external to the core. All the blocks were synthesized from RTL-level behavioral descriptions, except for the DCO and the calibrated reference delay chain.

In this study, we present a novel calibration system for digital phase-locked loops, specifically designed to overcome the challenges associated with time-to-digital converter gain calibration. The proposed system effectively addresses the limitations of existing dual-interpolated TDCs, which typically suffer from performance degradation due to process, voltage, and temperature variations. By ensuring consistent TDC resolution aligned with the DCO period, our system significantly mitigates the impact of PVT variations, leading to improved overall stability and accuracy. One of the key advantages of our approach is the dual-mode operation of the calibrated dual-interpolated TDC, which functions in both foreground and background modes. This dual-mode capability allows the DPLL to maintain stable performance under varying environmental conditions, making it highly adaptable to real-world applications where conditions are not always ideal. Additionally, the background calibration mode ensures that the DPLL can dynamically adjust to any shifts in PVT without interrupting normal operation, further enhancing its robustness.

Implemented via a 28 nm CMOS process, our DPLL design is highly efficient in terms of both area and power consumption. Occupying only 0.019 mm², the design is extremely compact, making it suitable for integration into a wide range of digital communication systems. Despite its small size, the DPLL achieved excellent performance, with integrated phase noise (IPN) of −17.5 dBc when integrated from 10 kHz to 10 MHz at a PLL output of 570 MHz, and −20.5 dBc at 1.1 GHz. The wide frequency range of operation, spanning from 475 MHz to 1.1 GHz, combined with the low power consumption of just 930 µW under typical conditions with a 1.0 V supply, underscores the efficiency and effectiveness of our design. The results of this study demonstrate that the proposed calibration system not only can enhance the stability and performance of DPLLs but also offers significant improvements in power efficiency. The reduced sensitivity to PVT variations and the ability to maintain consistent performance across a wide frequency range make this DPLL design a robust and reliable solution for modern digital communication systems. These advancements pave the way for future applications where high performance, reliability, and efficiency are critical, particularly in the context of increasingly demanding digital and wireless communication environments.

In summary, this approach provides a significant leap forward in the design of DPLLs, addressing key challenges and setting a new standard for performance and reliability in the field. The proposed calibration system is a strong candidate for next-generation communication systems that require robust operation under varying conditions, low power consumption, and compact design.