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Electronics
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Advances in Low Powered Circuits Design and Their Application
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Advances in Low Powered Circuits Design and Their Application

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Power Electronics".

Deadline for manuscript submissions: closed (15 July 2024) | Viewed by 2678

Special Issue Editors

Dr. Anteneh Gebregiorgis

E-Mail Website
Guest Editor
Quantum and Computer Engineering Department, Delft University of Technology, 2628 CD Delft, The Netherlands
Interests: AI; edge computing; in-memory computing; neuromorphic computing; low-power design for IoT
Dr. Salahuddin Nur

E-Mail Website
Guest Editor
Quantum and Computer Engineering Department, Delft University of Technology, 2628 CD Delft, The Netherlands
Interests: scalable fabrication and on-chip integration processes for diamond-based quantum technologies; incorporation of photonic circuits with spins in diamond and integration of diamond color centers

Special Issue Information

Dear Colleagues,

Edge computing brings data processing, mainly AI, to edge devices where the data are harvested. This optimizes computation resources, reduces communication needs, and ensures the security and privacy requirements of applications deployed on edge devices such as wearables. However, edge devices have a stringent energy budget as they are mainly battery-powered, and a longer battery lifetime is of prime importance. Therefore, breakthroughs in device technologies, low-power circuit design, and architectural rethinking play key roles in developing energy-efficient devices for battery-operated platforms such as edge computing and IoT devices. Although advances in emerging non-volatile devices such as memristors are paving the way for energy-efficient computing, low-power circuits and architecture design require extensive scientific work to harness advances in technology.

This Special Issue aims to explore the advances in low-power circuit design for both traditional CMOS technology and emerging non-volatile memory technologies and their applications, ranging from IoT and edge computing to data and computation-intensive high-performance computing platforms.

Authors are invited to submit manuscripts to this Special Issue on Advances in Low-Powered Circuits Design and Their Applications. Relevant topics of interest to this Special Issue include (but are not limited to) the following:

  • Low-power circuit design;
  • Approximate and stochastic computing for low-power design;
  • Low-power circuit design using emerging memory devices;
  • Low-power computing-in-memory (CIM) circuits and architectures;
  • New designs for computing-in-memory paradigm;
  • Application of low-power design;
  • Applications of computing-in-memory.

Dr. Anteneh Gebregiorgis
Dr. Salahuddin Nur
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • low-power design
  • computation-in-memory
  • near threshold computing (NTC)
  • approximate computing
  • DVFS

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Published Papers (3 papers)

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Research

12 pages, 5383 KiB  
Article
A Fully Synthesizable Fractional-N Digital Phase-Locked Loop with a Calibrated Dual-Referenced Interpolating Time-to-Digital Converter to Compensate for Process–Voltage–Temperature Variations
by Seojin Kim, Youngsik Kim, Hyunwoo Son and Shinwoong Kim
Electronics 2024, 13(18), 3598; https://doi.org/10.3390/electronics13183598 - 10 Sep 2024
Viewed by 272
Abstract
This paper presents advancements in the performance of digital phase-locked loop (DPLL)s, with a special focus on addressing the issue of required gain calibration in the time-to-digital converter (TDC) within phase-domain DPLL structures. Phase-domain DPLLs are preferred for their simplicity in implementation and [...] Read more.
This paper presents advancements in the performance of digital phase-locked loop (DPLL)s, with a special focus on addressing the issue of required gain calibration in the time-to-digital converter (TDC) within phase-domain DPLL structures. Phase-domain DPLLs are preferred for their simplicity in implementation and for eliminating the delta–sigma modulator (DSM) noise inherent in conventional fractional-N designs. However, this advantage is countered by the critical need to calibrate the gain of the TDC. The previously proposed dual-interpolated TDC(DI-TDC) was proposed as a solution to this problem, but strong spurs were still generated due to the TDC resolution, which easily became non-uniform due to PVT variation, degrading performance. To overcome these problems, this work proposes a DPLL with a new calibration system that ensures consistent TDC resolution matching the period of the digitally controlled oscillator (DCO) and operating in both the foreground and background, thereby maintaining consistent performance despite PVT variations. This study proposes a DPLL using a calibrated dual-interpolated TDC that effectively compensates for PVT variations and improves the stability and performance of the DPLL. The PLL was fabricated in a 28-nm CMOS process with an active area of only 0.019 mm2, achieving an integrated phase noise (IPN) performance of −17.5 dBc, integrated from 10 kHz to 10 MHz at a PLL output of 570 MHz and −20.5 dBc at 1.1 GHz. This PLL operates within an output frequency range of 475 MHz to 1.1 GHz. Under typical operating conditions, it consumes only 930 µW with a 1.0 V supply. Full article
(This article belongs to the Special Issue Advances in Low Powered Circuits Design and Their Application)
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17 pages, 2770 KiB  
Article
Design of a High-Speed, Low-Power PTL-CMOS Hybrid Multiplier Using Critical-Path Evaluation Model
by Yihe Yu, Wanyuan Pan, Chengcheng Tang, Ningyuan Yin and Zhiyi Yu
Electronics 2024, 13(7), 1284; https://doi.org/10.3390/electronics13071284 - 29 Mar 2024
Viewed by 787
Abstract
The multiplier is the fundamental component of many computing modules. As the most important component of a multiplier, the full adder (FA) also has a significant impact on the overall performance. Full adders based on pass transistor logic (PTL) have been a very [...] Read more.
The multiplier is the fundamental component of many computing modules. As the most important component of a multiplier, the full adder (FA) also has a significant impact on the overall performance. Full adders based on pass transistor logic (PTL) have been a very popular research field in recent years, but the uneven delay makes it difficult to analyze the critical path of multipliers based on PTL full adders. In this paper, we propose a model to evaluate the critical path of the carry save array (CSA) multiplier that could reduce the size of the simulation input set from 4 G to 93 K to finally obtain the maximum delay of the multiplier. We propose a novel low-power, high-speed CSA multiplier based on both PTL full adders and CMOS full adders, using our critical-path evaluation model. The proposed work is implemented in the 28 nm process. We use the model to reduce the worst-case delay by 14.5%. The proposed multiplier improved the power delay product by 9.4% over the conventional full CMOS multiplier. Full article
(This article belongs to the Special Issue Advances in Low Powered Circuits Design and Their Application)
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13 pages, 631 KiB  
Article
An Energy Consumption Model for SRAM-Based In-Memory-Computing Architectures
by Berke Akgül and Tufan Coşkun Karalar
Electronics 2024, 13(6), 1121; https://doi.org/10.3390/electronics13061121 - 19 Mar 2024
Viewed by 1142
Abstract
In this paper, a mathematical model for obtaining energy consumption of IMC architectures is constructed. This model provides energy estimation based on the distribution of a specific dataset. In addition, the estimation reduces the required simulation time to create an energy consumption model [...] Read more.
In this paper, a mathematical model for obtaining energy consumption of IMC architectures is constructed. This model provides energy estimation based on the distribution of a specific dataset. In addition, the estimation reduces the required simulation time to create an energy consumption model of SRAM-based IMC architectures. To validate our model with realistic data, the energy consumption of IMC is compared by using NeuroSim V3.0 for the CIFAR-10 and MNIST-like datasets. Furthermore, an application is created with our model to select highest performing quantization mapping based upon the parameters of energy consumption and accuracy. Full article
(This article belongs to the Special Issue Advances in Low Powered Circuits Design and Their Application)
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