A 78 dB 0.417 mW Second-Order NS SAR ADC with Dynamic Amplifier-Assisted Integrator

Abstract

The noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) is an innovative hybrid structure that offers performance advantages. The NS-SAR ADC leverages the SAR ADC as its foundation and combines oversampling technology and noise-shaping technology found in Sigma-Delta ADC. This integration effectively combines the strengths of both structures and enhances overall performance. The ADC features a simple circuit structure, compact chip area, and high energy efficiency, which has positioned it as a prominent research area. In this paper, leveraging the TSMC 65 nm GP process, the NS-SAR ADC is designed with a power supply voltage of 1 V. This design adopts an 8-bit differential capacitor structure, operates at a sampling frequency of 16 MS/s, and achieves an oversampling rate of 16 times the desired performance indicators. Through extensive circuit post simulation verification, the SNR obtained reaches 78 dB, providing an effective bit resolution of 12.7 bits. The core chip area of the ADC measures 366 × 333 μm², while the power consumption is impressively low at 417 μW and FoMs is 168 dB.

1. Introduction

The NS-SAR ADC offers several advantages such as a simple structure, small area, low power consumption, and high precision. However, different noise-shaping SAR ADC structures employ varying methods of integrating residual voltage and achieving noise shaping, each with their own advantages and disadvantages. For instance, the passive integrator structure relies solely on a switched capacitor circuit to achieve noise shaping. This structure benefits from its simplicity and good PVT characteristics. However, during the integration process, constant charge redistribution is necessary, resulting in significant signal attenuation and a poor noise-shaping effect [1,2,3,4]. On the other hand, the noise-shaping structure based on a closed-loop amplifier effectively addresses the problem of signal attenuation. Before residual voltage and charge redistribution, the amplifier boosts a specific multiple of the signal and transfers it to the sampling capacitance, thereby minimizing signal attenuation during the integration process [5,6,7,8]. However, this closed-loop amplifier consumes a considerable amount of power and presents relative difficulties in design. To obtain a better noise-shaping effect, higher requirements are imposed on power consumption and circuit design complexity. In order to reduce power consumption, the noise-shaping circuit based on a dynamic amplifier was developed. The dynamic amplifier solely activates when a signal is present, eliminating static power consumption and greatly reducing the overall circuit’s power consumption.

The dynamic amplifier plays a crucial role in amplifying the residual voltage and redistributing charge among the three capacitors in order to achieve second-order noise shaping. However, the noise transfer function (NTF) of the EF noise-shaping structure deviates from the ideal second order (1 − z⁻¹)². This discrepancy is caused by signal attenuation originating from capacitive charge redistribution, which subsequently leads to increased noise in the comparator, dynamic amplifier, and FIR filter circuits. The challenge lies in designing the circuit due to the excessively high gain of the dynamic amplifier. Moreover, the high-gain dynamic amplifier proves to be highly sensitive to variations in process, voltage, and temperature (PVT) conditions. This instability of the zero pole in the NTF severely impacts the noise-shaping effect of the system. To address this issue, an additional dynamic amplifier gain calibration circuit needs to be incorporated [9,10]. However, this addition increases the overall circuit’s power consumption and subsequently lowers its energy efficiency and figures of merit (FoMs).

This paper introduces a novel second-order noise-shaping structure called sampling error feedback (SEF). In comparison to the traditional EF structure, the SEF structure incorporates a new dynamic amplifier, denoted as G₂. However, the gain of the dynamic amplifier is significantly reduced, and the required number of capacitors in the integrator is reduced as well. As a result, the overall circuit experiences a substantial reduction in power consumption. Additionally, the issue of high gain dynamic amplifier’s sensitivity to changes in PVT conditions is alleviated, leading to a reduction in circuit design complexity.

This paper is organized as follows. In Section 2, the SEF NS-SAR ADC is proposed with circuit architecture and system dynamic model. Section 3 discusses the circuit implementation of the proposed ADC. In Section 4, the circuit performance is simulated and the post simulation results are shown. Finally, the experimental results are discussed in Section 5.

2. System Overview

2.1. The Architecture of the Proposed ADC

Figure 1 showcases the block diagram and schematic diagram of a novel second-order error feedback noise-shaping SAR ADC, proposed in this paper. This NS-SAR ADC is primarily composed of four key components. The first component is the CDAC circuit, responsible for implementing successive approximation of voltage. The second component consists of the second-order noise-shaping branch, where the residual voltage from each conversion cycle undergoes high-pass filtering before being outputted to the CDAC. The third component is the comparator circuit, which compares the voltage of the CDAC’s top plate and generates the digital code output for the analog-to-digital converter. The fourth component is the SAR logic circuit, tasked with generating the necessary control signals for the entire ADC system. It is noteworthy that C_res1, C_res2, and C_delay are equal in capacitance value.

The proposed second-order noise-shaping sequence is depicted in Figure 2. During the sampling phase Φ_S, the input signal is transmitted to the CDAC top plate via the sampling switch. After eight cycles of operation by the comparator, the residual voltage V_res is present on the CDAC top plate. Prior to the next sampling phase, the Φ_RST signal resets the potential of C_delay. Upon activation of Φ_D2, charge is shared between C_res2 and C_delay. Upon deactivation of Φ_D2, Φ_AMP is activated, causing the dynamic amplifier G₁ to amplify the V_res voltage on the CDAC top plate and transmit it to both C_res1 and C_res2. Finally, Φ_D3 is activated to facilitate charge sharing between C_res2 and C_delay. After completing these operations, when the next sampling phase Φ_S cycle commences, the dynamic amplifier G₂ amplifies the voltage stored on C_delay and feeds it back to the C_x, achieving second-order noise shaping.

2.2. System Hybrid Model

During the N − 1 cycle of the ADC sampling process, once the comparator completes its normal operations, the Φ_RST switch is closed. This action clears and resets the residual voltage stored on the C_delay capacitor from the N − 2 cycle, bringing it back to 0. At this moment, the voltage on the C_res1 capacitor in the FIR filter circuit is V_D1(N − 1). The voltage on the C_res2 capacitor is V_res2(N − 1) = V_res(N − 2), and the voltage on the C_delay capacitor is V_D2 = 0. Subsequently, the Φ_D2 switch is closed, causing C_res2 to redistribute the voltage stored on its upper plate to the C_delay capacitor:

$$V_{D2}\left(N\right)=0.5V_{res2}\left(N-1\right)=-0.5G_1{V}_{res}\left(N-2\right)$$

(1)

After closing the Φ_AMP switch, the dynamic amplifier initiates its operation, resulting in the following voltages on the C_res1 and C_res2 capacitors:

$$V_{D1}\left(N\right)=-V_{res2}\left(N\right)=G_1{V}_{res}\left(N-1\right)$$

(2)

After closing the Φ_D3 switch, the voltages on the C_res1 and C_delay capacitors are

$$V_{EF}\left(N\right)=V_{D1}\left(N\right)=V_{D2}\left(N\right)=\frac{G_1{V}_{res}\left(N-1\right)}{2}-\frac{G_1{V}_{res}\left(N-2\right)}{4}$$

(3)

Then, the dynamic amplifier G₂ begins operation, connecting the top plate of the C_x to the amplified residual voltage. Finally, upon closing the Φ_S switch, the upper plate of the CDAC initiates sampling. Following the principle of charge conservation, this process can be derived from the equation:

$$Q_{SIG}\left(N\right)=C_{DAC}\left\{V_{SIG}\left(N\right)-\left[\frac{G_2{G}_1{V}_{res}\left(N-1\right)}{2}-\frac{G_2{G}_1{V}_{res}\left(N-2\right)}{4}\right]\right\}$$

(4)

$$Q_{SIG}\left(N\right)=C_{DAC}\left[V_{DAC}\left(N\right)-V_{CM}\right]$$

(5)

$$V_{DAC}\left(N\right)=V_{SIG}\left(N\right)-\left[\frac{G_2{G}_1{V}_{res}\left(N-1\right)}{2}-\frac{G_2{G}_1{V}_{res}\left(N-2\right)}{4}\right]+V_{CM}$$

(6)

When |G₁| = |G₂| = 2,

$$V_{DAC}\left(N\right)=V_{SIG}\left(N\right)-2V_{res}\left(N-1\right)+V_{res}\left(N-2\right)+V_{CM}$$

(7)

As the ADC operates as a differential circuit, the common-mode voltage (V_CM) can be eliminated. After the introduction of quantization noise during normal ADC operation, its expression in the z-domain is given by

$$V_{DAC}\left(z\right)=V_{SIG}\left(z\right)+Q\left(1-2z^{-1}+z^{-2}\right)$$

(8)

But Q(N) can be represented by V_res(N), so when we convert the expression into the z domain, we are left with the expression Q. Based on Formula (8), the SEF structure exhibits a perfect second-order noise-shaping function of (1 − z⁻¹)², resulting in a stronger noise-shaping effect compared to the traditional EF structure. The main distinction between the SEF and EF noise-shaping structures lies in the different methods of feeding back the integrated residual voltage to the input.

The EF structure achieves this by directly connecting the integrated capacitor in the FIR filter to the capacitor CDAC, utilizing charge redistribution. In contrast, the SEF structure feeds back the residual signal to the lower plate of the CDAC capacitor during sampling while connecting the upper plate of the CDAC to the common-mode potential. Subsequently, the residual signal from the lower plate is transmitted to the upper plate and combined with the input signal. This eliminates the problem of signal attenuation for both the input and residual voltage, which is often observed in the EF structure. Consequently, it avoids the issue of increased noise within components like the comparator, dynamic amplifier, and FIR filter.

While the SEF structure employs two dynamic amplifiers, their gains are only 1/15 of those used in the EF structure. This significant reduction in gain greatly simplifies circuit design, reduces the sensitivity of high-gain dynamic amplifiers to PVT changes, eliminates the need for additional gain calibration circuits, lessens the workload, reduces overall power consumption, and enhances FoMs.

In order to determine the amplifier gain, the noise of the circuit system is analyzed. The expression of the equivalent input noise power $n_{tot}^2$ of ADC can be written out according to the flow diagram when |G₁| = |G₂| = 2.

$$n_{tot}^2=n_{DAC}^2+n_{res1,AMP}^2+\frac{1}{4}{n}_{res2,AMP}^2+\frac{1}{4}{n}_{delay,RST}^2+n_{delay,D2}^2+4n_{delay,D3}^2$$

(9)

$$n_{tot}^2=\frac{kT}{C_{DAC}}+\frac{8kT}{C_{DAC}}+\frac{2kT}{C_{DAC}}+\frac{2kT}{C_{DAC}}+\frac{4kT}{C_{DAC}}+\frac{16kT}{C_{DAC}}=\frac{33kT}{C_{DAC}}$$

(10)

where $n_{res1,AMP}^2$ is the noise power generated by the switch Φ_AMP on the capacitor C_res1 when the residual voltage is amplified and collected; the $n_{DAC}^2$ represents the thermal noise power introduced when the sampling switch is turned off; $n_{res2,AMP}^2$ is the noise power generated by the switch Φ_AMP on the capacitor C_res2 when the residual voltage is amplified and collected; $n_{delay,RST}^2$ is the noise power generated when the capacitor C_delay is reset by the switch Φ_RST; $n_{delay,D2}^2$ is the noise power generated by the switch Φ_D2 on the capacitor C_delay when the capacitor C_delay is reassigned with the capacitor C_res2; $n_{delay,D3}^2$ is the noise power generated by the switch Φ_D3 on the capacitor C_delay when the capacitor C_delay redistributes the charge with the capacitor C_res1.

When |G₁| = 8 and |G₂| = 0.5, the ADC equivalent input noise power expression becomes

$$n_{tot}^2=n_{DAC}^2+\frac{1}{16}{n}_{res1,AMP}^2+\frac{1}{64}{n}_{res2,AMP}^2+\frac{1}{64}{n}_{delay,RST}^2+\frac{1}{16}{n}_{delay,D2}^2+\frac{1}{4}{n}_{delay,D3}^2$$

(11)

$$n_{tot}^2=\frac{kT}{C_{DAC}}+\frac{kT}{{2C}_{DAC}}+\frac{kT}{{8C}_{DAC}}+\frac{kT}{{8C}_{DAC}}+\frac{kT}{{4C}_{DAC}}+\frac{kT}{C_{DAC}}=\frac{3kT}{C_{DAC}}$$

(12)

It can be seen that when |G₁| = 8 and |G₂| = 0.5, the equivalent input noise power of ADC is much smaller than that when |G₁| = |G₂| = 2. With the same structure, the kT/C in the band is reduced by as much as a factor of ten, the integrated capacitance size does not increase, and the power consumption is not increased, which optimizes the energy efficiency. In order to further suppress the switching thermal noise in the second-order noise-shaping branch and improve accuracy and FoMs, the dynamic amplifier gains are finally determined as G₁ = 8 and G₂ = 0.5 while considering the system’s noise level.

3. Circuit Implementation

3.1. The Dynamic Amplifier

Figure 3 illustrates the circuit diagram of the dynamic amplifier designed in this paper, based on the differential flip voltage follower (DFVF). This architecture represents an incomplete dynamic amplifier, where the switching transistor M₁₃ enables dynamic operation and the gain is determined by the amplification time. When compared to a dynamic amplifier based on common mode detection, the transistors M₅, M₉ (M₆, M₁₀), M₇, and M₁₁ (M₈, M₁₂) in the DFVF serve as current sources between each other. They also play a clamping role on the potential of the intermediate point, ensuring that the tubes M₅, M₆, M₇, and M₈ maintain a constant V_GS. This design feature guarantees high linearity even under large input swings. For the input stage of the amplifier, a Class A-B structure is employed to increase the transconductance of the amplifier and reduce amplifier noise.

In Figure 3, the working process of the circuit can be divided into two stages: the reset stage and the amplification stage. During the reset stage, characterized by a low Φ_RA signal and high Φ₁ and Φ₂ signals, the load capacitor is reset to V_CM. The amplification stage commences when the Φ₂ signal is low, and the Φ₁ and Φ_RA signals are high. In this stage, the two load capacitors begin to charge and discharge based on the input voltages, V_in and V_ip. The rate of charge and discharge is dependent on these input voltages. Once the output voltage reaches the desired gain, the Φ₁ signal switch is turned off, concluding the amplification process. The output current of the aforementioned circuit structure can be expressed as:

$$I_{op}=I_1-I_3=k_p{\left(-V_{id}-V_{TP}\right)}^2-k_n{\left(V_{id}-V_{TN}\right)}^2$$

(13)

$$I_{on}=I_2-I_4=k_p{\left(V_{id}-V_{TP}\right)}^2-k_n{\left(-V_{id}-V_{TN}\right)}^2$$

(14)

V_id represents the voltage difference between V_in and V_ip, k denotes the parameter μC_oxW/2L (with μ being the mobility of the channel, Cox representing the oxide capacitance per unit area, W referring to the width of the transistor, and L representing its length). Additionally, V_TP represents the overdrive voltage of the M₅ transistor, and V_TN signifies the overdrive voltage of the M₇ transistor. Under the assumption that there is no mismatch between each pair of differential transistors, the differential output current can be calculated as follows:

$$I_{id}=I_{op}-I_{on}=4k_p{V}_{id}{V}_{TP}+4k_n{V}_{id}{V}_{TN}=4(k_p{V}_{TP}+k_n{V}_{TN})V_{id}$$

(15)

Gain can be expressed as

$$A_V=\frac{2(k_p{V}_{TP}+k_n{V}_{TN})t_{amp}}{C_S}$$

(16)

In the equation, t_amp represents the effective amplification time, and Cs denotes the load capacitance. In our design, there is negligible difference between k_p and k_n. As a result, for a given current, the dynamic amplifier offers nearly twice the effective transconductance while reducing the input equivalent noise. Referring to Formula (15), the gain error of the amplifier primarily originates from variations in V_TP and V_TN within the input range. To minimize the gain error, adjustments can be made by appropriately increasing the current in the M₅ and M₇ branches, and reducing the current in the M₁ and M₃ branches. This helps mitigate variations in V_TP and V_TN within the input range.

3.2. Nonlinearity Caused by Mismatch Error

This design uses a redistributive SAR ADC, which has the advantages of low power consumption and small area compared with other types of capacitor arrays. However, with the improvement in ADC accuracy, the area brought about by the exponential increases, and the difficulty of the circuit design and production costs are also greatly increased. With the increase in the number of capacitors, it means that the nonlinear problem caused by the mismatch error of capacitors cannot be ignored on the circuit, which will affect the quantization process of ADC, thus reducing the accuracy of ADC. The causes of mismatch in CDAC are mainly divided into two categories. The first is the chip process manufacturing, because it is impossible to ensure that the etching rate of each place of the capacitor is exactly the same. There will be deviations in the same layer of media, resulting in random errors between the length and width area of the capacitor and the size in the design, and eventually the capacitor value mismatch. Secondly, in the layout design stage, the top plate and bottom plate of the capacitor need to be connected to the control switch and the comparator input end. In the process of wiring, side-by-side wiring between metals is unavoidable, or the layout and wiring between adjacent metal layers overlap, resulting in a large number of parasitic capacitors between metal lines, which affects the accuracy of the ADC. In order to define the nonlinear mismatch error of the CDAC, the highest capacitance in the CDAC array can be used as a reference to define the mismatch error of the remaining low capacitance. Assuming that the capacitance of the most significant bit (MSB) is C_N−1 = 2^N−1C, where C represents the unit capacitance value, the capacitance size of the remaining low least significant bit (LSB) can be expressed as:

$$C_i=2^{i}C+e_i=\frac{2_i}{2^{N-1}}{C}_{N-1}+e_i ,i\in [1,N-2]$$

(17)

In Formula (17), e_i is defined to represent the mismatch of the unit capacitance C_i when the MSB capacitance value C_N−1 is used as the reference. Therefore, it can be considered that the MSB is not mismatched, and the value of its analog quantity converted to digital quantity is equal:

$${DAC}_{MSB}=D_{MSB}=\frac{D_{N-1}}{2}$$

(18)

Among them, DAC_MSB represents the analog amount of MSB, and D_MSB represents the digital amount of MSB. According to Formula (17), LSB bits contain mismatch errors, and the relationship between analog and digital quantities is:

$${DAC}_{LSB}=D_{LSB}+E$$

(19)

where the weighted sum of analog quantities of all LSB bits except MSB is defined as DAC_LSB, and the weighted sum of digital quantities of all LSB bits is defined as D_LSB. E represents the weighted sum of mismatch errors of LSB bits, and its definition can be expressed as:

$${DAC}_{LSB}=\frac{{\sum }_{i=0}^{N-2}{D}_i{C}_i}{2C_{N-1}}$$

(20)

$$D_{LSB}=\sum _{i=0}^{N-2}{D}_i{2}^{i-N}$$

(21)

$$E=\sum _{i=0}^{N-2}{D}_i{e}_i$$

(22)

D_i is the digital control code corresponding to C_i. In the analog domain, after the sampling phase is over and the comparator starts working, the CDAC array switches from the MSB to the LSB successively, subtracting the analog voltage corresponding to the capacitance ratio from the analog input signal V_in successively, and finally pulling the V_in to nearly zero voltage after multiple comparisons are completed. The conversion process can be expressed as follows:

$$V_{in}-{DAC}_{MSB}-{DAC}_{LSB}=0$$

(23)

In the digital domain, the final digital output can be obtained by summing the D_MSB and D_LSB by weight:

$$D_{out}=D_{MSB}+D_{LSB}$$

(24)

By substituting the Formulas (20)–(22) into (24), we obtain:

$$D_{out}=V_{in}-E$$

(25)

As can be seen from Formula (25), the mismatch error E of the CDAC appears directly in the digital output D_out. As shown in Formula (22), since the mismatch error E is the result of the digital output code modulating the mismatch of each capacitor, it is not a random noise, but a semaphore related to the input signal. In the time domain, E appears as a waveform related to the input signal; In the frequency domain, E appears as a higher harmonic of the input signal. Because the capacitor nonlinearity of CDAC mainly appears in the layout design and the subsequent chip production process, the influence of capacitor nonlinearity should be fully considered in the design. Therefore, the selection of unit capacitance needs to consider kT/C noise, power consumption, process production, area cost, and other factors. The larger the capacitance area, the smaller the nonlinear impact caused by mismatch, but the overall power consumption and cost are also relatively increased, so it is necessary to choose the appropriate unit capacitance size.

4. Post Simulation and Results

The novel second-order sampling error feedback noise-shaping SAR ADC proposed in this paper has been successfully implemented using TSMC 65 nm technology. The chip design is carried out in the post-simulation stage. It occupies a compact area of 0.122 mm², as illustrated in Figure 4. After carrying out rigorous post simulations, the total power consumption of the ADC is determined to be 417 μW. The power distribution among different components is as follows: CDAC accounts for 28%, second-order noise-shaping branch for 31%, SAR logic for 32%, and comparator for 9%. Figure 5 illustrates a pie chart depicting the power distribution of the entire noise-shaping ADC. Figure 6 illustrates the impact of capacitor mismatch on second-order noise-shaping effects. The peak represents the input signal energy, and the rest represents the noise energy. Under the interference of mismatch, the signal energy is unchanged and the noise energy is increased. It is evident from the figure that the mismatch in the capacitor array significantly affects the accuracy of the ADC. The main factor restricting the attainment of high precision in the ADC is device mismatch. In the case of a typical SAR ADC, the mismatch error of the DAC restricts the effective number of bits to approximately 12 bits.

The distribution of unit capacitance in the actual manufacturing process is a normal fraction of a certain mismatch error and increases as the unit capacitance value decreases. When the capacitance mismatch error is added, a large number of odd harmonics appear in the spectrogram along with the elevation of the noise base, which seriously affects the conversion accuracy.

As a result of the utilization of an incomplete dynamic amplifier in the circuit, the amplifier gain will exhibit slight variation across different input voltages. Figure 7 demonstrates that the amplifier gain will range from 7.2 to 8.0 when the input range is -0.04 V to 0.04 V. As can be seen in Figure 7, the gain change in the dynamic amplifier has a great influence on the SNDR of the ADC, and the SNDR is reduced by 10 dB when the error reaches 0.04 V. Figure 8 illustrates the simulated spectrum with a conversion rate of 16 MS/s and an input frequency of 13 kHz. The simulated signal-to-noise-and-distortion ratio (SNDR) is 78 dB when the oversampling rate (OSR) is 16.

As the input signal frequency, fin, is varied from 50 kHz to 450 kHz, the post-simulation SNDR ranges between 67 dB and 78 dB, as depicted in Figure 9. This second-order noise-shaping SAR ADC, utilizing sampling error feedback, achieves an impressive FoMs of 168 dB. According to the oversampling principle, doubling the OSR will increase the SNDR by 3 dB as in Figure 10, so oversampling can effectively improve the accuracy of the ADC. However, in order to maintain the signal bandwidth, doubling the oversampling rate requires doubling the sampling rate, resulting in doubling the power consumption, so simply using oversampling to improve ADC accuracy is not a highly energy efficient solution.

The performance parameters of this study, compared to other noise-shaping approaches, are detailed in

Table 1. Comparison with similar ADCs.

Paper	ISSCC 2019 [8]	JSSC 2019 [11]	TCAS-II 2020 [12]	JSSC 2021 [13]	TCAS-II 2023 [14]	This Work
Process (nm)	40	40	65	40	28	65
Supply (V)	1	1.1	1.2	1.1	1.1	1
Area (mm2)	0.061	0.04	0.483	0.125	0.0387	0.122
Resolution (Bit)	10	9	8	10	8	8
NS order	4	2	2	2	1	2
Fs (MHz)	400	8.4	100	400	600	16
OSR	4	16	16	6	4	16
Bandwidth (MHz)	50	0.262	3.125	33.3	75	0.5
SNDR (dB)	70.4	78.4	77	73.7	65.37	78
Power (mW)	13	0.143	1.24	8.5	4.015	0.417
FoMs	166.3	171	171	169.6	168.1	168

FoMs = P/$f_B$/2^ENOB (P: power, $f_B$: bandwidth).

. Notably, the chip area in this research falls within the medium range, largely influenced by the selection of the 65 nm process, which places it behind several alternative designs. However, in terms of SNDR, this work achieves a superior level compared to others, and its ability to achieve a similar SNDR at a lower resolution than the JSSC 2019 in Table 1 [11] positions it at the forefront among various structures. When considering power consumption, 0.417 mW of this work rating is only surpassed by the 0.143 mW of [11], significantly outperforming several other structured NS ADCs in this aspect. Furthermore, a higher FoMs value indicates improved energy efficiency for the corresponding ADC. As indicated in the table, the energy efficiency of this study falls within the medium range, as the adoption of a dynamic amplifier structure for noise shaping in this work results in increased energy consumption.

5. Discussion

With the rapid development of the Internet of Things, wireless communication, artificial intelligence, and other fields, there has been an increased demand for the collection and processing of analog information. As a hybrid analog-to-digital converter, the noise-shaping SAR ADC can efficiently convert analog signals to digital signals with low power consumption and high precision. In this study, a new high-performance ADC architecture has been designed, allowing the noise-shaping SAR ADC circuit to achieve a higher signal-to-noise distortion ratio, lower power consumption, and higher energy efficiency. This enriches relevant research achievements and provides strong support for the aforementioned applications.

In this paper, a high-precision analog-to-digital converter based on dynamic amplifier is designed. This paper presents an 8-bit 16 MS/s, sampling error feedback NS SAR ADC in a 65 nm GP CMOS technology. In the case of 1 V supply voltage, 16 times oversampling rate, the final SNR of 78 dB and effective bits of 12.7 bits are achieved. The ADC core chip area is 0.122 mm², its power consumption is 417 μW, and it achieves a FoMs of 168 dB.

Despite completing the circuit design and layout of the high-precision analog-to-digital converter based on dynamic amplifier in this research, there are still some shortcomings that need to be discussed in future research. These mainly include the following: 1. The gain of the dynamic amplifier is greatly affected by PVT and requires external calibration. 2. Capacitor mismatch limits the improvement in accuracy and requires shaping. This can be solved by adding the structure of mismatch shaping in the future.