A Critical Analysis and Comparison of the Effect of Source Inductance on 3- and 4-Lead SuperJunction MOSFETs Turn-Off

Abstract

This paper critically compares the turn-off performance of two package solutions, 3-lead (3L) vs. 4-lead (4L), in SuperJunction MOSFETs. It is commonly assumed that the better performance (lower switching losses) of the 4L MOSFET is obtained thanks to the decoupling of the power and driving loops. On the contrary, in this work, the experimental results, circuit models and Kirchhoff laws show that the turn-off improvement (lower turn-off losses) obtained by adopting the Kelvin source is due to the lower inductance of the driver loop of the 4L MOSFET, instead of the decoupling between the driver and power loops. In detail, an inductor is added to the gate path of the 4L MOSFET to obtain a total inductance in the driver loop equal to the 3L counterpart. The experimental results show that the 4L MOSFET presents the same drain current slew rate under this condition, although the driver and power loops are still decoupled.

1. Introduction

In many applications, the market pushes towards a concurrent reduction in the bill of materials and an increment in power density [1,2]. The first target is achieved by adopting mature technologies with a good tradeoff between investment and performance [3]. The latter target can be achieved by operating the power converter at a high switching frequency to reduce the size of the passive components, thus also benefiting from cost reduction [4]. However, an increase in switching frequency inflicts increased switching losses that can considerably compromise power efficiency [5]. Furthermore, high-density high-frequency power converters lead to challenging thermal issue management [6]. This task becomes more difficult when the power converter is frequently operated at a high/full load [7]. The thermal operating conditions of the power devices critically affect their lifetime [8].

Taking into account all the aforementioned aspects, a cost-effective solution can be reached using power devices capable of ensuring good efficiency when operated at high frequency and high load. SuperJunction MOSFETs enhanced by the introduction of an additional source pin, called Kelvin source, are the best compromise solution [9]. The Kelvin pin enables the decoupling of the driving and power loops. At high loads, these devices presenting 4-lead (4L MOSFETs) strongly reduce the switching losses and, consequently, the device and converter operating temperature in comparison with 3-lead MOSFETs [10]. The advantages obtained by using the Kelvin source have been widely studied so far. A package design with Kelvin drain-to-source connection is adopted to minimize the blanking time [11]. The effect of source inductance in 3L and 4L MOSFETs is investigated via theoretical analysis and spice simulations in [12]. The reasons behind common source inductance in power devices with Kelvin source are investigated in [13]. The evaluation of the reliability and ruggedness of 3L and 4L MOSFETs are evaluated in [14]. The work in [15] proposes a method to evaluate TO-247-3 and TO-247-4 MOSFETs in typical half-bridge circuits. The study reported in [16] enables the development of an analytical model to evaluate the turn-on switching losses of MOSFETs enhanced with the Kelvin source. The turn-on losses of 3L and 4L MOSFETs are also investigated in [17]. A design and evaluation method of the Kelvin source in multi-chip power module is proposed in [18]. The work in [19] analyzes the effect of the Kelvin source on the overall power losses of the MOSFETs as well as its benefits in terms of lower operation temperature.

However, it is necessary to fully understand the reasons behind this improvement to fully exploit the advantages of 4L MOSFETs. In this perspective, this paper investigates improvement mechanisms that involve a reduction in switching losses during turn-off. Firstly, a comparison of the switching losses is presented. After that, the switching waveforms are analyzed to properly model the devices during the interval in which the greatest part of the turn-off losses occurs. The key aspect is that during the interval where the drain current falls, which mainly coincides with those when the turn-off losses occur, there is no channel current (or it is present in a small initial subinterval). For this reason, the drain current does not depend on the gate–source voltage and, consequently, the increment in this voltage due to the source inductance does not have any effect on the drain current. This implies that the mechanism leading to lower turn-off losses in 4L is different from the common understanding of this phenomenon. An additional consequence is that the circuit model to be used for studying the turn-off must not contain the typical current source controlled by the gate–source voltage.

Then, the circuit model is analyzed and an approximate analytical expression of the current slew rate is obtained for both kinds of device packaging. The comparison of these equations highlights that the turn-off improvement obtained thanks to the higher current slew rate in 4L MOSFETs is due to the lower inductance of the driver loop in comparison with the power loop inductance. In other terms, the source inductance of the 3L MOSFET negatively affects its performance, but this is due to a mechanism that is different from the common understanding of this phenomenon.

Finally, this theoretical framework based on the circuit model and Kirchhoff laws is proven experimentally by placing an inductor in the gate path of the 4L MOSFET to equal the driver loop inductance of the 3L counterpart. The experimental results show that the 4L MOSFET does not obtain better performance under this condition, although the driver and power loops are still decoupled. As far as the authors know, so far, there has not been a complete framework based on simplified circuit equations and experimentation that highlights this fact. On the contrary, it is currently (erroneously) assumed in academia and industry that the better performance of 4L MOSFETs is obtained thanks to decoupling. This is true only when the turn-on is considered, as proven in [17].

2. Preliminary Comparison of the Experimental Turn-Off Losses

The aim of this section is first to recall some aspects related to the different turn-off losses in 3L and 4L MOSFETs for different combinations of gate resistance and load conditions, by analyzing their interaction. After that, the turn-off waveforms are critically analyzed to properly model the device. This circuit model is essential for the theoretical framework that combines it with Kirchhoff laws to properly analyze the reasons behind the lower turn-off switching losses in the 4L MOSFET.

A boost converter (Figure 1a) is selected for analyzing the turn-off behaviour of 3L and 4L MOSFETs because it is the simplest converter to perform the study in an actual application. Moreover, it avoids MOSFET body diode turn-on. In detail, when the MOSFET is turned off, the current is diverted into the diode of the converter. This choice enables us to analyze only the relationships among gate–source voltage, drain current and sources’ parasitic inductance. Finally, in a boost converter, it is very easy to tune the current to perform the analysis under different working conditions.

The device is a TO-247-packaged N-channel MOSFET produced by STMicroelectronics with a breakdown voltage of 650 V, on-state resistance of 37 mΩ and a maximum current of 58 A (part numbers: STW69N65M5, STW69N65M5-4L). The 4L MOSFET is identical to the 3L one, except for the presence of the additional source lead (Kelvin pin). A schematic of the converter with the embedded MOSFET is reported in Figure 1b. The MOSFET is modeled in the red box that highlights the parasitic R-L components of the terminals. The parasitic components R_K,P and L_K,P are present in the 4L MOSFET only.

The test vehicle is the boost converter reported in Figure 1 with the overall experimental setup and the related schematic.

The test equipment consists of the following components.

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AC source: Agilent AC/DC power supply 6813B (1750VA).

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Oscilloscope: 1 GHz Tektronix MS05140.

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Yokogawa power meter WT500 and WT310 to measure, respectively, the input and output power.

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Chroma DC Electronic Load Model 6314 to set the output current (active load).

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Tektronix TCP0030 current probe to measure MOSFET current.

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Tektronix passive voltage probe (1:10) to measure the gate–source voltage.

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LeCroy passive voltage probe P6139B (1:100) to measure the drain–source voltage.

Finally, an auxiliary power supply is used to supply the cooling fan. Figure 2 reports the additional turn-off switching losses due to the use of a 3L MOSFET instead of the same device enhanced by the Kelvin source, the 4L MOSFET, as a function of the converter load. The results are reported for different values of gate resistance (RG). For low load levels (<45%), it is interesting to note that the curves overlap, which means that the gate resistance has a negligible effect. Also, the load condition does not have any effect, as highlighted by the constant additional losses.

For a load level greater than 45%, the curves do not overlap anymore. Consequently, the additional losses depend on the gate resistance: they increase as the resistance increases. Considering that the gate resistance regulates the switching speed, which, in turn, affects the switching losses, the increment in the gate resistance slows the 3L MOSFET turn-off more than the 4L one. In this load range, the load itself also affects the additional energy losses, which increase as the load increases. Therefore, the load current also affects the turn-off switching speed. As mentioned above, it is necessary to properly model the device during the turn-off to derive a formulation based on circuit analysis to understand the effect of the gate resistance and load conditions on the switching speed of 3L and 4L MOSFETs.

Before focusing on this target, it is interesting to recall that it is well known that during 3L MOSFET turn-on, the source inductance imposes negative feedback on the gate–source voltage, reducing this voltage, and thus, slowing its rising. Considering that the gate–source voltage controls the channel current, it can be concluded that the source inductance causes a slower drain current increase and, consequently, a slower turn-on, which leads to increased turn-on losses [17].

Similar reasoning is adopted according to the common understanding of the effect of source inductance in 3L MOSFETs during turn-off. In particular, it is usually stated that source inductance imposes positive feedback on the gate–source voltage, increasing this falling voltage during turn-off. Considering that the gate–source voltage controls the channel current, it can be concluded that the source inductance causes a slower drain current decrease and, consequently, slower turn-off, thus leading to increased turn-off losses. Therefore, the 4L package is implemented to reach fast commutations that reduce switching losses by decoupling the driver and power loops.

In detail, this phenomenon is typically explained as follows: Turn-off occurs due to the gate–source reduction consequent to setting the driver voltage to 0. However, the drain current flows through the parasitic inductance L_S. The reducing current provokes a voltage across L_S that slows down the gate–source reduction. This phenomenon does not occur in 4L MOSFETs. Figure 3 shows the different impact of this voltage drop in 3L and 4L MOSFETs. In a 3L MOSFET (Figure 3a) the source inductance voltage belongs to both the power and driving loops. Consequently, the voltage drop across the source inductance has the same effect as a driver voltage greater than zero (green box). On the other hand, it has no effect on the gate–source voltage in 4L MOSFETs (Figure 3b). The stylized gate–source voltage trend in 3L and 4L MOSFETs during the turn-off is represented in Figure 3c. Analyzing the two waveforms, it is apparent that the 3L MOSFET gate–source voltage is late compared to the 4L one, and this delay grows (green arrows).

During commutation, the MOSFETs should enter the saturation region, where the drain current is almost proportional to the gate–source voltage. Therefore, slowing down the gate–source reduction implies slowing down the drain current reduction (i.e., lowering the current slew rate).

These intuitive considerations are usually adopted to describe the reasons for the fast turn-off of a 4L MOSFET in comparison to a 3L one. However, such an explanation presents an Achilles heel: it assumes that, for both MOSFETs, the current reduction occurs concurrently with the gate–source voltage reduction in the saturation region. In other words, it assumes that the drain current during the turn-off is a channel current proportional to the gate–source voltage. In the following (Figure 4 and Figure 5), it will be proven that this common interpretation is wrong because the current reduction does not occur when the MOSFETs operate in saturation; hence, the drain current is not a channel current. In detail, drain current reduction very often occurs when the MOSFET gate–source voltage is lower than the voltage threshold (Figure 4 and Figure 5); this invalidates the common explanation. Only in a few cases does the drain current reduction start before the gate–source voltage has reached the threshold, but, even in these cases, the common explanation is not valid. In fact, two crucial aspects make anyway the previous common explanation wrong:

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Looking at the interval where the drain current reduces, the subinterval where the gate–source voltage is lower than the threshold is the greatest one;

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The gate–source voltage is close to the threshold voltage when the current reduction starts.

Therefore, the feedback due to the source inductance observed during turn-on does not occur during turn-off because the gate–source voltage is below the threshold (the channel is closed when the current fall begins. Hence, the drain current is not a channel current, and consequently, the switching waveforms have to be investigated to better understand the effect of the fourth lead.

The switching waveforms are reported in Figure 4 for 3L and Figure 5 for 4L MOSFETs considering a low load (a and b), medium load (c and d) and full load (e and f) when the selected RG is, respectively, equal to 3.9 Ω (a,c,e) and 15 Ω (b,d,f).

In each figure, a horizontal dashed blue line representing the voltage threshold has been superimposed. The value of the voltage threshold accounts for its reduction with increasing MOSFET temperature, which is the temperature measured in each specific operating condition reported in the figures.

The vertical dashed red line indicates where the switching losses start, which almost coincides with the time at which the drain current starts to decrease. Looking at the intersection between the two dashed lines, it appears that the device’s gate–source voltage (violet waveform) is below or just above the threshold voltage at the beginning (red dashed line) of the interval, where the switching losses are greater than zero. Moreover, even when the gate–source voltage is greater than the threshold voltage at the beginning (red dashed line), for a large part of the interval where the power losses are greater than zero, the gate–source voltage is lower than the threshold one.

Considering this discussion, according to the experimental results in Figure 4 and Figure 5, there is no channel current (or it is negligible) when the drain current falls: hence, it is a capacitive current only. Therefore, the device can be modeled considering only its parasitic capacitance for the circuit analysis of the turn-off. It is worth noting that the drain current almost becomes a capacitive current due to the drain voltage increment. In other words, as the gate voltage decreases and the drain voltage increases, the drain current switches from a channel current to a capacitive one. After the red dashed lines, the drain current decreases because the channel current extinguishes and the capacitive current strongly reduces due to the capacitance reduction as the drain voltage increases. The variation in capacitance as a function of the drain-source voltage is reported in Figure 6.

3. Turn-Off Circuit Analysis and Theory Foundation with Experimental Validation

As reported in the literature and shown in Figure 2, the additional turn-off switching losses in the 3L MOSFET in comparison to the 4L MOSFET increase with increasing gate resistance and load [10,17,18,19,20]. Such greater switching losses are commonly attributed to the lower switching speed of the 3L MOSFET. Therefore, circuit analysis is performed in this section to obtain an analytical formulation of the current slew rate during the turn-off of 3L and 4L MOSFETs. The goal is the identification of an equation representing the effect of the gate resistance and load condition on the current slew rate for comparison purposes.

It is worth noting that to perform this comparison (Figure 4 and Figure 5), two MOSFETs with the same die were adopted. These MOSFETs differ by the presence of an additional source in one of them. This choice enabled us to properly compare 3L and 4L MOSFETs being the different behavior due to only the Kelvin source. For this reason, the parasitic capacitances, inductances, etc., are (ideally) the same in the equations reported in this section, regardless of whether an equation refers to the circuit with the 3L MOSFET or to the circuit with the 4L MOSFET. Obviously, the parasitic resistance and inductance of the Kelvin terminal appear only in the 4L MOSFET equations.

Figure 7 reports a circuit model of a 3L and a 4L MOSFET embedded in the converter. According to the previous considerations based on the analysis of the waveforms, the gate–source voltage is considered equal or below the threshold and, consequently, the voltage-controlled current generator between the drain and source is omitted.

From the inspection of Figure 7, it is apparent that the following Kirchhoff current laws (KCL) are valid for both MOSFETs:

$$i_d-c_{ds}{\displaystyle \frac{d{v}_{ds}}{dt}}-c_{dg}{\displaystyle \frac{d{v}_{dg}}{dt}}=0$$

(1)

$$i_g-c_{gs}{\displaystyle \frac{d{v}_{gs}}{dt}}+c_{dg}{\displaystyle \frac{d{v}_{dg}}{dt}}=0$$

(2)

Moreover, looking at the device’s parasitic capacitance loop, the following Kirchhoff voltage law (KVL) can also be considered for both MOSFETs:

$$v_{dg}+v_{gs}-v_{ds}=0$$

(3)

By substituting this KVL into Equation (1) and rearranging it, the following expression is obtained for both devices:

$${\displaystyle \frac{d{v}_{gs}}{dt}}={\displaystyle \frac{\left(c_{ds}+c_{dg}\right)\frac{d{v}_{ds}}{dt}-i_d}{c_{dg}}}$$

(4)

Similarly, by substituting the KVL into Equation (2) and considering Equation (4), the following expression is obtained for the gate current of both MOSFETs:

$$i_g={\displaystyle \frac{c_{gs}\left(c_{ds}+c_{dg}\right)+c_{dg}{c}_{ds}}{c_{dg}}}{\displaystyle \frac{d{v}_{ds}}{dt}}-\left({\displaystyle \frac{c_{gs}+c_{dg}}{c_{dg}}}\right)i_d$$

(5)

There is the following key difference when the KVL related to the driving loop is considered:

KVL—3L (Figure 7a)

$$L_s{\displaystyle \frac{d{i}_s}{dt}}+v_{gs}+L_g{\displaystyle \frac{d{i}_g}{dt}}+R_g{i}_g-V_{DRI}=0$$

(6)

KVL—4L (Figure 7b)

$$v_{gs}+\left(L_g+L_k\right){\displaystyle \frac{d{i}_g}{dt}}+R_g{i}_g-V_{DRI}=0$$

(7)

Equations (6) and (7) can be combined, respectively, with the previous one to obtain the analytical expression of the current slew rate. In fact, in the case of a 3L MOSFET, an additional equation is necessary because the source current is present in Equation (6). The necessary additional equation is obtained considering the KCL related to the Gaussian surface represented by the dashed green line in Figure 7a:

$$i_d+i_g-i_s=0$$

(8)

By substituting Equations (5) and (8) into Equation (6) and rearranging the results, the following expression is obtained for the current slew rate of a 3L MOSFET during turn-off:

$${{\displaystyle \frac{d{i}_d}{dt}}}_{3L}={\displaystyle \frac{\left[\begin{array}{c}{c}_{dg}\left(v_{gs}-V_{DRI}\right)+\\ +\left(L_s+L_g\right)\left(c_{gs}\left(c_{ds}+c_{dg}\right)+c_{dg}{c}_{ds}\right)\frac{d^2{v}_{ds}}{d{t}^2}+\\ +R_g\left(c_{gs}\left(c_{ds}+c_{dg}\right)+c_{dg}{c}_{ds}\right)\frac{d{v}_{ds}}{dt}+\\ -R_g\left(c_{gs}+c_{dg}\right)i_d\end{array}\right]}{L_s{c}_{gs}+L_g\left(c_{gs}+c_{dg}\right)}}$$

(9)

A similar equation can be obtained for the current slew rate of a 4L MOSFET by substituting Equation (5) into Equation (7) and rearranging the results as reported in Equation (10):

$${{\displaystyle \frac{d{i}_d}{dt}}}_{4L}={\displaystyle \frac{\left[\begin{array}{c}{c}_{dg}\left(v_{gs}-V_{DRI}\right)+\\ +\left(L_g+L_k\right)\left(c_{gs}\left(c_{ds}+c_{dg}\right)+c_{dg}{c}_{ds}\right)\frac{d^2{v}_{ds}}{d{t}^2}+\\ +R_g\left(c_{gs}\left(c_{ds}+c_{dg}\right)+c_{dg}{c}_{ds}\right)\frac{d{v}_{ds}}{dt}+\\ -R_g\left(c_{gs}+c_{dg}\right)i_d\end{array}\right]}{\left(L_g+L_k\right)\left(c_{gs}+c_{dg}\right)}}$$

(10)

In both cases, some considerations enable simplified, although less accurate, equations. In particular,

$$\left|\left(L_s+L_g\right){\displaystyle \frac{d^2{v}_{ds}}{d{t}^2}}\right|\ll \left|R_g{\displaystyle \frac{d{v}_{ds}}{dt}}\right|$$

$$\left|\left(L_k+L_g\right){\displaystyle \frac{d^2{v}_{ds}}{d{t}^2}}\right|\ll \left|R_g{\displaystyle \frac{d{v}_{ds}}{dt}}\right|$$

$$c_{gs}\gg c_{dg}$$

$$c_{ds}\gg c_{dg}$$

The first two relations are apparent from the typical switching waveforms (e.g., Figure 4 and Figure 5) and typical parasitic resistances (µΩ or mΩ) and inductances (nH) of the terminals. Considering that C_gs = C_iss-C_rss, C_dg = C_rss and C_ds = C_oss-C_rss, the relations among the capacitances are always satisfied (e.g., Figure 6). By applying these relations, Equations (9) and (10) can be approximated, respectively, as follows:

$${{\displaystyle \frac{d{i}_d}{dt}}}_{3L}\approx {\displaystyle \frac{\frac{c_{dg}}{c_{gs}}\left(v_{gs}-V_{DRI}\right)+R_g{c}_{ds}\frac{d{v}_{ds}}{dt}-R_g{i}_d}{L_s+L_g}}$$

(11)

$${{\displaystyle \frac{d{i}_d}{dt}}}_{4L}\approx {\displaystyle \frac{\frac{c_{dg}}{c_{gs}}\left(v_{gs}-V_{DRI}\right)+R_g{c}_{ds}\frac{d{v}_{ds}}{dt}-R_g{i}_d}{L_g+L_k}}$$

(12)

These simplified equations present the same numerator, while the denominator is different. The denominators in (11) and (12) represent the total inductance of the driver loop when, respectively, a 3L and a 4L MOSFET are considered. The greatest inductance in the first cases is due to the longer path; then,

$$L_s>L_k$$

(13)

$${\displaystyle \frac{1}{L_s+L_g}}<{\displaystyle \frac{1}{L_g+L_k}}$$

(14)

This result means that the greater current slew rate of the 4L MOSFET is due to the lower overall parasitic inductance of the power loop. This result complies with a previous study on the effect of gate inductance on switching power losses [21].

These results are consistent with the experimental switching waveforms reported in Figure 4 and Figure 5 and highlight the reasons behind the different switching speeds.

To experimentally verify the results obtained in Equations (11) and (12), an inductor, L_A, is added to the gate path of the 4L MOSFET in Figure 7b so that

$$L_{G,new}=L_G+L_A$$

(15)

The value of L_A was carefully chosen to obtain the same driving loop inductance.

$$L_A=L_s-L_k$$

(16)

Under this condition, the current slew rate of the 3L and 4L MOSFETs should be similar if the theoretical aspects obtained in Equations (11) and (12) are true:

$${{\displaystyle \frac{d{i}_d}{dt}}}_{4L}\approx {{\displaystyle \frac{d{i}_d}{dt}}}_{3L}$$

(17)

In other terms, proving Equation (17) is sufficient to prove Equations (11) and (12).

These equations have revealed that, during turn-off, the greater derivative drain current of 4L MOSFET is due to the lower driving loop in comparison to its 3L counterpart. It is worth noting that these equations do not have any other objective, e.g., they have not been developed to estimate switching losses. In other words, they have been developed for qualitative analysis to understand the reasons behind the different speeds; they have not been developed for quantitative estimation.

As mentioned before, to validate the theoretical aspect that emerged from this analytical model, an additional source inductance is added to the driving loop of the 4L MOSFET to obtain an overall driving loop inductance equal to the 3L one. The measurements show that, in this case, the 4L MOSFET’s current speed during turn-off coincides with that of its 3L counterpart, thus proving the analytical model’s intuition. In detail, Figure 8, Figure 9, Figure 10, Figure 11, Figure 12 and Figure 13 show the waveforms obtained for the 3L MOSFET (a) and 4L MOSFET (b) when L_A is added to the gate path of the 4L one in Figure 7b, and its inductance is chosen according to Equation (16). These figures confirm that, under this condition, the current slew rate is similar, thus proving the theoretical results.

4. Conclusions

The SuperJunction MOSFETs empowered by the addition of the Kelvin pin—4L MOSFETs—present lower switching losses than their 3L counterparts. The maximum difference between the switching losses of the two MOSFETs is obtained at a high load. This makes 4L MOSFETs the best choice in high-power-density applications when substantial load currents must be considered.

In this work, the turn-off switching losses of 3L and 4L MOSFETs are first experimentally compared. Then, circuit models and Kirchhoff laws are adopted to obtain simplified analytical expressions of the MOSFETs’ current slew rate. These expressions have highlighted the reasons behind the improvements obtained by adopting a 4L MOSFET during turn-off. The key information that emerged is that the turn-off improvement obtained by adopting the Kelvin source is due to the lower inductance of the driver loop of the 4L MOSFET instead of the decoupling between the driver and power loops. This result are also experimentally confirmed by adding an inductor to the gate loop of the 4L MOSFET to achieve similar total inductance in the driver loop for 3L and 4L MOSFETs. Under this condition, the same current slew rate is found, thus confirming our theoretical expressions.

Finally, the circuit analysis and the aforementioned expressions explain the reasons behind the increment in the difference in the turn-off losses between 3L and 4L MOSFETs with increasing gate resistance and load current.