A 48-Channel High-Resolution Ultrasound Beamforming System for Ultrasound Endoscopy Applications

Abstract

We introduce a highly efficient 48-channel ultrasound beamforming system ideal for ultrasound endoscopy applications. The system includes a transmitter and a receiver that allows for low-area, high-resolution imaging acquisition. The transmitter uses a charge redistribution HV (high-voltage) scheme to generate three-level pulses that actuate the transducer, implemented with the standard CMOS process for optimal cost and power savings. Meanwhile, the receiver features a sub-array structure and a delay generator that reduces the area usage. To achieve high-resolution ultrasound imaging acquisition with low computational power, we developed a Shift Coherence Factor (SCF) algorithm that is hardware-friendly. This approach delivers a lateral resolution of over 20% better than that of the conventional delay and sum (DAS) algorithm, with a contrast ratio of over 30 dB. The system was implemented in a 180 nm standard CMOS process with an area of 24.98 mm², power consumption of 8.23 mW per channel, achieving a delay resolution of 8.33 ns, and a low-area implementation of 0.52 mm² per channel. The system offers high-quality imaging acquisition with minimal additional area and power consumption, which has great potential for 3D imaging or catheterized ultrasound systems.

1. Introduction

Pancreatic and biliary cancers have some of the lowest cure rates, with five-year survival rates of only 12% and 28%, respectively [1]. Detecting these cancers early is crucial since a cure rate of more than 50% can be achieved. However, once these cancers metastasize, they are difficult to treat. Current diagnostic methods include ultrasound, CT, MR cholangiopancreatography, and endoscopic retrograde cholangiopancreatography [2]. Unfortunately, detecting early cancers of 1 cm or less using these methods is challenging. Histological confirmation is necessary for diagnosis, and ultrasound endoscopy is one of the available diagnostic methods [3]. It is used to obtain images, diagnose and locate lesions, and take biopsies [4]. However, the large outer diameter of the ultrasound endoscope (more than 10 mm) makes it challenging to perform a biopsy in the narrow bile duct or pancreatic duct.

Figure 1 illustrates the need for a catheter to integrate both the transmitter and receiver for ultrasound endoscopy to diagnose pancreaticobiliary diseases. This technique carries the risk of heat generation, which can harm living tissues. As a result, the total power consumption must be limited to 0.5 W or less. The diameter of the ultrasound endoscope should be smaller than that of the pancreaticobiliary duct, which requires the use of a low-area ASIC. Moreover, the number of input and output wires in the endoscope is severely limited, making it essential to obtain a high detection resolution to guide the needle for tissue biopsy. Therefore, low-power consumption and low-area occupancy implementation with high-resolution imaging are key requirements for catheterized applications.

First, the transmitter is the main power consumer in an ultrasound system and typically uses high-voltage pulses of tens of volts to actuate the transducer. Therefore, reducing the power consumption of the transmitter is crucial. The bipolar CMOS-DMOS (BCD) or HV process [5,6,7] is commonly used, and the approximate structure for this process is shown on the left side of Figure 2a. However, it has dynamic power losses due to high-voltage switching operation, and it can be expensive to fabricate. By using a standard CMOS process to alternately stack PMOS and NMOS [8], as shown on the right side of Figure 2a, dynamic power dissipation can be reduced through low-voltage switching. An alternative technique to achieve high power efficiency is using the charge redistribution method [8]. Conventional methods discharge by shorting both ends of the transducer to ground, as shown on the left of Figure 2b, but charge redistribution is accomplished by shorting both ends of the transducer, as shown on the right of Figure 2b, which allows the charge to be recycled to reduce dynamic power. However, the 2-level high-voltage pulses still generate dynamic power dissipation from the large parasitic capacitance from the transducers.

Second, the beamformer is responsible for coordinating the timing of the TX pulse with the timing of the echoes received from the multiarray transducers. To achieve a low-area system, it is crucial to generate delay information efficiently. The delay data can vary depending on the application, but tens of Mb or more data are typically needed to reconstruct a single image. The delay information can be specified in a lookup table (LUT) or internally calculated by the processing unit. Figure 3a shows the LUT-based architecture [8,9,10,11,12,13], which consists of an LUT that stores the delay data and a FIFO that receives the delay data and performs the beamforming operation. When a signal is received, the delay and stored delay information are processed in the FIFO. The delayed signals were then combined to generate a signal at the corresponding focal point. The more delayed the data, the larger the size of the LUT, which leads to a significant area overhead. Symmetric delay information was used to minimize the size of the LUTs [10]. However, it still requires a size of over 1 Mb. On the other hand, Figure 3b shows the delay calculator-based architecture [14,15,16,17]. The output signals from all ADCs are stored in memory. The delay calculator generates the delay information for each focal point. To obtain the corresponding delayed signal, the address in the memory is accessed by a calculated delay. The calculator is utilized instead of LUTs to save area, and it uses a power-consuming computation, which results in a smaller area with more significant power consumption.

Finally, while there are many image processing approaches [18], it is essential to consider beamforming algorithms to obtain high-quality images using an appropriate number of channels. The conventional delay and sum (DAS) algorithm [19] has some limitations in improving the lateral resolution and sidelobe rejection ratio, which are essential factors for image quality. Other algorithms have been developed to address these limitations, as shown in Figure 4. These algorithms are typically implemented through an external FPGA or GPU due to their high computational requirements. For example, a delayed multiplication and summation algorithm [20] improves the lateral resolution of an image through additional multiplication and square root operations. Another algorithm introduced a coherence factor [21] to reduce the number of arithmetic functions compared to the approach presented in [20]. However, even with these improvements, the algorithms still require division operations, which can be computationally expensive.

Based on the above considerations, we propose an ultrasound beamforming application-specific integrated circuit (ASIC) that is efficient in terms of both power and area. The ASIC includes three key features.

• A three-level biphasic charge redistribution HV (CRHV) TX pulser uses a standard CMOS process to increase the power efficiency.
• A hybrid beamforming architecture with an analog subarray beamformer and a calculator-based digital beamformer that uses FIFO instead of memory to achieve a low-area system.
• A hardware-efficient Shift Coherence Factor (SCF) beamforming algorithm that produces high-resolution images.

The paper is organized as follows. Section 2 introduces the block diagram and system features. Section 3 describes the implementation of the TX pulser, analog subarray beamformer, delay generator, and SCF beamformer. Section 4 presents the implementation results. Section 5 presents a discussion. Finally, Section 6 concludes the paper.

2. System Features

The proposed system is characterized by low power consumption, low area occupancy, and high-resolution image acquisition. To achieve low power consumption, we implemented a TX pulser based on charge redistribution and low area occupancy; a non-memory structure was implemented using a delay generator and FIFO, and an analog subarray architecture was used to mitigate the delay resolution and the number of channels in the digital beamformer. Finally, to achieve high-resolution image acquisition, the center frequency was set to 7.5 MHz, and the ADC sampling frequency was set to 60 MHz to enable the detection of the biopsy needle with high axial resolution. In addition, the SCF algorithm was implemented to ensure a low sidelobe and high lateral resolution, allowing for accurate biopsy needle guidance.

Figure 5 shows a block diagram of the overall system. The system operates by updating the parameter information of the transducer using an SPI interface. Then, it calculates the delay signal for TX beamforming and determines when the signal for each focal point arrives at the sensor using the updated parameters. This information is then used to generate the delay data. The delay data are utilized to perform beamforming of the received echo signal, which is further processed through the SCF algorithm to produce high-resolution image data. As a result, the system requires minimal input and output wires, except for the transducer interface, which only consists of input wires for power, clock, reset, and SPI communications and a multi-bit output wire for image data output.

Figure 6 shows the parameters of the pMUT 1D phased-array transducer. It is a 48-channel transducer with an 80 µm pitch, a frequency bandwidth of 6–10 MHz to cover the 7.5 MHz band, and a peak-to-peak voltage of up to 20 V.

3. Beamformer Implementation

3.1. CRHV TX Pulser

Figure 7 depicts the transmitter block and the timing diagram. The transmitter receives a 5 V power supply (VDDM) and a 60 MHz clock signal (CLKM) from an external source. The signal control logic generates the inputs TXIN1, TXIN2, and TXEN. A voltage doubler generates VDDH, a 10 V power source for the high-voltage pulser. To reduce the power consumption, CLKM is only asserted when TXEN is 0. The CRHV pulser takes TXIN1 and TXIN2 as inputs and produces cont1 to cont8 to drive the stacked NMOS and PMOS gates through the level shifters and logic gates. The resulting TX+ and TX− voltage pulse swings from VDDH to −VDDH and is applied to the transducer via a high-voltage switch (TXSW). TXSW uses standard CMOS and is implemented using the TXIN1 signal and a level shifter to receive a differential high voltage of 20 V.

Figure 8 illustrates the detailed operation of the CRHV pulser. The pulser used a full-bridge configuration to generate pulses differentially with a voltage of 20 Vpp. To utilize the standard CMOS process, the PMOS and NMOS are stacked alternately. During t1, the top left PMOS and bottom left NMOS are turned on, supplying 10 V to the positive terminal of the transducer and 0 V to the negative terminal. In t2, the floated output is shorted by the NMOS and PMOS in the middle through charge redistribution. Similarly, during t3 and t4, the transducer is charged and charge-redistributed, respectively. Therefore, the three-level 20 V output pulses effectively drive the transducer, which reduces the dynamic power by 50% compared to the conventional charge redistribution architecture [8].

3.2. Delay Generator

Figure 9 shows the proposed structure of the delay generator. It utilizes SPI communication to update the scan depth (R), number of channels (X), and wavelength. With the updated parameters and the stored sine values in the LUT, the time-of-flight (TOF) parameters are calculated. The TOF calculator is a circuit designed as a pipelined structure and implemented using the Taylor approximation [22] to reduce the computation. Instead of the traditional TOF calculation method, which requires finding the distance between each transducer element and the focal point, the proposed structure implements a delay generator block that calculates the channel-to-channel delay of the signal at each focus by calculating the channel on which the signal arrives first and its delay from other channels from the previously estimated TOF data. The output signals from this block are the TX delay data, fine(analog) delay data, coarse(digital) delay data, and RX switch-on signals. The TX delay is calculated only once for RX dynamic focusing and is based on a focus of half the scan depth per scan line. The fine delay and coarse delay, which are part of the RX delay, are calculated every clock for RX dynamic focusing, and the generated delay data are output through a register that matches the delay data with the timing of the received echo signal on each channel to enable accurate dynamic focusing. The fine delay calculates the delay between the three adjacent channels that the analog beamformer will be beamforming. The coarse delay calculates the delay between the 16 channels processed by the analog beamformer and then processed by the digital beamformer. Finally, the RX Enable signal is used to activate the RX switches based on the timing of the first signal to arrive at each channel in the calculated TOF data. By reducing the complexity of the TOF calculations, the proposed delay generator achieves relatively low power consumption and area occupancy. As a result, the proposed structure offers an efficient way to perform beamforming.

A memoryless structure can be realized using an RX-enabled signal generated by a delay generator block. As shown in Figure 10, an RX enable signal is turned on by calculating when the echo signal reaches the focus and returns to each channel based on the TX beamforming signal. When the signal is on, the RX switch is turned on, and the delay signal calculated for each channel is updated simultaneously with the reception of the echo signal on each channel. RX beamforming can be performed without storing all echo signals in memory because the delay information of the corresponding focal point can be calculated from the TOF data at the same time as the echo signal is received. Therefore, the signals received in real time can be kept as input signals with their corresponding delay data using a FIFO and then exported to the output.

3.3. Hybrid Subarray Beamforming Architecture

Figure 11 illustrates the use of a hybrid subarray beamforming architecture. This architecture employs both an analog RX beamformer [23] and a digital RX beamformer. The analog beamformer focuses the signals between adjacent channels with small delays, whereas the digital beamformer enhances the signal between relatively distant channels with significant delays. To reduce the number of delay cells required for the digital beamformer, we use a 3-channel analog subarray, which reduces the number of delay cells needed by a factor of three.

The waveform in Figure 12 represents a beamforming operation that utilizes a fine delay in an analog beamformer. Three signals control the analog beamformer: coarse delay, fine delay, and average signals. The coarse delay and fine delay signals indicate when the ADC is sampling, whereas the average signal is provided by adding the outputs of the three channels of the delay cells in the analog beamformer to perform a summation operation. To achieve a delay resolution that is 16 times higher while using a clock eight times the center frequency, the coarse delay signal is sampled through the positive edge, and the fine delay signal is sampled through the negative edge. This provides the same effect as using 1/3 FIFOs in a digital beamformer while using twice the clock and twice the FIFO depth.

3.4. Digital RX Beamformer

The digital RX beamformer structure is illustrated in Figure 13. The beamformer consists of two main components: a delay cell (FIFO) and an SCF processing block. The FIFO is designed to manage the delays that occur when the delay is generated using the scan depth of the target system and transducer parameters. The signal that has been delayed and phase-matched through the FIFO is then directed to the input of the SCF processing block for the proposed beamforming algorithm to enhance the imaging quality.

Figure 14 shows the structure of the SCF processor. Compared with the structure that utilizes the coherence factor [24], the division calculation is implemented with the help of a comparator. The division calculation of the coherence factor operation must be able to represent a value of less than 1 to be meaningful. However, the decimalization of division is hardware-intensive, making it challenging to implement. The proposed algorithm takes advantage of the fact that powers of two are easy to implement circuitously and performs a bit-shift operation to perform the multiplication or division operation. The output of the comparator is the difference between the two input values rounded to a power of two, and the output value of the comparator can be viewed as the coherence factor value. After, bit shifters multiply the delay and sum the outputs by the coherence factor. The comparator compares the two values and produces an output rounded to a power of two based on the magnitude of the difference. Bit shifting is used to implement the comparator, as it only requires comparing the difference in magnitude while multiplying by a power of two, which is not computationally intensive. The output of the comparator is then applied to the bit shifter, which shifts the bits to the left or right. Applying the coherence factor through the hardware efficient implementation results in improved lateral resolution and sidelobes. This is because the correlation coefficient increases the signal-to-noise ratio from the focal point with negligible errors from the rounded output from the bit shifter.

4. Implementation Results

Figure 15a shows the waveform measurement for the CRHV pulser. This component receives TXIN1 and TXIN2 signals from the signal control block and generates an output pulse that swings differentially by 20 Vpp and operates at 7.5 MHz, enabling the functionality of the pulser. On the other hand, Figure 15b shows the dynamic power loss of the capacitance in comparison to other references. The proposed work demonstrated a significantly lower dynamic power loss when compared to [7,8].

The proposed algorithm, Shift Coherence Factor (SCF), was compared to the DAS and CF algorithms based on their lateral resolution performance, as shown in Figure 16. Comparative simulations were performed using K-Wave [25]. Because the axial resolution is determined by the TX frequency, transducer bandwidth, and ADC bandwidth, we compared the performance of the three algorithms using the lateral resolution. The lateral resolution was tested at 8 mm, 13 mm, 17 mm, and 22 mm depths. The results showed that, regardless of the number of channels, the SCF algorithm outperformed the DAS algorithm by approximately 20% at all depths. The SCF algorithm also showed a similar level of resolution to the CF algorithm.

Figure 17 compares the contrast ratio (CR) between the cyst and the corresponding portion of the background to see the sidelobes. The CR was calculated by contrasting the average grayscale data values of the cyst and the highly reflective background. A lower CR indicates that the sidelobe is more extensive, whereas a higher CR implies smaller sidelobes. The results show that the 16-channel case has an overall lower CR due to the very wide sidelobes. However, even in this case, it shows an improvement of approximately 3 dB over DAS, and the 48-channel case shows that the proposed SCF algorithm results in a performance improvement of approximately 40 dB over DAS. Therefore, we can conclude that the hardware-efficient SCF algorithm does not suffer from significant performance degradation compared with the computationally intensive CF algorithm.

Table 1. Artix-7 XC7a100tcsg324 Synthesis Utilization Results.

Beamforming Algorithm	Channels	Logic LUTs	Memory LUTs	Regs	BRAM	DSP
Delay and Sum	16	36.27%	0.51%	22.91%	0	26.67%
Single Precision Coherence Factor	16	51.14%	0.51%	23.30%	0	57.08%
Shift Coherence Factor	16	39.21%	0.51%	23.22%	0	27.08%

shows the simulated utilization levels of FPGA synthesis using VIVADO for various beamforming algorithms, focusing on the RX beamformer. Specifically, a comparison is made between the DAS, CF, and proposed SCF algorithms. The table compares the FPGA utilization of logic, memory, register, RAM, and DSP. The results indicate that the SCF algorithm only differs from DAS by approximately 3% in Logic LUTs and shows no significant difference in overall utilization. On the other hand, the CF algorithm implemented with high precision uses more than 50% of logic LUTs and over 30% of DSPs. In other words, the proposed SCF algorithm does not significantly increase computation compared to DAS.

Table 2. Artix-7 XC7a100tcsg324 Synthesis Power Results.

Beamforming Algorithm	ALL	ETC	Delay Generator	FIFO	CF
Delay and Sum	483.080 W (100%)	25.309 W (5.2%)	359.546 W (74.4%)	98.495 W (20.4%)	0 W (0%)
Single Precision Coherence Factor	689.602 W (100%)	20.668 W (3%)	357.116 W (51.8%)	113.407 W (16.4%)	198.411 W (28.8%)
Shift Coherence Factor	522.020 W (100%)	27.404 W (5.3%)	353.826 W (67.8%)	112.823 W (21.6%)	27.967 W (5.3%)

compares the power consumption of the different algorithms after FPGA synthesis. Among them, DAS consumes the least power due to its simplicity. The proposed algorithm consumes approximately 5% more power than DAS. Additionally, the CF implemented using single-precision consumes approximately 30% more power than the proposed SCF. The additional power consumption of SCF is relatively small compared to that of CF because it reduces the amount of computation.

Figure 18 shows the image reconstruction results obtained using the ASIC. MATLAB simulation converted the reference image into a matrix-based echo signal according to the parameters of the ultrasound transducer. This transformed matrix was used as the input to an ASIC, and the output of the ASIC was reconstructed into an image using MATLAB. The CR of the background and cyst parts were calculated by comparing the pixel values of the image data directly. The results of DAS and CF shown in Figure 18a are 17.42 dB and 30.032 dB, respectively, exhibiting a difference of approximately 13 dB. By examining the images from one focal point each, we can detect where the image is smeared due to sidelobes. The proposed SCF makes the boundary between the cyst and background sharp, as shown in Figure 18b, which results from inverting the image from Figure 18a. It is observed that the image is relatively sharper, with values of 27.68 dB and 53.629 dB, respectively. The effect of sidelobes appearing in unwanted areas was more prominent in DAS.

Figure 19 shows the outcomes obtained after measuring the lateral resolution of each focus using the reference image. We assessed the lateral resolution at 10 mm and 25 mm depth. Our results demonstrate that the lateral resolution of the focus improves by more than 20% at all depths. This indicates that the proposed SCF can achieve a relatively good lateral resolution, even for images at close depths.

Figure 20 shows the reconstructed image when the reference image is a kidney. The image on the proposed CF is better at distinguishing the boundaries of tissues when a more complicated picture is fed in.

Figure 21a shows a micrograph of the implemented ASIC. The chip area is 4.98 mm × 4.98 mm, with 2.42 mm × 3.31 mm for the digital beamformer and 633.14 μm × 834.29 μm for the three channels of the analog beamformer. Figure 21b summarizes the performance of the chip.

Figure 22 shows the ratio of power consumption and area of the ASIC.

Table 3. Performance Comparison Table.

	This Work	JSSC2022 [14]	ISSCC2019 [8]	TBCAS2017 [10]	TBCAS2014 [9]
Process	180 nm	180 nm	180 nm	130 nm	130 nm
Center Frequency	Standard CMOS	Standard CMOS	Standard CMOS	Standard CMOS	Standard CMOS
Delay Dynamic Range (Max. delay/delay resolution)	160 (1.33 μs/8.33 ns)	N/A	256 (1.28 μs/5 ns)	1260 (7.875 μs/6.25 ns)	1280 (8 μs/6.25 ns)
Memory Usage	X	SRAM	X	X	X
Delay cell type	Analog S/H + FIFO	Memory	Analog S/H	FIFO	Analog S/H + FIFO
Overall Power	395 mW	142.3 mW	371.88 mW	605 mW	1.14 W
# Channel	48	64	36	64	64
Delay Generation (Method)	On-chip (Calculation)	On-chip (Calculation)	On-chip (LUT)	On-chip (LUT)	Off-chip
TX Beamforming	O	O	O	X	X
Area (mm2)	24.8	32.5	11.75	30.25	19.4

presents a comparison of on-chip delay generation for ultrasound beamformers, highlighting the proposed ASIC’s unique advantage in minimizing the circuit complexity and footprint. The proposed work eliminates memory and LUT usage, leading to a significantly smaller silicon footprint than the LUT-based implementation in [8] (49 focal points, which is insufficient for high-resolution imaging). Furthermore, the off-chip approach proposed in [9] incurs greater area overhead. These factors combined demonstrate the proposed ASIC’s significant area advantage.

5. Discussion with Further Work

The current system requires a TOF calculator per channel for the transducer. As a result, the digital beamformer’s power and area are significantly impacted by the number of calculators. To optimize the power and area efficiency, reducing the number of calculators is recommended. One way to achieve this is by implementing a small number of calculators using time division instead of one calculator per channel. This approach can help maximize power and area savings while maintaining the same number of channels.

In Figure 23, it is demonstrated that implementing a Time Division Multiplexing (TDM) based delay generator can decrease the frequency at which the delay is updated. However, for the current application, the delay in one channel of a single scan line changes only slightly for every two to three sampling points. This implies that adjusting the degree to which the current structure is time-sliced can be executed more efficiently, depending on the required application.

The results of the gate-level synthesis are presented in

Table 4. Design Compiler Synthesis Result.

Beamformer Architecture	Area	Power	Cell Count
Digital Beamformer	6.76 mm2	358 mW	270,317
TDM Digital Beamformer	2.42 mm2	226 mW	84,772

. We changed the delay update interval from 1 clock to 48 clock using a TDM-based delay generator. As a result, the area was reduced to 35.8% from 6.76 mm² to 2.42 mm². Furthermore, the power consumption of the TDM structure was also reduced to 58.57%, indicating that an efficient low-area and low-power implementation is feasible. These findings suggest that the structure has the potential for use in catheter applications that require a small area and in 3D applications that require a large number of channels.

6. Conclusions

This paper presents a mixed-signal ultrasound beamformer ASIC for 48-channel ultrasound endoscopy applications, featuring integrated transmit and receive functionalities to achieve high-resolution image acquisition with reduced power and area consumption. To achieve this, we propose three key design innovations: a charge redistribution-based CRHV pulser generating low-power three-level pulses, a sub-array RX beamformer with a memoryless delay generator for a minimal per-channel area, and a hardware-friendly SCF algorithm enabling high-resolution imaging with superior power-to-area efficiency and reduced computational complexity. Consequently, our system surpasses conventional DAS algorithms in terms of image quality while achieving significant power and area savings compared to prior works. Its compact design and efficient operation hold promise for advanced applications in 3D ultrasound imaging and catheterization.