An Optimized Device Structure with a Highly Stable Process Using Ferroelectric Memory in 3D NAND Flash Memory Applications
Round 1
Reviewer 1 Report
Comments and Suggestions for AuthorsThe present paper proposes a way to improve on known Flash-like 3D NAND memory devices. A new device structure, incorporating ferroelectric memories instead of the standard Flash or charge-trap memories often used in 3D NAND architectures, is proposed. While avoiding some of the issues typical of those latter solutions, specific problems arise from this new architecture and have to be addressed. In particular, GSL and SSL transistors can be disturbed during memory operations due to their ferroelectric nature. The solution brought through this paper, supported by process and electrical simulation, as well as electric measurements on test ferroelectric capacitors, consists in blunting the ferroelectric behavior of said transistors by choosing the right metal to be used as top electrode (gate).
The paper’s topic is highly relevant in the field of memory devices and data storage. The proposed methodology doesn’t look to have any major flaw, and the obtained results look promising. I however think a few things could be improved in order to communicate the results better.
I feel some of the parts of this paper, especially at the beginning, would need the inclusion of more references from the literature to support a certain number of assertions made in the text:
- “… no need for a lithography process” (l. 38)
- “Nevertheless, recent outcomes… encounter various limits” (l. 42-47)
- “In contrast … stability and reliability” (l. 53-55)
- “This is because… to control it” (l. 69-72)
- “Fortunately, … compressive stress” (l. 109-111)
- “Conventional” (l. 122)
- “… string hole, channel layer and macaroni oxide…” (l. 132)
- “… the threshold voltage of HZO can easily fluctuate…” (l. 136-137)
Concerning the paper title and subsequent developments in the text, do you feel it is still justified to call the device of interest “3D NAND flash memory” as flash memory is replaced with ferroelectric memory here? Is it a common thing in the literature to keep calling this kind of structures “flash”?
To conclude this paper, I think that the authors, if possible, should elaborate a little bit more on this work’s perspectives. Process and electrical simulation for the new NAND structure has been carried out to investigate its feasibility, supported by measurements performed on ferroelectric capacitors with different top electrodes. What is the next step towards the manufacturing of such devices? Can manufacturing hurdles be foreseen? Is something missing at this point to start the production of the devices proposed in this paper?
Outside of those general remarks, I noticed a few minor problems or omissions that should be easily addressed by the authors:
- “in-stead of metal“ (l. 15). As nickel is already a metal, you probably meant “instead of tungsten (W)” here? Please check any redundancy with the next sentence if a correction is necessary.
- “In the simulation… for the ferroelectric material” (l. 211-213). Shouldn’t the saturation and remanent polarizations have different values ?
- What is the experimental methodology used to obtain the results displayed in figures 6.a and 6.b? Is it similar to what was used in [13]? Please specify.
- Using the expression “control gate” (l. 139) may be a bit confusing as it refers to something specific in the field of memory devices. Did you mean “select transistor” instead ?
- What is the thickness of the HZO layer used to obtain the results displayed in Figure 6?
Comments on the Quality of English LanguageHere are some of the possible typos I found throughout the text (as well as some suggestions) :
- Figure -> Figures? (l. 125)
-“Figure 2…etched” (l. 154-157). I am not sure this sentence is worded properly. Please check.
-“…the deposited layer is etched simultaneously…” (l. 161) -> layers are etched (referring to both SiO2 and Si3N4 ?
- “The implemented structure, which is represented by only half of Figure 3(a)” (l. 185-186): do you instead mean that Figure 3.a only represents half of the structure?
- “A novel structure with the process” (l. 350): please check the syntax
- “Here … to date” (l. 213-215) : I am not sure the sentence is grammatically correct. Did you mean you chose your Pr/Ps values for the simulation according to the largest values you found in the literature? Please check and add references if necessary.
- “size” (l. 228) : you probably meant value or strength ?
Author Response
Dear editor and reviewers:
Thank you very much for your helpful comments and suggestions. We carefully reviewed and revised the manuscript according to your comments. Attached are the overall responses to the editor’s and reviewers’ comments and two revised manuscripts of which the first one has a full text and the second one includes the notations highlighted in blue. Please advise us of any comments for our responses. We greatly appreciate your thoughtful attention and support for our manuscript.
Yours sincerely,
Yoon-Heub Song
Department of Electronic Engineering,
Hanyang University, Seoul, Korea.
Note:
Black-colored text: reviewer’s comments and our responses
Blue-colored text: revised texts in the manuscript
Comments and Suggestions for Authors
The present paper proposes a way to improve on known Flash-like 3D NAND memory devices. A new device structure, incorporating ferroelectric memories instead of the standard Flash or charge-trap memories often used in 3D NAND architectures, is proposed. While avoiding some of the issues typical of those latter solutions, specific problems arise from this new architecture and have to be addressed. In particular, GSL and SSL transistors can be disturbed during memory operations due to their ferroelectric nature. The solution brought through this paper, supported by process and electrical simulation, as well as electric measurements on test ferroelectric capacitors, consists in blunting the ferroelectric behavior of said transistors by choosing the right metal to be used as top electrode (gate).
The paper’s topic is highly relevant in the field of memory devices and data storage. The proposed methodology doesn’t look to have any major flaw, and the obtained results look promising. I however think a few things could be improved in order to communicate the results better.
Comment 1.
I feel some of the parts of this paper, especially at the beginning, would need the inclusion of more references from the literature to support a certain number of assertions made in the text:
- “… no need for a lithography process” (l. 38)
- “Nevertheless, recent outcomes… encounter various limits” (l. 42-47)
- “In contrast … stability and reliability” (l. 53-55)
- “This is because… to control it” (l. 69-72)
- “Fortunately, … compressive stress” (l. 109-111)
- “Conventional” (l. 122)
- “… string hole, channel layer and macaroni oxide…” (l. 132)
- “… the threshold voltage of HZO can easily fluctuate…” (l. 136-137)
Answer to comment #1
Thank you for your valuable comments. As you suggested, we included references in the correspond parts as follows:
Sentence: “… no need for a lithography process [2]” (l. 38)
Sentence: “Nevertheless, recent outcomes… encounter various limits [4]” (l. 42-47)
Sentence: “In contrast … stability and reliability [5]” (l. 53-55)
Ref. [5 ]: S. Tehrani, J. Pak, M. Randolph, Y. Sun, S. Haddad, E. Maayan and Y. Betser, “Advancement in Charge-Trap Flash memory technology”, 2013 5th IEEE International Memory Workshop, May. 2013, DOI: 10.1109/IMW.2013.6582082
Sentence: “This is because… to control it.” (l. 69-72)
- The sentence has been changed to another reviewer's request.
Sentence: “Fortunately, … compressive stress [14]” (l. 109-111)
Sentence: “Conventional [13]” (l. 122)
Sentence: “… string hole, channel layer and macaroni oxide… [1][2]” (l. 132)
Sentence: “… the threshold voltage of HZO can easily fluctuate…[9-12]” (l. 136-137)
Comment 2.
Concerning the paper title and subsequent developments in the text, do you feel it is still justified to call the device of interest “3D NAND flash memory” as flash memory is replaced with ferroelectric memory here? Is it a common thing in the literature to keep calling this kind of structures “flash”?
Answer to comment #2
Thank you for your insightful comments. The term “flash” was introduced by Toshiba to erase and reprogram certain cell bundles called "block" at once in its 2D NAND flash memory structure, rather than individually selecting and erasing specific cells. This approach was adopted due to the shared sources and drains are shared among cells, enhancing integration, while quickly erasing multiple cells simultaneously. Of course, there has been debate about using the term "flash" even when referring to structures incorporating ferroelectric memory. Despite this, the 3D NAND flash memory structure, utilizing Charge Trap Flash (CTF) memory, has been in use since 2007 with ongoing minor structural and behavioral adjustments, while it has continued to utilize vertical stacking and vertical channel memory structures. Furthermore, ferroelectric memory behaves similarly to CTF memory, except for the reversal in threshold voltage change after memory operation. Given the priority of low cost in the memory industry, major 3D NAND flash memory manufacturers will likely integrate ferroelectric memory into the existing 3D NAND flash memory structure and operation. Consequently, despite the shift of the memory device from CTF to ferroelectric memory, the structure and functionality of “3D NAND flash memory” are expected to keep calling consistent, thus retaining the same name.
Comment 3.
To conclude this paper, I think that the authors, if possible, should elaborate a little bit more on this work’s perspectives. Process and electrical simulation for the new NAND structure has been carried out to investigate its feasibility, supported by measurements performed on ferroelectric capacitors with different top electrodes. What is the next step towards the manufacturing of such devices? Can manufacturing hurdles be foreseen? Is something missing at this point to start the production of the devices proposed in this paper?
Answer to comment #3
Thank you for your valuable comments. As you suggested, we added a more detailed explanation to the conclusion, including the perspective of this study and the contents of the next research step, as follows, “Based on these results, we will first manufacture 2D FeFETs in subsequent studies, measure, and verify whether the operation of GSL and SSL transistors can be as stable as the simulation results. Then 3D GAA structures will be manufactured to verify operational performance.”.
In addition, the next steps in manufacturing these devices and the expected obstacles are outlined as follows. First, the variation in threshold voltage according to the gate electrode change in the 2D FeFET device needs verification, based on the verified polarization characteristics change in the MFS capacitor. If stable threshold voltage control aligns with simulation results, GSL and SSL transistors of the actual GAA 3D structure will be manufactured to ensure stability. The GAA structure, with the gate electrode surrounding the channel, is expected to offer more reliable threshold voltage control, requiring confirmation. Moreover, predictive research for the 3D NAND flash memory structure, comprising numerous stacked layers, can be conducted based on prior measurement results.
Furthermore, the performance of ferroelectric memory poses a significant obstacle for future research or production. Currently published ferroelectric memory exhibits a memory window of 4 to 5 V, notably lower than the average memory window of CTF memory, which is 7 to 8 V. Despite ferroelectric memory’s advantages of relatively low power consumption and high speed compared to CTF memory, its smaller memory window is the primary reason it has not yet been applied to 3D NAND flash memory structures. Thus, the limited memory window of ferroelectric memory is the main hindrance to the production of 3D NAND flash memory with ferroelectric memory.
Comment 4.
Outside of those general remarks, I noticed a few minor problems or omissions that should be easily addressed by the authors:
- “instead of metal“ (l. 15). As nickel is already a metal, you probably meant “instead of tungsten (W)” here? Please check any redundancy with the next sentence if a correction is necessary.
- “In the simulation… for the ferroelectric material” (l. 211-213). Shouldn’t the saturation and remanent polarizations have different values ?
- What is the experimental methodology used to obtain the results displayed in figures 6.a and 6.b? Is it similar to what was used in [13]? Please specify.
- Using the expression “control gate” (l. 139) may be a bit confusing as it refers to something specific in the field of memory devices. Did you mean “select transistor” instead ?
- What is the thickness of the HZO layer used to obtain the results displayed in Figure 6?
Answer to comment #4
Thank you for your valuable comments. The modifications to the parts you pointed out are as follows:
Question: “instead of metal“ (l. 15). As nickel is already a metal, you probably meant “instead of tungsten (W)” here? Please check any redundancy with the next sentence if a correction is necessary.
Answer: Thank you for pointing out the mistake. The sentence was corrected as follows: instead of tungsten (W).
Question: “In the simulation… for the ferroelectric material” (l. 211-213). Shouldn’t the saturation and remanent polarizations have different values?
Answer: Thank you for pointing out the mistake. The saturation polarization was corrected to 60 μC/cm2.
Question: What is the experimental methodology used to obtain the results displayed in figures 6.a and 6.b? Is it similar to what was used in [13]? Please specify.
Answer: The results depicted in Figure 6.a and 6.b were obtained using the structure shown in Figure 5. Specifically, the MFS capacitor structure of W(Ni)/HZO/Si was fabricated, and the change in polarization characteristics of the actual device according to the mechanical stress change applied to the lower HZO thin film was confirmed. This change stemmed from differences in the upper metal electrode during the annealing process in this fabrication. Concurrently, the correlation with the change in polarization characteristics due to stress change, as confirmed by process simulation, referenced the results of ref. [13].
Question: Using the expression “control gate” (l. 139) may be a bit confusing as it refers to something specific in the field of memory devices. Did you mean “select transistor” instead ?
Answer: As you commented, we changed "control gate" to "select transistor".
Question: What is the thickness of the HZO layer used to obtain the results displayed in Figure 6?
Answer: The thickness of the HZO layer is 9 nm.
Comments on the Quality of English Language
Here are some of the possible typos I found throughout the text (as well as some suggestions) :
- Figure -> Figures? (l. 125)
- “Figure 2…etched” (l. 154-157). I am not sure this sentence is worded properly. Please check.
- “…the deposited layer is etched simultaneously…” (l. 161) -> layers are etched (referring to both SiO2 and Si3N4 ?
- “The implemented structure, which is represented by only half of Figure 3(a)” (l. 185-186): do you instead mean that Figure 3.a only represents half of the structure?
- “A novel structure with the process” (l. 350): please check the syntax
- “Here … to date” (l. 213-215) : I am not sure the sentence is grammatically correct. Did you mean you chose your Pr/Ps values for the simulation according to the largest values you found in the literature? Please check and add references if necessary.
- “size” (l. 228) : you probably meant value or strength ?
Answer to comment on the Quality of English Language
Thank you for your valuable comments. We revised the expression according to your comments as follows:
Comment: Figure -> Figures? (l. 125)
Answer: We changed “Figure” to “Figures”.
Comment: “Figure 2…etched” (l. 154-157). I am not sure this sentence is worded properly. Please check.
Answer: We revised the sentence as follows: “Figure 2 illustrates the formation process of the proposed structure. Figure 2(a) shows the GSL electrode formation process. During the formation process, the silicon oxide and nickel metal electrode are deposited and immediately etched.”.
Comment: “…the deposited layer is etched simultaneously…” (l. 161) -> layers are etched (referring to both SiO2 and Si3N4 ?
Answer: Referring to both SiO2 and Si3N4, we revised the sentence as follows: "the deposited layers are etched simultaneously".
Comment: “The implemented structure, which is represented by only half of Figure 3(a)” (l. 185-186): do you instead mean that Figure 3.a only represents half of the structure?
Answer: To clarify this, we revised the sentence as follows: “The implemented structure, which is represented by only half of the structure depicted in Figure 3(a), “.
Comment: “A novel structure with the process” (l. 350): please check the syntax
Answer: Thank you for pointing out the mistake. We revised the sentence as follows: “The novel structure and process were presented to suppress”.
Comment: “Here … to date” (l. 213-215) : I am not sure the sentence is grammatically correct. Did you mean you chose your Pr/Ps values for the simulation according to the largest values you found in the literature? Please check and add references if necessary.
Answer: To clarify the meaning, we revised the sentence and added a reference as follows: “Here, the polarization characteristic parameter used in this work represents one of the largest values of ferroelectric polarization characteristics to date [17].”.
Comment: “size” (l. 228) : you probably meant value or strength ?
Answer: To clarify this, we revised the sentence as follows: “in the strength of the applied electric field,”
Author Response File: 
Author Response.pdf
Reviewer 2 Report
Comments and Suggestions for Authors1. Line15, please correct “in-stead”
2. From Line62-85, this paper describes the advantage & disadvanage of different technologies. But, maybe ferroelectric materials just the core techniques that you want to involve. Please concise the description in the corresponding part.
3. From Line130-132, explain the structure reduces manufacturing costs, with a minimized number of process steps. Can you detail explain what processing steps reduces?
4. From Line 143-145, could you explain what leads to this difference?And Ref[13] has the different combination of material, like TiN/HZO/W. In this paper, it seems like that this is W/HZO/Poly-Si, will it have the same effect ? The stress condition is determined by different materials combination.
5. From Line173-175, Do you have any refernce or experiment data to support this temperature range between 600 and 700 oC ? Also, what is the detail annealing parameters?
6. Line 193-197, Do you have a reference or similar model to support such dimension of structure?
7. From Line 211-215, please give the reference to support this simulation parameter selection?
8. From 316-317, Maybe this number should not be a certain value since you just use 9nm and 13.5nm to do the test.
9. Figure 8 label should not include “is”
10. Could you check the reference format, for example, in Ref[11], the authors’ name should be separated by the comma instead of semicolon ?
Author Response
Dear editor and reviewers:
Thank you very much for your helpful comments and suggestions. We carefully reviewed and revised the manuscript according to your comments. Attached are the overall responses to the editor’s and reviewers’ comments and two revised manuscripts of which the first one has a full text and the second one includes the notations highlighted in blue. Please advise us of any comments for our responses. We greatly appreciate your thoughtful attention and support for our manuscript.
Yours sincerely,
Yoon-Heub Song
Department of Electronic Engineering,
Hanyang University, Seoul, Korea.
Note:
Black-colored text: reviewer’s comments and our responses
Blue-colored text: revised texts in the manuscript
Comments and Suggestions for Authors
Comment 1.
Line15, please correct “in-stead”
Answer to comment #1
Thank you for pointing out the mistake. We corrected it to "instead".
Comment 2.
From Line62-85, this paper describes the advantage & disadvantage of different technologies. But, maybe ferroelectric materials just the core techniques that you want to involve. Please concise the description in the corresponding part.
Answer to comment #2
Thank you for the valuable comments. As you suggested, we summarized the description in the corresponding part as follows:
To address this issue, research on next-generation memories to replace CTF memory in current 3D NAND flash memory structures has been conducted [8]. Ferroelectric memory, among these new concepts, offers advantages similar to resistance change memory, such as low power consumption and high operating speed. Its structure closely resembles the oxide-nitride-oxide (ONO) structure used in CTF flash memory [9-12]. Consequently, the NAND flash memory structure utilizing ferroelectric memory retains the fundamental advantage of seamlessly preserving the existing NAND flash memory structure and operational methodology. Owing to these inherent strengths, research on applying ferroelectric memory to the 3D NAND structure has progressed rapidly compared to other memory devices, with some instances of tangible devices being fabricated to demonstrate the feasibility of the aforementioned approach [13].
Comment 3.
From Line130-132, explain the structure reduces manufacturing costs, with a minimized number of process steps. Can you detail explain what processing steps reduces?
Answer to comment #3
Thank you for your valuable comments. The structure proposed in this paper is based on a 3D NAND flash memory structure. Therefore, it has the same advantage that a lithography process is not required to form each memory cell, which is a representative feature of 3D NAND flash memory. As is generally known, the lithography process incurs the highest process cost in semiconductor manufacturing, and thus the overall process cost can be significantly lowered by reducing the reliance on lithography.
Comment 4.
From Line 143-145, could you explain what leads to this difference? And Ref[13] has the different combination of material, like TiN/HZO/W. In this paper, it seems like that this is W/HZO/Poly-Si, will it have the same effect? The stress condition is determined by different materials combination.
Answer to comment #4
Thank you for your thoughtful comments. Since the polarization characteristics can be increased or decreased by controlling the difference between the gate metals used in control transistor regions (SSL and GSL) compared to other WLs, Ni was selected as the gate electrode metal for SSL and GSL to suppress polarization properties caused by differences in the thermal expansion coefficient of Ni and HZO thin films. Ref. [14](Orignal Ref[13]) employs a TiN/HZO/W structure, unlike W(Ni)/HZO/Si structure used in this paper, and investigates altering the polarization properties of the HZO thin film during the annealing process by using various metals with different thermal expansion coefficients from W to Ni as the lower electrode. Conversely, this paper assumes that these characteristics apply to a 3D NAND flash memory structure using polysilicon as a channel. Therefore, the change in the polarization characteristics of HZO in the MFS capacitor structure of the W(Ni)/HZO/Si structure was measured and analyzed. The results confirmed that the difference in polarization characteristics between the device using W and the device using Ni was clearly observed by the metal electrode, and the polarization characteristics could be negligibly suppressed, especially when Ni was used.
Comment 5.
From Line173-175, Do you have any refernce or experiment data to support this temperature range between 600 and 700 oC ? Also, what is the detail annealing parameters?
Answer to comment #5
Thank you for the valuable comments. The temperature of the annealing process used in this paper is generally known as the temperature that activates the polarization properties of HZO, as referenced from ref. [11]. Additional parameters of the annealing process include the gas (N2) and pressure (760 Torr).
Comment 6.
Line 193-197, Do you have a reference or similar model to support such dimension of structure?
Answer to comment #6
Among the dimensions of each structure described in lines 193-197, the thickness of HZO was referenced from ref. [17]. In addition, the dimensions of the overall 3D NAND flash memory structure, especially the gate lengths of SSL and GSL, were referenced from ref. [2].
Comment 7.
From Line 211-215, please give the reference to support this simulation parameter selection?
Answer to comment #7
The polarization characteristics parameters described in lines 211-215 were referenced from ref. [17]. As explained in the text, the referenced research results exhibited significantly better polarization characteristics than other research results published at the time through the 'Quenching process', which is why they were cited in this paper.
Comment 8.
From 316-317, maybe this number should not be a certain value since you just use 9nm and 13.5nm to do the test.
Answer to comment #8
Thank you for your valuable comments. As you suggested, we revised the sentence as follows: “Therefore, in this paper, the optimal thickness for controlling ferroelectric properties through stress change caused by the annealing process was set to 9.5 nm.”.
Comment 9.
Figure 8 label should not include “is”
Answer to comment #9
Thank you for pointing out the mistake. As you suggested, we revised the sentence as follows: “Memory operation results in: (a) WL4, (b) GSL, and (c) SSL”
Comment 10.
Could you check the reference format, for example, in Ref[11], the authors’ name should be separated by the comma instead of semicolon ?
Answer to comment #10
Thank you for pointing out the mistake. We carefully reviewed and revised the reference format in ref. [11] as follows: “K. Florent, M. Pesic, A. Subirats, K. Banerjee, S. Lavizzari, A. Arreghini, L. Di Piazza, G. Potoms, F. Sebaai, S. R. C. McMitch-ell, M. Popovici, G. Groeseneken and J. Van Houdt, ” Vertical Ferroelectric HfO2 FET based on 3-D NAND Architecture: To-wards Dense Low-Power Memory”, IEEE International Electron Devices Meeting, San Francisco, CA, USA, 1–5 December 2018; pp. 43–46.”
Additionally, we revised other references in the same way. Thank you for your thoughtful comments again.
Author Response File: Author Response.pdf
