SC-IZ: A Low-Cost Biologically Plausible Izhikevich Neuron for Large-Scale Neuromorphic Systems Using Stochastic Computing

Abstract

Neurons are crucial components of neural networks, but implementing biologically accurate neuron models in hardware is challenging due to their nonlinearity and time variance. This paper introduces the SC-IZ neuron model, a low-cost digital implementation of the Izhikevich neuron model designed for large-scale neuromorphic systems using stochastic computing (SC). Simulation results show that SC-IZ can reproduce the behaviors of the original Izhikevich neuron. The model is synthesized and implemented on an FPGA. Comparative analysis shows improved hardware efficiency; reduced resource utilization, which is a 56.25% reduction in slices, 57.61% reduction in Look-Up Table (LUT) usage, and a 58.80% reduction in Flip-Flop (FF) utilization; and a higher operating frequency compared to state-of-the-art Izhikevich implementation.

1. Introduction

The remarkable capabilities of the brain have inspired engineers to develop novel hardware and computational architectures that mimic or draw inspiration from the brain’s principles [1]. Spiking Neural Networks (SNNs) are unlike conventional Artificial Neural Networks (ANNs) that more closely resemble the structure and function of biological neural networks in the brain [2,3]. SNNs offer advantages such as energy efficiency on event-driven neuromorphic hardware and the ability to perform complex tasks like spike pattern recognition [4,5,6], image segmentation [7], optical flow estimation [8], and localization [9,10,11] due to their rich spatiotemporal dynamics and event-driven paradigm. The emergence of large-scale neuromorphic chips with a high number of neurons has indeed opened up new possibilities for the field of SNNs. These chips provide the computational power and resources required to simulate and implement complex SNNs at scale [3,12,13,14]. However, to fully harness the potential of these chips, it is essential to design neuronal models that strike a balance between computational efficiency and biological plausibility.

Neuromorphic research has developed various neuronal models that simulate real neurons at different levels of abstraction. These models range from highly detailed biophysical models to simplified abstract models. The choice of abstraction level depends on the balance between biological realism and computational efficiency required for a specific application [15,16]. Neuronal models can be expressed using ordinary differential equations (ODEs). The Hodgkin–Huxley model [17] is highly biologically accurate but computationally expensive due to its complexity, which consists of four equations and tens of biophysically meaningful parameters. The Leaky Integrate-and-Fire (LIF) model [16] consists of one equation that is the easiest to implement but lacks some fundamental properties of cortical spiking neurons. The Izhikevich model [18], consisting of two equations, can exhibit firing patterns of various cortical neurons and provides a good balance between computational efficiency and biological plausibility. It helps in understanding the temporal structure of cortical spike trains and how the neocortex processes information. Therefore, the Izhikevich neuron model is considered both computationally efficient and biologically plausible [16,19].

Researchers have explored various approaches for hardware implementation of the Izhikevich neuron model, aiming to replicate its behavior while leveraging specialized hardware for efficient computations. Ref. [20] involves replacing the quadratic polynomial of the Izhikevich model with a PieceWise Linear (PWL) model. However, the PWL model deviates significantly from the original quadratic polynomial and incurs high hardware costs. Another approach, proposed in [15], utilizes COordinate Rotation DIgital Computer (CORDIC) algorithms to calculate the quadratic polynomial. However, this method requires 12 iterations for accurate computation. In [21], researchers replaced the quadratic polynomial with an equation involving $cosh$ and $sinh$ functions, but this approach demands significant resources for achieving the desired performance. To simplify the scheme in [21], Ref. [22] used only the $cosh$ function to approximate the quadratic polynomial, yet this simplified scheme relies on the Deme GA search algorithm to find suitable parameters.

Graphics Processing Units (GPUs) have been widely used for executing neural network models due to their inherent parallel nature. However, cost and power constraints have driven the exploration of alternative computing architectures [23,24]. While Application-Specific Integrated Circuit (ASIC) design can be fast and efficient, it suffers from inflexibility and a long development time [25]. Over the past few years, Field-Programmable Gate Array (FPGA) platforms have become increasingly popular for addressing the needs of large-scale neuromorphic applications. FPGA implementation offers rapid, accurate, compact, and flexible alternatives compared to ASIC [26,27,28].

In contrast to previous approaches to hardware implementation of Izhikevich neurons, our proposal advocates for the utilization of stochastic computing (SC), an unconventional computing technique that has demonstrated effectiveness in specific applications [29,30,31,32,33,34,35,36]. It processes information using probabilities instead of conventional binary or real-valued representations [37]. SC encodes data as a sequence of random bits and performs computations using simple logic gates, often requiring fewer hardware resources compared to conventional binary computing [38]. SC enables efficient hardware utilization by leveraging parallel computations. Additionally, the probabilistic nature of SC allows for the mitigation of individual bit errors or transient disturbances through the statistical properties of the random sequences [39]. Stochastic integrator, a computation element often applied in SC, is utilized for solving Laplace’s equations, logarithm functions, and high-order polynomials [30,40].

In this paper, we introduce SC-IZ, a low-cost stochastic computing-based Izhikevich neuron model specifically designed for large-scale neuromorphic systems. The implementation of SC-IZ is performed on an FPGA platform, leveraging the flexibility, logic density, and rapid development cycle offered by FPGAs.

Our main contributions are as follows:

• We introduce SC-IZ, an Izhikevich neuron model based on stochastic computing (SC). In order to adapt the Izhikevich neuron model to the SC domain, we make mathematical modifications to accommodate the probabilistic nature of SC computations.
• We conduct a comprehensive investigation into the accuracy of the proposed SC-IZ model. This analysis includes error assessment and the study of its biologically plausible behavior. Simulation results indicate that our model can accurately represent various biologically plausible characteristics, similar to the original Izhikevich model.
• We validate the efficiency of the proposed SC-IZ model by synthesizing and implementing it on an FPGA platform. A comparative analysis is performed against state-of-the-art Izhikevich hardware implementations. The results demonstrate that SC-IZ exhibits improved hardware efficiency.

The remaining sections of the paper are organized as follows: Section 2 provides a review of stochastic computing and the original Izhikevich neuron model, and presents our SC-IZ neuron model. Section 3 evaluates the spiking patterns, conducts error analysis, and examines the network behaviors of SC-IZ. Section 4 describes the hardware architecture of SC-IZ and compares it with existing Izhikevich hardware implementations. Finally, Section 5 concludes the paper.

2. Methodology for SC-IZ Hardware Implementation

2.1. Stochastic Computing

Approximate computing is a promising approach that offers a trade-off between accuracy and performance. Stochastic computing (SC) is a prominent method within the realm of approximate computing [41]. It involves performing computations using randomized bitstreams and has shown promise for accelerating neural networks. One of the key benefits of SC is its ability to enable multiplication and addition using single gates, leading to significant improvements in computation density [42]. In contrast to the conventional base-2 format, SC is error-robust, with the bit represented in SC being free of the bit position [43]. SC utilizes two common representations: unipolar and bipolar. In the unipolar representation, values range from 0 to 1, where the probability of encountering a 1 in the bitstream, denoted as $p_X$, encodes the actual value of a stochastic number X. For example, if a bitstream has the pattern 10110111, the value of $p_X$ is 6 divided by the length of the bitstream (8), which equals 6/8. In the bipolar representation, the range extends from −1 to 1. The probability is given by the formula $2p_X-1$ and encodes the actual value X. The bitstream 10110111 in the bipolar representation represents a value of 4/8.

Arithmetic operations in SC can be implemented using basic logic gates and multiplexers. Unipolar multiplication can be achieved with an AND gate as depicted in Figure 1a, while bipolar multiplication can be realized using an XNOR gate as shown in Figure 1b. Unipolar addition can be implemented using an OR gate with negatively correlated bitstreams [44] as illustrated in Figure 1c. Additionally, both unipolar- and bipolar-scaled addition can be accomplished using a multiplexer as demonstrated in Figure 1d. To convert binary numbers to bitstreams, a Stochastic Number Generator (SNG) unit is commonly employed [45]. This unit consists of a Linear-Feedback Shift Register (LFSR)-based Random Number Generator (RNG) and a comparator as shown in Figure 1e. In each clock cycle, a 1 is generated if the binary number (A) is greater than the number (R) generated by the Linear Feedback Shift Register (LFSR).

SC Finite-State Machines (FSMs) have been introduced as methods to perform various non-linear functions, such as exponential functions, Rectified Linear Unit (ReLU) functions, and hyperbolic tangent functions on stochastic bitstreams [46]. Furthermore, a stochastic integrator has been proposed to implement the accumulative function of the Euler method in an ODE solver [40]. Unlike conventional stochastic circuits that require long stochastic bitstreams for accurate results, the stochastic ODE solver offers estimates of the solution for each bit in the stochastic bitstream, resulting in notable reductions in latency and energy consumption [30,40]. The circuit diagram and symbol of the stochastic integrator are depicted in Figure 2a and Figure 2b, respectively.

A crucial component of the stochastic integrator is a $2^n$-state up/down counter. The counter’s value is encoded in a stochastic bitstream $S_{out}$, generated by a RNG and a comparator acting as a SNG. The $S_{out}$ bitstream can serve as feedback or act as an input for subsequent stochastic integrators. If it is not necessary for the specific application, the RNG unit and the comparator can be omitted from the hardware design, leading to reduced hardware costs. The input signals A and B are stochastic bitstreams that dictate the operations to be executed on the counter. These operations include increasing (INC), decreasing (DEC), or maintaining the counter’s current value. We denote the integer value stored in the counter as I. In the unipolar representation, the probability encoded by the output stochastic bitstream is $\frac{I}{2^n}$. At the i-th clock cycle, the two bits in the input streams A and B are denoted as $a_i$ and $b_i$, respectively. The functionality of the up/down counter is as follows:

$$I_{i+1}=\left\{\begin{array}{cccc}{I}_i+1& if& a_i=1,& b_i=0\\ I_i& if& a_i=b_i\\ I_i-1& if& a_i=0,& b_i=1\end{array}\right.$$

(1)

where input bit streams A and B only serve as the control signals for the counter.

For an ODE, $\frac{dy\left(t\right)}{dt}=p_a\left(t\right)-p_b\left(t\right)$, where $p_a\left(t\right)$ and $p_b\left(t\right)$ are probabilities encoded by the input sequences of the stochastic integrator at $t=\frac{i}{2^n}$. The estimated value of the function $y\left(t\right)$ at $t=\frac{k}{2^n}$ with a step size of $\frac{1}{2^n}$ can be obtained. The estimate is based on the normalized expected value of the up/down counter at the k-th clock cycle, assuming the same initial condition $y_0=s_0$. The estimation is given by [30]:

$$y\left(\frac{k}{2^n}\right)\approx s_0+\frac{1}{2^n}\sum _{i=0}^{k-1}(p_{a,i}-p_{b,i})$$

(2)

In Equation (2), $p_{a,i}$ and $p_{b,i}$ represent the probabilities of $p_a\left(t\right)$ and $p_a\left(t\right)$ at the i-th clock cycle, respectively. The stochastic integrator provides estimates for the solution of the ODEs. By employing the stochastic integrator, we can approximate the dynamics of the two ODE equations that govern the behavior of the Izhikevich neuron model.

2.2. Izhikevich Neuron

The Izhikevich neuron model [18,47] is a quadratic excitation model with recovery variables, known for its simplicity, computational efficiency, and ability to replicate various firing patterns observed in real biological neurons. The model is defined by two ordinary differential equations, along with an auxiliary reset equation, as follows:

$$\begin{array}{cc}\hfill C\frac{dv}{dt}& =k(v-v_r)(v-v_t)-u+I\hfill \end{array}$$

(3)

$$\begin{array}{cc}\hfill \frac{du}{dt}& =a(b(v-v_r)-u)\hfill \end{array}$$

(4)

$$\begin{array}{cc}\hfill ifv⩾v_{th}& \Rightarrow \left\{\begin{array}{c}v\leftarrow c\\ u\leftarrow u+d\end{array}\right.\hfill \end{array}$$

(5)

In these equations, v represents the membrane potential, u represents the recovery variable, and other parameters of the model are listed in

Table 1. Parametric description of the Izhikevich neuron model.

Parameters	Description
C	membrane capacitance (pF)
k	input resistance (pA·${\mathrm{mV}}^{-1}$)
$v_r$	resting membrane potential (mV)
$v_t$	instantaneous threshold potential (mV)
I	input current (pA)
a	time scale of the recovery variable (${\mathrm{ms}}^{-1}$)
b	sensitivity of the recovery variable (pA·${\mathrm{mV}}^{-1}$)
c	potential reset value (mV)
d	spike triggered adaptation (pA)
$v_{th}$	spike threshold potential (mV)

. When the membrane potential v reaches or exceeds a threshold $v_{th}$, the membrane potential resets to a value denoted as c and updates the recovery variable according to the increment specified by the parameter d. By adjusting the values of the parameters a, b, c, and d, different firing patterns observed in biological neurons (e.g., regular spiking (RS), intrinsically bursting (IB), chattering (CH), etc.) can be replicated [16,47].

2.3. Proposed Izhikevich Neuron Model

In this section, we present SC-IZ, a stochastic computing-based implementation of the Izhikevich neuron model. SC-IZ leverages the principles of stochastic computing to simulate the behavior of Izhikevich neurons. Stochastic computing is a computational paradigm that represents and manipulates data using probabilistic bitstreams [30,48]. SC operates with a data range from 0 to 1, using unipolar representation. Therefore, to align with the SC computing paradigm, it becomes necessary to normalize the original Izhikevich neuron model. We suppose that v is in the range $[mi{n}_v,ma{x}_v]$, and u is in the range $[mi{n}_u,ma{x}_u]$, and $L_v=ma{x}_v-mi{n}_v$, $L_u=ma{x}_u-mi{n}_u$. The mapping procedure is as follows:

$$\begin{array}{c}\hfill \left\{\begin{array}{cc}\tilde{v}& =\frac{v-mi{n}_v}{L_v}\\ \tilde{u}& =\frac{u-mi{n}_u}{L_u}\end{array}\right.\end{array}$$

(6)

where $\tilde{v}$ and $\tilde{u}$ represent the mapped membrane potential and mapped recovery variable, respectively. From Equations (3) and (6), we have the following equation:

$$\begin{array}{c}\hfill \frac{d\tilde{v}}{dt}=\frac{1}{L_v}\frac{dv}{dt}=a1·{\tilde{v}}^2+a2·\tilde{v}-a3·\tilde{u}+\tilde{I}\end{array}$$

(7)

where parameters $a1$, $a2$, $a3$, and $\tilde{I}$ are

$$\begin{array}{cc}\hfill a1& =\frac{k·L_v}{C}\hfill \end{array}$$

(8)

$$\begin{array}{cc}\hfill a2& =\frac{k·(2mi{n}_v-v_r-v_t)}{C}\hfill \end{array}$$

(9)

$$\begin{array}{cc}\hfill a3& =\frac{L_u}{C·L_v}\hfill \end{array}$$

(10)

$$\begin{array}{cc}\hfill \tilde{I}& =\frac{k·(mi{n}_v^2-v_r·mi{n}_v-v_t·mi{n}_v+v_r·v_t)+I-mi{n}_u}{C·L_v}\hfill \end{array}$$

(11)

From Equations (4) and (6), we have the following equation:

$$\begin{array}{c}\hfill \frac{d\tilde{u}}{dt}=\frac{1}{L_u}\frac{du}{dt}=b1·\tilde{v}-b2·\tilde{u}+b3\end{array}$$

(12)

where the parameters $b1$, $b2$, and $b3$ are

$$\begin{array}{cc}\hfill b1& =ab·\frac{L_v}{L_u}\hfill \end{array}$$

(13)

$$\begin{array}{cc}\hfill b2& =a\hfill \end{array}$$

(14)

$$\begin{array}{cc}\hfill b3& =\frac{a(b·mi{n}_v-b·v_r-mi{n}_u)}{L_u}\hfill \end{array}$$

(15)

Then, the normalized spike reset equation is denoted as

$$\begin{array}{c}\hfill \tilde{v}⩾{\tilde{v}}_{th}\Rightarrow \left\{\begin{array}{c}\tilde{v}\leftarrow \tilde{c}\\ \tilde{u}\leftarrow \tilde{u}+\tilde{d}\end{array}\right.\end{array}$$

(16)

The parameters ${\tilde{v}}_{th}$, $\tilde{c}$, and $\tilde{d}$ are denoted as

$$\begin{array}{c}\hfill \left\{\begin{array}{cc}{\tilde{v}}_{th}& =\frac{v_{th}-mi{n}_v}{L_v}\\ \tilde{c}& =\frac{c-mi{n}_v}{L_v}\\ \tilde{d}& =\frac{d}{L_u}\end{array}\right.\end{array}$$

(17)

Equations (7), (12) and (16) indicate that SC-IZ can be simulated with only two stochastic integrators.

3. Dynamical Behaviors and Error Analysis

In this section, we perform evaluations on the spiking patterns and network behaviors of the proposed SC-IZ model. Furthermore, we analyze the accuracy of SC-IZ by comparing it to the original Izhikevich neuron model. To quantify the discrepancies between the two models, we calculate various error metrics, including $ERRT$ (timing error between spike trains [15]), Root Mean Square Error ($RMSE$) [49], Normalized Root Mean Square Error ($NRMSE$) [50], and correlation.

Table 2. Original Izhikevich neuron parameters used to generate different spike patterns.

Spiking Pattern	Parameters
	$\mathit{C}$	$\mathit{k}$	${\mathit{v}}_{\mathit{r}}$	${\mathit{v}}_{\mathit{t}}$	$\mathit{a}$	$\mathit{b}$	$\mathit{c}$	$\mathit{d}$	$\mathit{v}\mathit{\_}\mathit{t}\mathit{h}$
Regular spiking (RS)	100	0.7	−60	−40	0.03	−2	−50	100	35
Intrinsically bursting (IB)	150	1.2	−75	−45	0.01	5	−56	130	50
Chattering (CH)	50	1.5	−60	−40	0.03	1	−40	150	25

lists the parameters of the original Izhikevich neuron model [47].

3.1. Dynamical Behaviors

Leveraging shifting operations to implement coefficients based on 2 offers a valuable technique for reducing hardware complexity. In our model, if $L_v=\frac{C}{k}$, where C and k are constants, the parameter $a1$ in Equation (7) is set to 1. Furthermore, if $b1$ is a coefficient based on 2, we can express $L_u$ as $L_u=\frac{a·b·L_v}{b1}$.

Table 3. SC-IZ neuron parameters used to generate different spike patterns.

Spiking Pattern	Parameters
	$\mathit{a}\mathbf{1}$	$\mathit{a}\mathbf{2}$	$\mathit{a}\mathbf{3}$	$\mathit{b}\mathbf{1}$	$\mathit{b}\mathbf{2}$	$\mathit{b}\mathbf{3}$	$\tilde{\mathit{c}}$	$\tilde{\mathit{d}}$	${\tilde{\mathit{v}}}_{\mathit{t}\mathit{h}}$
Regular spiking (RS)	1.000	−0.210	0.019	−(1/32)	(1/32)	0.000	0.105	0.412	0.700
Intrinsically bursting (IB)	1.000	−(1/4)	0.043	(1/128)	(1/64)	0.000	0.152	0.164	1.000
Chattering (CH)	4.000	−0.660	0.077	(1/128)	(1/32)	0.000	0.158	0.295	0.645

provides the parameters for different firing patterns of the proposed model, allowing for the characterization and analysis of various neuron behaviors. The simulation results, as depicted in Figure 3, demonstrate that the SC-IZ model can successfully reproduce a range of biological neuron behaviors. Furthermore, the SC-IZ model closely follows the behavior exhibited by the original Izhikevich model.

3.2. Network Behaviors

Raster plots, which are a common way to visualize the firing activity of neurons over time in network simulations, display the spikes generated by each neuron, providing insights into the temporal dynamics and synchrony within the network. Raster plots are crucial for understanding the emergent properties of neural networks [21,22]. In order to implement the SC-IZ model at the network scale, a simulation is conducted, using a network consisting of 1000 randomly connected neurons. The results of the simulation are illustrated in Figure 4, which displays raster plots representing the activity of the network. Upon examining the raster plots, it becomes apparent that the network behaviors of both the Izhikevich model and the SC-IZ model exhibit similar structures. The capacity of the neurons to organize themselves into assemblies is a crucial aspect in understanding the emergent behavior and information processing in neural networks [22]. The ability of the SC-IZ model to exhibit similar self-organizing capabilities as the original Izhikevich model further validates its effectiveness in capturing the essential dynamics of biological neurons, even within a network context.

3.3. Error Analysis

In accordance with [15], alterations made to the neuron model may lead to differences in spike timing, potentially causing a lag in the spike train of the modified model compared to the original. This timing variation between two spike trains, as defined in [15], is referred to as the timing error, denoted by $ERRT$. First, the two spike trains are synced, and the time to the next spike is used to compute the timing error for both the original Izhikevich model and the proposed model. This error can be given by

$$\begin{array}{cc}\hfill ERRT& =\frac{{\sum }_{i=1}^n\left|\frac{\Delta t_{sc}-\Delta t_o}{\Delta t_o}\right|}{n}\hfill \end{array}$$

(18)

$$\begin{array}{cc}\hfill \Delta t& =t_{s2}-t_{s1}\hfill \end{array}$$

(19)

where $\Delta t$ is the time error between the second spike time $t_{s2}$ and the first spike time $t_{s1}$.

In Equation (18), $\Delta t_{sc}$ represents the SC-IZ model, while $\Delta t_o$ represents the original Izhikevich model as depicted in Figure 5.

The $RMSE$ calculates the root mean square difference between the original Izhikevich model and our SC-IZ model, which is defined as

$$\begin{array}{c}\hfill RMSE=\sqrt{\frac{{\sum }_{i=1}^n{(v_{sc}-v_o)}^2}{n}}\end{array}$$

(20)

The $NRMSE$ is the $RMSE$ normalized by the range of the spike train values. This error can be given by

$$\begin{array}{c}\hfill NRMSE=\frac{RMSE}{v_{max}-v_{min}}\end{array}$$

(21)

$v_{sc}$ represents the membrane potential of the SC-IZ model after denormalization, while $v_o$ represents the membrane potential of the original Izhikevich model. The domain of the membrane potential $v_o$ is bounded by its maximum value $v_{max}$ and its lowest value $v_{min}$. Correlation measures the linear relationship between two neuron models. It provides insights into the similarity of spike patterns between the SC-IZ and original Izhikevich models. As shown in

Table 4. The errors between the proposed SC-IZ model and the Izhikevich model.

Spiking Pattern	ERRT	RMSE	NRMSE (%)	Correlation (%)
Regular spiking (RS)	0.024	1.168	0.818	99.770
Intrinsically bursting (IB)	0.013	2.262	1.809	99.267
Chattering (CH)	0.032	1.292	0.969	99.706
Average	0.023	1.574	1.199	99.581

, the errors between the proposed SC-IZ model and the original Izhikevich model are found to be very small within a specific range of membrane potential values, specifically within the range of [−100 mV, 50 mV]. Additionally, a high average correlation of 99.581% is observed between the two models within this range.

4. Hardware Implementation and Evaluation

4.1. Square Unit

The SC ODE solver provides estimates for the solution of the ODEs [40]. For example, the ODE as

$$\begin{array}{c}\hfill \frac{\mathrm{d}y}{\mathrm{d}t}=v^2\end{array}$$

(22)

Equation (2) provides an estimation for the solution using a stochastic integrator at the k-th clock cycle, where $y\left(\frac{k}{2^n}\right)\approx v_0+\frac{1}{2^n}{\sum }_{i=0}^{k-1}(p_{a,i}-p_{b,i})$. Here, $v_0$ represents the initial condition, and $p_{a,i}$ and $p_{b,i}$ represent the probabilities of v at the i-th clock cycle.

However, using correlated bitstreams in SC poses a significant design challenge and can lead to errors [51]. It is crucial to ensure that uncorrelated unipolar bitstreams achieve high accuracy in stochastic computation. This typically requires separate RNGs to generate independent random numbers for each bitstream. Unfortunately, this approach presents a significant challenge for large-scale SNNs. The necessity for numerous RNG units to maintain bitstream independence in these networks introduces substantial hardware demands, exacerbating both complexity and potential performance bottlenecks [38]. Considering the complexity of developing a true RNG, pseudo-random number generators like LFSR-based RNGs are frequently employed in SC. To reduce the size and energy consumption of the RNG circuitry, a proposed approach called LFSR sharing has been introduced. LFSR sharing involves utilizing an LFSR with multiple random number outputs. Ref. [52] recommends employing multiplexers to circularly shift the outputs of the LFSR. Ref. [53] proposes a hybrid RNG approach that combines an LFSR with a Halton sequence generator to diversify random number generation. While these methods utilize the LFSR module, they do require additional hardware resources to generate distinct random numbers. [30] suggests that rearranging the output of the LFSR can also yield different random numbers. Notably, permuting the LFSR outputs in reverse order can achieve lower cross-correlation without the need for extra hardware overhead. Consequently, we opt for the output rearrangement method to produce different random numbers. An LFSR with two random number outputs is employed in our SC-IZ model as depicted in Figure 6.

In our SC implementation, we have chosen a bit width of 8. However, for clarity purposes, we only display a 4-bit LFSR. Within our RNG unit, two variables are generated. The first variable corresponds to the LFSR outputs, denoted as $s_0$, $s_1$, $s_2$, and $s_3$, which are connected to $a_0$, $a_1$, $a_2$, and $a_3$, respectively. The second variable is generated by rearranging the LFSR outputs in reverse order, where $s_0$, $s_1$, $s_2$, and $s_3$ are connected to $b_3$, $b_2$, $b_1$, and $b_0$, respectively. This rearrangement in reverse order is known to maximize the deviation distance, resulting in low-correlated random bitstreams [30]. The utilization of different LFSR outputs ensures statistical independence between the inputs of the AND gate. This independence allows the AND gate to effectively function as a multiplier as depicted in Figure 6. By comparing the value v with two random numbers $R1$ and $R2$, different random bitstreams are generated for v. These random bitstreams serve as inputs to the AND gate, enabling the computation of $v^2$.

Figure 7 illustrates the comparison between the mathematical analysis results of Equation (22) and the results obtained from a SC implementation with different bit widths. When using 8-bit stochastic ODE solvers, the SC implementation provides relatively accurate solutions that closely match the analytical results. Zooming in on a narrow range reveals that the SC implementation with a bit width of 8 closely aligns with the analytical results, while the 4-bit implementation shows some differences. To evaluate the error between the SC implementation and the analytical results, the $RMSE$ and $NRMSE$ are analyzed. Figure 8 displays the error analysis results. The $NRMSE$ value is lower than $5\times {10}^{-3}$, indicating a very small error between the SC squaring operation and squaring using a normal multiplication operation.

4.2. The Overall Architecture of SC-IZ Model

The overall architecture of our SC-IZ model is shown in Figure 9. To optimize hardware resources, the architecture utilizes shared RNG modules. Additionally, the hardware implementation focuses on simple operations such as simple addition, AND operations, and shift operations.

To improve implementation efficiency, fixed-point arithmetic was utilized in our design. The architecture consists of three main components: the control unit (CTRL), the SC-IZ stochastic integrators, and the RNG unit. A control Finite State Machine (FSM), depicted in Figure 9, governs the behavior of the model, featuring three states: idle ($S0$), integrate ($S1$), and fire ($S2$). These states correspond to the activities of integrate-and-fire neurons within the system.

Each neuron starts in the idle state ($S0$) and transitions to the integrate state ($S1$) upon triggering, where initial values are assigned to variables v and u. In the integrate state ($S1$), the neuron performs membrane potential accumulation and adaptation accumulation using SC-IZ stochastic integrators. The neuron remains in the integrate state until the reset condition, defined by Equation (16), is met. Once the reset condition is satisfied, the neuron switches from the integrate state ($S1$) to the fire state ($S2$). The SC-IZ stochastic integrator within our architecture utilizes shared random numbers ($R1$ and $R2$) generated by the RNG unit. The sign of parameters $a1$, $a2$, $a3$, $b1$, and $b2$ determines whether the stochastic integral accumulator performs accumulation or decrement.

For multiplication operations, our hardware design avoids complex binary implementations and instead employs a simple AND gate. This approach, along with straightforward accumulation and shifting operations, significantly reduces complexity and resource requirements compared to traditional multiplication circuits. As a result, our design achieves a more compact and efficient hardware implementation. By minimizing hardware resource usage and simplifying circuitry, our architecture enables the realization of large-scale SNNs, opening up new possibilities for neural network applications.

4.3. Evaluation

The SC-IZ neuron model was implemented on the Xilinx Zynq-7000 SoC ZC702 FPGA, and the simulation and analysis were performed using Vivado 2018.3. The FPGA implementation of the proposed SC-IZ design successfully reproduces various spiking patterns as demonstrated in Figure 10. Additionally, the resource utilization of the FPGA implementation was evaluated.

Table 5. Comparison of FPGA resource utilization of the implemented SC-IZ model with the previously proposed Izhikevich model.

Approach	Slices	LUTs	FFs	MULTs	Max Frequency (MHz)	Platform
TCASI ’12 [20]	495	617	493	0	242	Virtex-II Pro XC2VP30
TBioCAS ’18 [21]	490	459	408	0	240	Virtex-II Pro XC2VP30
TBioCAS ’18 [21]	857	1268	551	4	28	Virtex-II Pro XC2VP30
TCASI ’19 [15]	NA	469	280	0	213	Spartan6 XC6SLX75
TCASII ’20 [54]	356	346	41	0	NA	Altera DE0 Cyclone III
TCASII ’21 [22]	96	309	274	0	224	Zynq-7000 ZC702
Ours	42	131	113	0	260	Zynq-7000 ZC702

presents a comprehensive comparison of hardware resources between the SC-IZ model and previously proposed Izhikevich neuron models. The SC-IZ model stands out with its remarkable achievements. It operates at a frequency of 260 MHz on the FPGA, demonstrating its high-speed processing capabilities. In terms of power consumption, the total on-chip power usage for the SC-IZ model is 117 mW, with dynamic power accounting for 12 mW and device static power for 105 mW. These power levels highlight the model’s energy efficiency and its suitability for low-power applications.

One of the significant advantages of the SC-IZ model is its minimal hardware resource requirements compared to previous works. Notably, when compared to the state-of-the-art work [22], the SC-IZ model showcases impressive advancements. It achieves substantial reductions in the utilization of hardware resources, specifically reducing the utilization of Slices, Look-Up Tables (LUTs), and Flip-Flops (FFs) by 56.25%, 57.61%, and 58.80%, respectively. Additionally, the SC-IZ model is able to operate at a higher frequency. The constrained hardware resources of FPGA platforms necessitate efficient utilization to realize large-scale SNN implementations. For instance, on the Xilinx Zynq-7000 SoC ZC702 platform, which provides 13,300 Slices, 53,200 LUTs, and 106,400 FFs, the efficient utilization of these resources is paramount. In the state-of-the-art work [22], each neuron commands a substantial portion of these resources, consuming 96 Slices, 309 LUTs, and 274 FFs. As a consequence, the platform can accommodate up to 138 neurons. In contrast, our proposed SC-IZ endeavors to optimize resource utilization, significantly diminishing the resource footprint required per neuron. Specifically, our approach achieves a marked reduction to 42 slices, 131 LUTs, and 113 FFs per neuron. This optimization facilitates our implementation’s ability to accommodate up to 316 neurons on the same Xilinx Zynq-7000 SoC ZC702 platform. This substantial reduction in resource consumption underscores the superior efficiency of our approach in enabling large-scale SNN deployments.

Figure 11 provides a breakdown of the hardware resources, revealing that a significant portion is consumed by the RNG unit. Therefore, optimizing the RNG unit becomes crucial. If each random bit stream is generated using independent LFSR-based RNG units, it would lead to higher hardware resource consumption. However, our approach employs the LFSR sharing technique, which reduces the number of independent LFSRs from five to just one. This reduction in the number of RNG units amounts to an 80% decrease. By utilizing simple operations such as addition, AND operations, and shift operations, along with the LFSR sharing approach, we successfully minimize the FPGA resources required.

5. Conclusions

SNNs built on simplistic LIF models exhibit shortcomings in both biological plausibility and performance. The Izhikevich model can exhibit firing patterns of various cortical neurons. Recent studies have demonstrated that SNNs developed using Izhikevich neuron models outperform SNNs based on LIF models, especially for image classification tasks [55,56]. In this work, we propose SC-IZ, a hardware-efficient and biologically plausible Izhikevich neuron model based on stochastic computing. The SC-IZ model accurately reproduces a wide range of biological neural behaviors and is well suited for large-scale SNN implementations. Simulation results have demonstrated that the SC-IZ model achieves high accuracy while maintaining efficiency. Compared to the state-of-the-art Izhikevich neuron model, SC-IZ offers lower hardware cost and higher operating frequency. While the SC-IZ model presents a compelling solution for efficient and scalable SNN implementations, continued research efforts are necessary to address its limitations and further optimize its performance for a broader range of applications. Investigating strategies for seamlessly integrating SC-IZ into real-world applications and platforms would be invaluable for its practical adoption and deployment.