Optimizing Confined Nitride Trap Layers for Improved Z-Interference in 3D NAND Flash Memory
Abstract
:1. Introduction
2. Simulation Set Up
3. Investigation of Z-Interference
4. Process Flow
5. Conclusions
Author Contributions
Funding
Data Availability Statement
Conflicts of Interest
References
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Program | Erase | Read | |
---|---|---|---|
Selected cell | 18.5 V~19 V | 0 V | −3 V~5 V |
Unselected cell | 9 V | 0 V | 5.5 V |
BL | 0 V | 22 V | 0.5 V |
DSL | 3.3 V | floating | 3.3 V |
SSL | 0 V | floating | 3.3 V |
SL | 2 V | 22 V | 0 V |
Time | 20 µs | 0.5 ms | - |
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Kim, Y.; Hong, S.K.; Park, J.K. Optimizing Confined Nitride Trap Layers for Improved Z-Interference in 3D NAND Flash Memory. Electronics 2024, 13, 1020. https://doi.org/10.3390/electronics13061020
Kim Y, Hong SK, Park JK. Optimizing Confined Nitride Trap Layers for Improved Z-Interference in 3D NAND Flash Memory. Electronics. 2024; 13(6):1020. https://doi.org/10.3390/electronics13061020
Chicago/Turabian StyleKim, Yeeun, Seul Ki Hong, and Jong Kyung Park. 2024. "Optimizing Confined Nitride Trap Layers for Improved Z-Interference in 3D NAND Flash Memory" Electronics 13, no. 6: 1020. https://doi.org/10.3390/electronics13061020
APA StyleKim, Y., Hong, S. K., & Park, J. K. (2024). Optimizing Confined Nitride Trap Layers for Improved Z-Interference in 3D NAND Flash Memory. Electronics, 13(6), 1020. https://doi.org/10.3390/electronics13061020