Energy-Efficient Partial LDPC Decoding for NAND Flash-Based Storage Systems

Round 1

Reviewer 1 Report

1. Stronger support for statement “... However, the LDPC decoding necessitates high computational complexity and frequent memory accesses, and consumes considerably higher energy than BCH and RS decoding processes" should be added. Reference would be helpful.

2. Can the proposed method be used in varying channel case? If yes, how to use it?

3. How to determine the selection among the set from H_2 to H_6?

4. Clarify why consider different codes in simulation and implementation.

Author Response

Thank you for reviewing the manuscript. The reply letter is enclosed. Please see the attached document.

Author Response File: Author Response.pdf

Reviewer 2 Report

The paper presents a comprehensive study on energy-efficient LDPC decoding for NAND flash-based storage systems. While the contributions are significant, further clarification, quantitative analysis, and discussion on certain aspects would enhance the paper's impact and completeness. Overall, the paper provides valuable insights into LDPC decoding techniques.

The following feedback is provided to enhance the clarity, coherence, and completeness of the manuscript:

1. The design of this article is aimed at LDPC decoding, involving the H-matrix. Therefore, it requires a basic introduction to some relevant background knowledge.

2. The decoding architecture section offers a clear description of the proposed architecture and its compatibility with existing LDPC decoding methods. However, additional explanation of shuffle and de-shuffle networks and discussion on potential trade-offs would improve completeness.

3. How do you know the number of maximally allowed iterations (MAI)? Please explain it.

4. What is Channel SNR? It is involved in the experiment, so explain it and introduce it.

5. Are there any direct experimental results of energy consumption? Not the comparison of memory accesses, or decoding latency.

6. What are the applicable scenarios of the algorithm and the scenarios in which it cannot be used? Analyze the scenarios.

7. While the simulation results demonstrate the effectiveness of the proposed algorithm, providing additional details on the simulation setup, such as channel models and error metrics used, would be better. 

Good

Author Response

Thank you for reviewing the manuscript. The reply letter is enclosed. Please see the attached document.

Author Response File: Author Response.pdf

Reviewer 3 Report

The submitted manuscript can be published after minor revision.

For the details see the attached file. 

Comments for author File: Comments.pdf

Author Response

Thank you for reviewing the manuscript. The reply letter is enclosed. Please see the attached document.

Author Response File: Author Response.pdf

Reviewer 4 Report

The author had devised a partial LDPC decoding method for NAND flash-based storage systems and achieved boosted efficiency of energy and reduced memory access. This paper provided detailed simulation explanations, agreeable theoretical analysis, and additional implementation evidence to support the author’s points. Besides, This cross validation in simulations and theoretical analysis makes the study in the paper in high transparency and a convincing way. The paper should be published.

The reviewer has the following comments:

1. The decoding latency of the proposed algorithm in Figure 4 seems to be a reversed version of reduction ratio in Figure 3, is normalized latency = 1 - Reduction ratio? Could the author please extend on this?

2. The paper tests on simulation results based on (149, 61, 6)  array LDPC code and performs theoretical analysis to achieve an agreeable number of iterations in Figure 2 and Figure 6. Can the authors explain how the theoretical values are calculated?

3. Why is the simulation and theoretical analysis using (149, 61, 6)  array LDPC code and implementation test on hardware architecture on (607, 60, 6) array? Could the author please explain if the different arrays should be mentioned in the conclusion and abstract?

Additionally, I wonder if the author can provide explanation and any insights regarding two questions:

1. The author underscores that at the beginning of the lifespan that the channel condition of NAND flash memory is reliable, it is inefficient to apply maximum effort decoding with fully parity-check matrix. How about the late stage of the NAND flash memory? 

2. It is good to see the implementation. Does the implementation cover the lifespan? Is it only tested at the beginning of the lifespace for NAND  flash memory when it is on good channel condition?

3. For the late stage of NAND flash memory. What is the advantage of the posed method compared to conventional LDPC decoding architecture? Any adjustment needed? How to adjust the method? How to detect the reliability and adjust the partial LDPC decoding method accordingly?

Author Response

Thank you for reviewing the manuscript. The reply letter is enclosed. Please see the attached document.

Author Response File: Author Response.pdf

Round 2

Reviewer 1 Report

The authros addressed my concerns. No more comments.