A New Technology-Adaptable Design for High-Endurance EEPROM

Abstract

High-endurance EEPROM is widely used for data storage with a data maintenance requirement when powered off. A major factor in EEPROM design is its lifetime cycle. However, state-of-the-art high-endurance designs are based on an IDM (integrated device manufacturer), which is very expensive and unfeasible for fabless design houses. In this article, we propose an innovative technology-adaptable high-endurance EEPROM design that is suitable for fabless design houses, with a much lower manufacturing cost. The key part of our design is a new charge pump with a precise voltage step increase control to reduce the high voltage damage to memory cells and to increase the EEPROM’s endurance. A temperature-insensitive clamping device is also used to alleviate the voltage fluctuation problem. Our method is adaptable to advanced fabrication processes and, thus, applicable for fabless designs with lower costs. Our test on a 0.13 µm commercial fabrication technology shows 4 million erase/write cycles, which is on a par with the state-of-the-art IDM supplier STMicroelectronics.

1. Introduction

Electrically erasable programmable read-only memory (EEPROM) is a type of non-volatile memory (NVM) that is widely used in re-writable non-volatile storage devices, such as communication devices, consumer electronic devices, healthcare devices, automotive devices, industrial control devices, and personal computers. However, the increased demand for EEPROM has generated stringent requirements on its reliability and data retention time duration.

Currently, mainstream EEPROM products are based on floating gate technology. With the rapid development in semiconductor process technology in the scaling down of size, the issue of reliability has become important. In particular, there is a big gap between fabless products with only 1 million erase/write cycles and the EEPROM products of the IDM supplier STMicroelectronics, which have about 4 million cycles. Although the 1 million erase/write cycle specification meets the demand of consumer electronic devices, it is far below the requirement for critical usage in medical, finance, and automotive electronics. Improving the reliability of EEPROM is an important challenge both technically and economically.

There are two directions in improving design reliability: high-reliability design [1,2,3,4] and write behavior control to prevent repeated memory access on the same memory cells [5] or enhance endurance in processing-in-memory architectures [6]. In practice, one could combine the two approaches. This research focuses on high-reliability design technology.

Reliability is a very important feature of the EEPROM design. The factors affecting EEPROM reliability include tunnel gate oxide, cell size, and high voltage generation from the charge pump design. Thicker gate oxide, larger cell size, or less overstress on charge pump voltage can improve the write/erase life cycles of EEPROM. Hashim et al. proposed to change tunnel gate oxide during manufacturing to improve the robustness of the EEPROM cell and reach 1 million life cycles [1]. However, this approach requires a manufacturing process tuning time of more than a year and costs USD 1 million. Yeargain J R et al. suggested using larger memory cells to improve endurance [2]. This approach can reach 1.5 million life cycles but incurs a high production cost. Similarly, Gregor et al. [3] proposed a rigorous testing method to identify longer life cycle chips, but this also has a high manufacturing cost. Rahman et al. proposed adjusting the sense amplifier to extend the read margin to increase cycling times [4]. The common drawback of these approaches is the high manufacturing cost, which is a limiting factor in commercial applications. Since cell damage is caused by excessive high voltage generated by the charge pump circuit, a charge pump circuit with less cell damage during write/erase operations is an ideal solution for reliability at low cost.

STMicroelectronics (ST), a leader in the global semiconductor field, produces high-endurance EEPROM products with up to 4 million life cycles and a data retention capability of 100 years [7]. However, the applicability of its design is restricted to its own fabrication process, with stringent process control and production management. This is a high-cost technology and is not applicable for fabless design houses. How to design high-endurance EEPROM with an open commercial fabrication process is a very important problem, both technically and economically.

In this article, we propose a high-endurance EEPROM design with a new charge pump design with precise voltage step increase control. We use a very accurate and slow voltage step increase to minimize the damage to the device. In addition, a temperature-insensitive voltage clamping device is applied to the output of our voltage generator to reduce the instability caused by temperature variation. Our design using SMIC 0.13 μm technology reaches 4 million life cycles. The major contribution of our approach is a fabrication technology-adaptable high-reliability EEPROM design suitable for fabless designs.

The rest of this article is organized as follows: Section 2 reviews the EEROM design as well as the charge pump circuit module and its impact on memory endurance. In Section 3, we present our charge pump circuit design with precise step control. Section 4 lays out our test results and discussion; this is followed by our conclusions in Section 5.

2. Charge Pump Circuit and Cell Endurance

As shown in Figure 1, the EEPROM circuit includes a control logic unit, a charge pump circuit, a memory cell array, and a read circuit. The data in and out are write/read data and address inputs. CLK is the external clock signal. The memory cell array is the main unit for data storage. Control logic, which includes address decoding logic, controls which memory cells are in operation. The charge pump circuit generates high-voltage VPP for erase/write operations. The read circuit is used to read out memory cell data.

Initially, instructions and data are received by the EEPROM chip. These inputs are decoded using control logic to identify the specific bit within the cell array targeted for operations. In the meantime, the charge pump circuit generates VPP for the write/erase process. During a read operation, data from the addressed memory cell are accessed and output through the data out interface, ensuring accurate processing and reliable functionality.

The erase/write mechanism of the EEPROM cell is Fowler–Nordheim (F-N) tunneling [8]. The electric field formula is shown in Equation (1). F-N tunneling is triggered when $E_{OX}$ is larger than 6 × 10⁸ V/cm [9], which means that Vox must be larger than 16 V in the SMIC 0.13 μm process, which is provided by Foundry PDK.

$$E_{OX}={\displaystyle \frac{V_{OX}}{T_{OX}}}$$

(1)

where

• $E_{OX}$: electric field on oxide;
• $V_{OX}$: voltage on oxide;
• $T_{OX}$: tunnel oxide thickness.

Figure 2 shows a cross-sectional diagram of an EEPROM cell. The select gate transistor functions as a switch. The floating gate transistor [10] is isolated with a thin tunnel oxide layer used to store charges. The control gate (CG) is used to control the flow of electrons into or out of the floating gate. The write/erase process applies a high voltage to the control gate to generate an electric field. During erasing, a high voltage is applied to the control gate, causing electrons to be injected into the floating gate, thereby increasing the cell threshold voltage (VT). Conversely, during writing, when the control gate is at 0 V and a high voltage is applied to the drain (VD), electrons are injected into the drain, lowering the cell threshold voltage (VT).

The process of filling or removing electrons from the floating gate is typically achieved through Fowler–Nordheim tunneling, which involves applying a high electric field across the thin oxide layer to move electrons onto or off the floating gate. This mechanism allows for the non-volatile storage of data, as the charge on the floating gate remains even when the power is removed.

The operation conditions are shown in

Table 1. EEPROM cell operation conditions.

Items	Select Gate	Control Gate	Drain	Source	Body
Erase	VPP	VPPE	GND	GND	GND
Write	VPP	GND	VPPW	Float	GND
Read	3.3 V	1.8 V	1.5 V	0	0

. VPP is the high voltage generated by the charge pump, VPPE is the high voltage applied to the control gate during the erase operation, and VPPW is the high voltage applied to the drain (bit line) during the write operation. GND refers to ground. The voltage is a typical value recommended by Foundry.

The electron tunneling through a stress barrier by a high electric field [8] needs to reach 16 V (VPP). The write and erase as well as read operations are explained below.

Write: the drain side establishes a high voltage, and electrons are pulled out of the floating gate when Vth is of a low cell VT (−1.0 V) and the cell is on with “0”.

Erase: electrons are injected into the floating gate from the drain region by applying a high voltage to the control gate and the select gate when Vth is of a high cell VT (4.5 V) and the cell is off with “1”.

Read: by controlling the voltage on the gate, the charge state of the floating gate is distinguished, and by comparing it with a reference current, the stored data, in the form of “0” or “1”, are retrieved.

A VPP of 16 V is generated by the charge pump circuit to perform erasing and writing operations. The continuous write/erase operations of EEPROM standard cells under high voltage VPP can cause device damage, thereby affecting the distribution of storage unit thresholds and the variation in windows.

Figure 3 shows the VT change during the erase/write process. The X-axis represents the number of write/erase cycles in the log scale. The Y-axis represents the cell threshold voltage (VT) during the erasing or writing [11]. After numerous erase/write cycles, the VT@ER of erase will gradually decrease, while the VT@PG of write will gradually increase. This is called the aging process. In the end, VT@ER will be close enough to VT@PG, so that the read circuit will not be able to distinguish them; thus, the memory cell will become unreadable.

As shown in Figure 4, there are three types of transistors in the cell array [12,13]. The transistor on the word line (WL) is a byte select gate, which serves as a selection switch. When a high voltage (VPP) is applied to the WL, transistors along the horizontal direction are subjected to this voltage, enabling write operations when the vertical bit line (BL) is activated. The select transistor operates as a switch, while the cell transistor manages charge storage and release. As summarized in Table 1, applying VPPW to the BL and VPP to the WL activates the select transistor, enabling the cell transistor to perform write operations. Conversely, when the control gate is at a high voltage (VPPE) and the drain is grounded (GND), the select transistor turns off, allowing the cell transistor to execute the erase process.

A VPP of 16 V is generated by the charge pump circuit for erase/write operations. VPPE performs the erase operation, while erase is a byte/page operation; VPPW performs the write operation, while write is a bit operation. It may create instantaneous peaks in the electric field and degrade the oxide layer. Due to its special design, the floating gate oxide can enhance the EEPROM cell’s reliability [1,7,14,15,16]. However, it needs special fabrication technology, which greatly increases the manufacturing cost. Despite this, it can normally reach only 1 million life cycles. Although STMicroelectronics can reach 4 million erase/write cycles, the technical details are unknown.

Another approach is to reduce the exposure time of high voltage to the memory cell and voltage perturbation. The existing charge pump design with the voltage curve shown in Figure 5a can only have 1 million life cycles. Since the cell damage is mostly caused by a fast voltage increase above 14.5 V, we designed a new voltage curve as shown in Figure 5b; before applying a high voltage of 14.5 V, we sped up the rising process to reduce the erase/write time. After that, we slowed down the rising rate to alleviate the memory cell damage, which we thought would not only reduce the cell damage but also slow down the aging process. Our test results confirm this approach: as shown in Figure 6, it can indeed help slow the aging process.

In the next section, we will present a novel charge pump design with accurate stepwise control to reduce the exposure time of high voltage, thus slowing down the aging process and increasing the endurance.

3. Charge Pump with Precise Step Control

Our charge pump circuit design is shown in Figure 7, which includes a pump core for voltage increase, a digital control ramp for slowing down when the voltage reaches 14.5 V, a pump clamp for when the voltage reaches 16 V, and a pump OSC for generating a four-phase feedback control clock. The pump core generates a stepwise voltage output at an increase in VCC of 1.8 V. When the output reaches 14.5 V, the digital control ramp will start to trigger and slow down the increase rate. When the voltage reaches above 16 V, the pump clamp will start to work and clamp the output to 16 V and generate a current to control the pump OSC, which again will affect the pump core.

In the following, we will explain the design details and working mechanism of the modules separately.

As shown in Figure 8, the pump OSC generates [9] four clock signals (CLK_a/b/c/d) [17,18], using logical operations, and then generates four-phase clock signals necessary to drive the pump core [19,20,21]. This design utilizes a current-starving architecture with a five-stage ring oscillator based on the charging and discharging of capacitors. Given that the current (I) and capacitance (C) are constants, the circuit operates at low frequency under high voltage and high frequency under low voltage, thereby minimizing the impact of voltage fluctuations on the pump’s ramp-up speed. As illustrated in Figure 8, an increase in the feedback signal’s iclamp current reduces the gate voltage at node n1, leading to a decrease in the current mirror’s output. This reduction in current slows the internal charging and discharging processes, which lowers the frequency, effectively reducing the charge pump’s power consumption.

The pump core consists of 18 pump cells driven by a four-phase clock [19,22], as shown in Figure 9. The complementary operation of the four-phase charge pump causes vs0 and vs1 to invert. When vs0 is higher than vs1, pm0 conducts; when vs1 is higher than vs0, pm1 conducts, allowing the complementary charging of VPUMP. Analysis of the circuit operation reveals that in one cycle of the charge pump, adjacent transistors conduct alternately with the changing clock signals, ensuring that the substrate voltage of all transistors remains high during any clock phase. As shown in Figure 9, this design eliminates the substrate bias effect, improving the transfer ratio and effectively suppressing reverse leakage current [13,23].

Our pump core design [24,25] is shown in Figure 10. It is an improvement based on the Dickson charge pump, designed to increase the gate voltage of the MOS transistor, reduce the impact on the threshold voltage (Vth), and enhance transfer efficiency. This structure is suitable for low-voltage charge pumps. The overall pump design uses a complementary up-and-down approach to improve pump efficiency and reduce the setup time.

Where the clock signals are generated by the pump OSC is shown in Figure 8, while the waveform of the four-phase clock signals [25,26,27] is shown in Figure 11. During time frame t1, both CLK and CLKB are at a high level. When the input is VCC, point n2 becomes high, and transistor NMS0 turns on, charging the voltage at point n1 to a high level. During time frame t2, CLKB becomes low, and BOOST remains low, so transistor NMS0 is turned off, and the voltage at point n2 remains unchanged. In t3, BOOST becomes high, while CLK remains high, and point n1 jumps to an even higher voltage. This causes transistor NM0 to open and charges point n2. During t4, BOOST becomes low to close NM0 and finish the voltage-boosting process.

After VPUMP exceeds 14.5 V, it becomes essential to moderate the ascent of the pump’s high voltage to safeguard the array’s endurance. This is achieved through the implementation of a digital control ramp circuit. Initially, tr0 is logic high level, and the other control signals, tr1 through tr5, are logic low level, clamping VPP via diode-connected MOS transistors until it reaches 14.5 V, as shown in Figure 12. Subsequently, tr1 to tr5 are sequentially logic high level at 30 µs intervals, as shown in Figure 13. Each activation incrementally elevates VPP by approximately 0.3 V. After six steps, the digital control ramp is disengaged, allowing VPP to continue its rise until the clamping diode enters reverse breakdown, effectively capping the voltage at 16 V. The advantage is that the number of tr stages can be selected and adjusted based on the characteristics of different processes/devices for control.

As shown in Figure 12, the system permits precise control over the VPP output by adjusting the combination of tr0~tr5 stages. The duration of digital control pulses is shown in Figure 13. This flexibility enables adaptation to varying device voltages by either modifying the number of tr stages or altering the diode voltage values. For instance, an increase of 0.3 V per device may necessitate adding one tr stage, while a decrease of 0.3 V would remove one. Alternatively, maintaining a constant number of tr stages while varying the diode voltage can also achieve the desired VPP output. This approach minimizes the potential physical damage to memory cells and high-voltage components, ensuring the reliability and longevity of the system. The advantages of this design include the selection of the number of trs and the choice of pulse width for a single tr. The number of tr stages can be selected based on the different devices chosen on various process platforms.

The pump-generated high voltage is clamped at 16 V using the reverse breakdown voltage of the clamping diode, preventing excessive voltage. When the clamping diode undergoes reverse breakdown, a negative feedback loop reduces the pump OSC frequency, effectively lowering the pump’s power consumption.

As shown in Figure 14, this design incorporates an enhanced high-voltage clamping diode, which is used to create a feedback current and increases the circuit’s robustness.

As shown in Figure 15, we used a new structure to ensure the output of high voltage, addressing the stability and consistency of the clamping voltage under different conditions. When VPUMP is below the breakdown voltage, the current through D1 and D2 is approximately zero, while the resulting minimal iclamp current and pump OSC maintain their initial frequency. Once VPUMP reaches the breakdown voltage, the current through D1 and D2 increases, leading to a gradual rise in iclamp current, which slows down the pump OSC and minimizes voltage overshoot and oscillations. The output voltage ripple is reduced by 35%. It effectively suppresses abnormal fluctuations, protects high-voltage devices from damage, and significantly increases the number of write/erase cycles.

In this article, we propose a clamping structure with precise voltage output. Through process adjustments, this precise voltage clamping reduces the concentration of PN junctions on both sides and generates avalanche breakdown voltage. The structure is mainly based on IMP (ionized metal plasma) doping, which decreases the concentration of the PN junctions. This makes the breakdown voltage less sensitive to temperature variations, thereby improving the stability and controllability of the high voltage.

Compared to the existing four-phase clock structure charge pump (2), the four-phase clock structure with a digital control ramp circuit gradually rises, precisely controlling the ramp-up speed and output voltage, hence reducing damage to the device. The output VPUMP is set to VPP through a clamping structure. The feedback clock reduces the operating frequency of the pump after reaching VPP, thereby resulting in lower overshoot and power consumption.

$${ V}_{out}=V_{in}+\left[{\displaystyle \frac{C}{C+Cs}}{V}_{clk}-V_{th}-{\displaystyle \frac{I_{out}}{\left(C+Cs\right)f_{clk}}}\right]\ast N$$

(2)

where

• $V_{out}$: output voltage;
• $V_{in}$: input voltage;
• $C$: capacitance used for storing and releasing electric charge;
• $Cs$: node parasitic capacitance;
• $V_{clk}:$ clock amplitude;
• $f_{clk}$: clock frequency;
• $I_{out}$: load current;
• $N$: number of pump stages.

In summary, our four-phase clock structure with a precise voltage step increase control circuit reduces voltage loss and improves power utilization efficiency at the cost of a less than 1% area increase. The actual efficiency gain depends on various factors, such as device selection, process conditions, load, and operating environment. Under a 1.8 V supply and 0.13 μm process, the digital control module manages the ramp-up speed, and the precise clamping structure stabilizes the VPUMP output within the 16 V to 16.4 V range. The feedback oscillator decreases the pump’s operating frequency after reaching VPP. This reduces VPP overshoot and ensures minimal output voltage ripple.

The basic idea of our design is that we use accurate ramp-up control of VPP to enable correct write/erase of memory cells and minimize cell damage caused by high voltage. For a given technology, one can choose a transistor with the smallest Vth to construct the digital control ramp circuit, as shown in Figure 12, to accurately control the increase in VPP from 14.5 V to 16 V through the number of transistor stages in the digital control ramp design. Theoretically speaking, the stage number is (VPP − 14.5 V)/Vth, and it can be adjusted through process silicon data. We choose a transistor with the smallest Vth so that the ramp-up control of VPP can be more accurate. Our test design on SMIC 0.13 μm technology shows a successful EEPROM design, with over 4 million write/erase cycles, which is the highest standard available in commercial products.

4. Experimental Results and Discussion

In this study, a new design was compared with an existing design [5,11,23] using a cross-experimental approach on SMIC 0.13 μm technology. We implemented our design with the same process condition on an MPW of DP3821 for a 64 kb EEPROM product. Our tests were performed in the following sequence:

Wafer acceptance test (WAT), chip probing yield (CP), packaging, endurance testing (cycling), and data retention test.

WAT (wafer acceptance test) and CP (chip probing) are essential for product verification beyond cycling and data retention testing. WAT ensures wafer quality and fabrication consistency through electrical and structural assessments, while CP evaluates chip functionality and yield as indicators of manufacturing stability and product quality. For this experiment, WAT and CP yield testing at 25 °C and 90 °C was performed at the SMIC Foundry.

VPP output was tested from −40 °C to +85 °C to evaluate performance under varying thermal conditions.

The lifetime numbers were tested based on JEDEC standards [JESD22-A117] as follows:

Cycling testing: An endurance test simulates repeated write/erase cycles using an HP81110A pulse generator to assess the EEPROM’s ability to maintain data integrity over extensive use [24,28,29]. The test flow is as follows:

Step 1: All sector erase, check 0 × FF.

Step 2: Write pattern, pattern check.

Step 3: Repeat Step1–Step2 till 1 M cycling.

Step 4: Performs 500 times of read/write checks after 1 million erase/write cycles.

The criterion consists of 128 samples with zero failures.

Data retention testing [26,30] is assessed through accelerated aging at 150 °C for 1000 h, followed by a readout to detect data loss or corruption. The test flow is as follows:

Step 1: All sector erase, check 0 × FF.

Step 2: Page program CKB, pattern check.

Step 3: Bake at 150 °C, pattern check at 168 h, 300 h, 500 h, 1000 h (DataVerify).

Step 4: After 1000 h of DataVerify, check function.

The criterion consists of 128 samples with zero failures.

We designed and taped out 64 kb EEPROM chips and tested 128 samples for 1000 h at 150 degrees Celsius to verify the effects of our design.

Table 2. WAT/CP performance of the existing and new design experiments.

DOE	Process Condition	The Same Process of 0.13 μm@Different Design		WAT SPEC (By Foundry)
	Split Condition	New Design	Existing Design
	Lot	DP3821.02	DP3821.01
	Wafer ID	#16	#10
CP Yield	25 °C	98.7%	98.2%
	90 °C	97.8%	96.5%	Low	High	Unit
Key WAT Parameter	TOX_N50_tow_60_10	90.4	90.5	88	93	A
	VT_CL1_ER_STD	4.5	4.51	3	6	V
	VT_CL1_PG_STD	−1.4	−1.4	−2	−0.2	V
	IDSAT_CL1_PG_STD	27.6	27.5	15	30.5	µA

lists the WAT and CP test results. The WAT parameters show consistent performance within target specifications under the same process. The CP results at 25 °C align with typical product behavior, while the new design achieves a higher yield of 97.8% at 90 °C, surpassing the 96.5% yield at 25 °C by over 1%. This improvement highlights the positive impact of the new clamp design’s VPP output consistency at high temperatures on yield.

This comparative Delt_BVD (Delt_Clamp_VPP out voltage) test on the wafer level for 64 kb density production used the new design and the existing design. The test results are shown in Figure 16. The fluctuation range of output high voltage is reduced by over 60% at high temperatures, whereas the fluctuation is reduced by about 40% at room temperature.

The test results are shown in

Table 3. VPP voltage values of existing and new clamps.

Clamp	Temperature	BVD@10 uA
Existing	−40 °C	15.7 V
	25 °C	16.3 V
	+85 °C	17.1 V
	Delt_BVD (−40 °C~+85 °C)	1.4 V
New	−40 °C	16 V
	25 °C	16.2 V
	+85 °C	16.4 V
	Delt_BVD (−40 °C~+85 °C)	0.4 V

. The existing structure’s clamp VPP output voltage varies from 15.7 V to 17.1 V across a temperature range of −40 °C to 85 °C, with a 1.4 V fluctuation. In contrast, the new clamp design limits the voltage fluctuation to 0.4 V, demonstrating improved consistency and stability in voltage output with temperature variation. This ensures reliable clamping voltage under varying conditions, effectively mitigating abnormal fluctuations, protecting high-voltage devices from damage, and enhancing the endurance of write/erase cycles.

As shown in

Table 4. Comparison for cycling data with 64 kb of EEPROM.

Cycling Data		Voltage	Cycling Numbers (Unit: Million Cycles)
			0.5	1	1.5	2	2.5	3	3.5	4	4.5	5.5
64 kb DP3821	#10 Existing	3.6 V	0/ 128	0/ 128	35/ 128	121/ 128	128/ 128	-	-	-	-	-
	#16 New	3.6 V	0/ 128	0/ 128	0/ 128	0/ 128	0/ 128	0/ 128	0/ 128	0/ 128	36/ 128	128/ 128

, following JESD22-A117, there are 128-piece units of the same batch with separate erase/write cycling tests at ambient temperature. The test results show that the existing 64 kb product design would only pass 1 million cycles; our proposed design passes 4 million. The results show that we successfully achieved a high-reliability EEPROM product with over 4 million erase/write cycles with an adaptable design.

Following the JEDEC standard, we tested 128 samples of 64 kb EEPROM products by utilizing the data retention test in an oven for 1000 h at 150 degrees Celsius. As shown in

Table 5. Comparison of data retention with 64 kb of EEPROM.

Density	Data Retention	Temp	Voltage	168 h	300 h	500 h	1K h
64 kb	DP3821.01 #10—Existing	150 °C	3.6 V	0/128	0/128	0/128	0/128
	DP3821.02 #16—New	150 °C	3.6 V	0/128	0/128	0/128	0/128

, the existing 64 kb EEPROM product passed the data retention test after 1 million write/erase cycles. Our proposed design passed the data retention test after 4 million write/erase cycles. Both designs achieved a zero-unit failure and are capable of retaining data for 100 years. However, as our design was subjected to a stricter standard of 4 million write/erase cycles, it demonstrates superior performance compared to existing designs.

5. Conclusions

In this article, we propose a high-endurance EEPROM design with a novel precisely controlled charge pump circuit. Our design is technology-adaptable and, thus, suitable for low-cost fabless design houses. Moreover, our design improves endurance without sacrificing write/erase performance. We achieved 4 million cycling times on normal SMIC 0.13 μm technology, which is on par with the state of the art and the more expensive IDM designs provided by ST. Furthermore, our design is applicable to various fabrication processes through minor design adjustments.