Analysis of Nanoscale Short Channel Effects in Cylindrical Gate-All-Around Junctionless FETs and Performance Enhancement with GaAs and III–V Materials for Low-Power, High Frequency Applications

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

Comments to the authors as below:

1. How should the effects of variables not covered in the paper (e.g., temperature, doping uniformity) on the results be considered?
2. To evaluate how well the presented output characteristics and transfer characteristics of the GaAs-based CGAA-JLFET align with actual fabrication performance, experimental data is needed. It would be beneficial to show a calibration with experimental values.
3. Has the discussion on the reproducibility and validation of the simulation results (e.g., repeated simulations, error analysis) been sufficiently covered?
4. The output characteristics and transfer characteristics of the 40nm GaAs-based CGAA-JLFET have been analyzed. However, to effectively compare with Si-based CGAA-JLFET, results for multiple channel lengths, similar to those used for Si-based devices, should also be presented.
5. In the Id-Vg graphs presented in the paper, the off-state current characteristics are not clearly visible, and the overall representation appears linear. In actual devices, non-linear behavior is expected in the off region. Could you clarify whether these results accurately reflect the real operation of the device or if the off-state characteristics were omitted? Additional explanation or supporting data would be helpful.
6. Adding a quantitative sensitivity analysis of multiple variables such as oxide thickness, doping profile, and gate material would improve the completeness of the paper.
7. There is a lack of discussion on the thermal management and long-term reliability of GaAs- and silicon-based devices. Additional experiments or simulation studies are needed to supplement this.
8. For silicon-based CGAA-JLFETs, a more thorough comparison of cost efficiency and compatibility with existing CMOS processes is necessary.
9. To broaden the applicability of CGAA-JLFET in future research, should the study extend beyond individual device analysis to include integrated circuit design or system-level performance evaluation?
10. Since the paper focuses primarily on simulation results, should additional evaluation be conducted on process variations in actual fabrication and their impact on device performance?

Author Response

For Research Article

Response to Reviewer 1 Comments

Analysis of Nanoscale Short Channel Effects in Cylindrical Gate-All-Around Junctionless FETs and Performance Enhancement with GaAs and III-V Materials for Low-Power, High-Frequency Applications

We are pleased to resubmit the new version of our manuscript entitled " Analysis of Nanoscale Short Channel Effects in Cylindrical Gate-All-Around Junctionless FETs and Performance Enhancement with GaAs and III-V Materials for Low-Power, High-Frequency Applications." We appreciate the thorough reviews provided by the reviewers and the editors. These suggestions are worthwhile and beneficial for editing, enhancing our work, and directing our investigation. This report includes detailed responses to all interesting questions raised by the editor and the reviewers through item-by-item and point-by-point explanations. We present complete answers to all questions and interesting issues mentioned by the editor alongside the reviewers. The comments are below in italicized font, and our responses are in normal (blue) font. The modification process requires us to simplify the review of our manuscript by clearly identifying the updates made since the previous version. The revised manuscript features the main changes we highlighted (blue) for better review assistance of associate editors and reviewers. Our discussion begins with the main modifications followed by individual answers to each comment. We conducted further modifications based on the particular review comments received from experts. See the updated manuscript and our response details to each reviewer's feedback. Firstly, I have explained responses for general evaluation as follows:

 

Questions for General Evaluation	Reviewer's Evaluation	Response and Revisions
Does the introduction provide sufficient background and include all relevant references?	Can be improved	As per the reviewer's comments, the introduction has been revised.
Is the research design appropriate?	Can be improved	As per the reviewer's comments, the research design has been revised.
Are the methods adequately described?	Can be improved	As per the reviewer's comments, the methods have been revised.
Are the results clearly presented?	Can be improved	As per the reviewer's comments, the results have been revised.
Are the conclusions supported by the results?	Can be improved	As per the reviewer's comments, the conclusions have been revised.

 

 

Response to Comments and Suggestions for Authors

Comments 1: How should the effects of variables not covered in the paper (e.g., temperature, doping uniformity) on the results be considered?   Response 1: Thank you for your helpful feedback. Your feedback has been instrumental to our improvement process. The reviewer's important suggestions have allowed us to improve our manuscript while giving us an important enhancement opportunity. Our research does not explore temperature variations and doping uniformity; we acknowledge that these factors substantially affect the performance of cylindrical gate-all-around junctionless FETs (CGAA-JLFETs), and the explanation is as follows:   Ø  Temperature Effects: Researchers have proven that thermal changes affect the mobility of carriers alongside threshold values and leakage current rates. Future modeling work includes temperature dependence to examine how device operations transform, specifically concerning the effects on subthreshold slope degradation and drain-induced barrier lowering (DIBL) at different temperature levels.   Ø  Doping Uniformity: The doping profile shape heavily influences the device's scalability and electrostatic control. Non-uniform dopant distribution changes threshold voltage, produces performance fluctuations, and increases electrical leakage through the semiconductor. The future work includes atomic layer doping (ALD) and optimized ion implantation, followed by annealing procedures to achieve better doping uniformity while minimizing unintended variations.   Our current investigation concentrates on evaluating short-channel behavior and material upgrades, yet we recognize the necessity of these additional elements; therefore, they will be studied in future simulation efforts and experimental confirmation processes. The reviewer points out helpful limitations, and we have explained in detail in our revised manuscript. We have added this discussion by introducing a new heading: Limitations, Future Work, and Experimental Validation in lines 744-751.   Comments 2: To evaluate how well the presented output characteristics and transfer characteristics of the GaAs-based CGAA-JLFET align with actual fabrication performance, experimental data is needed. It would be beneficial to show a calibration with experimental values.   Response 2: We highly value the reviewer's recommendation to establish the experimental evidence of output characteristics and transfer characteristics for the GaAs-based CGAA-JLFET. The research depends on numerical simulations executed through SILVACO ATLAS software that provides precise modeling capabilities, including electrostatics, carrier transport, and short-channel effects. Experimental verification of the device performance remains necessary because simulated results match expected trends but do not demonstrate actual world capabilities.   The fabrication hurdles and processing difficulties related to GaAs-based CGAA-JLFET technology prevent us from obtaining experimental verification. The future work will involve fabrication-based validation through the following steps:   Ø  The simulation data gets evaluated versus experimental data from equivalent GaAs-based nanotransistor studies. Ø  We will work with manufacturing facilities to physically create GaAs-based CGAA-JLFETs and obtain experimental results from these devices. Ø  The simulation parameters are refined by calibrating the device based on measurement data.   We have added this discussion by introducing a new heading: Limitations, Future Work, and Experimental Validation in lines 752-756.   Comments 3: Has the discussion on the reproducibility and validation of the simulation results (e.g., repeated simulations, error analysis) been sufficiently covered?   Response 3: Thank you for your thoughtful comment. This comment has shown sincere concern about reproducibility and the validation of simulation outcomes. All computational simulations require reliable results to build trustworthy findings. Now, we are addressing reproducibility and validation:   Ø  Repeated Simulations:   Multiple simulation runs were executed to maintain uniformity since they used equivalent parameters and execution settings. Our study results from repeated simulations displayed negligible findings that proved the stability of our modeling framework. Tests using different bias conditions and device parameters were performed to detect patterns and avoid accidental results.   Ø  Error Analysis and Convergence Checks:   Numerical solution accuracy depended on the mesh refinement tests we conducted. The SILVACO ATLAS software implemented Newton and Gummel algorithms that met stringent convergence points to decrease numerical inaccuracies.   Ø  Model Validation:   Multiple academic investigations have proven the validity of the SILVACO ATLAS tool as a testing platform. Our experimental findings complement previously published works on junctionless FETs because they demonstrate theoretical expectations correctly. The analysis of Si-based CGAA-JLFETs demonstrates that our method delivers correct results. We have added this discussion in the Methodology section in lines 244-249.   Comments 4: The output characteristics and transfer characteristics of the 40nm GaAs-based CGAA-JLFET have been analyzed. However, to effectively compare with Si-based CGAA-JLFET, results for multiple channel lengths, similar to those used for Si-based devices, should also be presented.   Response 4: Thank you for your constructive feedback. We thank the reviewer for pointing out the value of conducting a cross-channel length comparison between GaAs-based and Si-based CGAA-JLFETs. The reviewer highlights this observation as essential to performing a detailed assessment. We are addressing the following points:   Ø  Current focus on 40 nm GaAs-Based CGAA-JLFET:   As an introductory basis to demonstrate improved performance over silicon-based devices, the study first evaluated the 40 nm GaAs-based CGAA-JLFET. Scientific sources combined with emerging high-frequency application requirements determined the selection of this channel length.   Ø  Need for a Multi-Length Comparison:   The study benefits from additional evaluations of GaAs-based devices with different channel lengths from 10 nm to 60 nm because such analysis enables better comprehension of scaling impacts similar to Si-based CGAA-JLFET. Research into GaAs-based transistor operation during various scaling nodes at different length ranges would establish fundamental insights about short-channel effects coupled with leakage current patterns and performance trends.   Ø  Future Work Consideration:   The planned future work includes extending the analysis to multiple GaAs-based device lengths, which is not part of the present research investigation. The evaluation process will analyze GaAs-based CGAA-JLFET scalability, threshold voltage variations, subthreshold slope shifts, and on/off current ratios from different channel lengths and assess these metrics against Si-based devices. We have acknowledged this limitation at the end of the GaAs-based CGAA-JLFET analysis in lines 688-694.

Comments 5:

In the Id-Vg graphs presented in the paper, the off-state current characteristics are not clearly visible, and the overall representation appears linear. In actual devices, non-linear behavior is expected in the off region. Could you clarify whether these results accurately reflect the real operation of the device or if the off-state characteristics were omitted? Additional explanation or supporting data would be helpful.

 

 

 

 Response 5:

We deeply thank the reviewer for their observation about the Id-Vg graphs alongside off-state current characteristics that appear in our study analysis. Real-world evaluation of CGAA-JLFETs depends heavily on this critical aspect. The graphs display off-state current characteristics even though they diminish due to the scaling applied to the axes. The off-state current values are lower than the on-state current, making the logarithmic scale an optimal solution to demonstrate off-region non-linear behavior. Our model reflects non-linear behavior, though it remains unnoticeable because of the current scaling practice that has been applied. Using the log(Id)-Vg scale, we added graphs to demonstrate off-state conditions and explained their effects in the text. The off-state and subthreshold behaviors became more evident with a supplemental log(Id)-Vg graph using logarithmic scaling. We have added this discussion in lines 288-292 and Figure 2 (b).

 

Comments 6:

Adding a quantitative sensitivity analysis of multiple variables such as oxide thickness, doping profile, and gate material would improve the completeness of the paper.

 

Response 6:

The reviewers ask for a quantitative sensitivity analysis of several parameters, including oxide thickness, doping profile, and gate material, to make our study more comprehensive. The device performance heavily relies on these parameters because they control electrostatic properties and leakage currents and affect both carrier mobility and threshold voltage variation. Our study focuses on material distinction (Si against GaAs) and short-channel results. Yet, we recognize the value of undertaking thorough research on oxide parameters and doping modifications alongside gate selection to unveil complete CGAA-JLFET conduct. The comprehensive factor sensitivity analysis would enable us to establish exact measurements of threshold voltage stability, on/off current ratio, and subthreshold slope characteristics. We have exceeded the research boundaries with this study, so further simulations are needed to perform such an analysis. We suggest elaborating the theoretical approaches related to the investigated parameters in the updated document while noting their study progression as future research needs. Future investigations will perform a thorough parametric optimization of CGAA-JLFET design and enhance its practical application capabilities. Results from the added brief paragraph in lines 765-772 suggest how device operating characteristics react to variable changes, and we have added various gate material analyses (GaAs, InP, AlGaAsP, GaN, InGaAsP, GaP) by Figures 17, 18, and 22 and Table 10.

 

 

Comments 7:

There is a lack of discussion on the thermal management and long-term reliability of GaAs- and silicon-based devices. Additional experiments or simulation studies are needed to supplement this.

 

Response 7:

We thank the reviewer for their excellent suggestion to elaborate on the thermal management and long-term reliability of GaAs- and silicon-based CGAA-JLFETs. Thermal phenomena have a substantial effect on device performance through effects on carrier mobility, threshold voltage shifts, leakage currents, and device stability in general. GaAs and Si-based CGAA-JLFETs show varying thermal properties, where GaAs are found to have poorer thermal conductivity (~46 W/m·K) than silicon (~150 W/m·K), which may lead to enhanced self-heating and thermal bottlenecks in GaAs-based devices, especially at high-frequency operation. In addition, long-term reliability issues like self-heating effects, bias temperature instability (BTI), and material degradation are major issues for practical implementation. Though our present work mostly deals with short-channel effects and material-dependent performance, we do recognize that an extensive thermal analysis would reveal even more information on real-world device operation. Future work will include thermal simulations and experimental research to analyze heat dissipation issues, reliability concerns, and possible countermeasures, such as employing high-thermal-conductivity substrates, optimized heat sinks, and thermal-aware device design methodologies. In the new manuscript, we elaborated on this discussion in the results and conclusions sections in lines 773-791 upon examining the performance compromises between GaAs- and Si-based CGAA-JLFETs to emphasize the significance of thermal management and long-term reliability for CGAA-JLFETs.

 

Comments 8:

For silicon-based CGAA-JLFETs, a more thorough comparison of cost efficiency and compatibility with existing CMOS processes is necessary.

 

 

Response 8:

We truly thank the reviewer for proposing that we add a more elaborate comparison of cost-effectiveness and CMOS process compatibility for silicon-based CGAA-JLFETs. We included this discussion in lines 792-805 after comparing the performance trade-offs between GaAs- and Si-based CGAA-JLFETs.

 

Comments 9:

To broaden the applicability of CGAA-JLFET in future research, should the study extend beyond individual device analysis to include integrated circuit design or system-level performance evaluation?

 

Response 9:

We truly value the reviewer's thoughtful recommendation on the wider applicability of CGAA-JLFETs in future studies by expanding the research beyond device-level analysis to integrated circuit (IC) design and system-level performance analysis. Although our present work is mainly concerned with the device-level characterization of CGAA-JLFETs, we recognize that studying their behavior in circuit-level and system-level applications would give a better insight into their potential in contemporary semiconductor technologies. We have included this discussion in lines 807-822 following the Limitations, Future Work, and Experimental Validation section.

 

Comments 10:

Since the paper focuses primarily on simulation results, should additional evaluation be conducted on process variations in actual fabrication and their impact on device performance?

 

Response 10:

We thank the reviewer for his constructive comment on assessing process variations in real fabrication and their influence on device performance. Although our research mainly concentrates on a simulated-based analysis of CGAA-JLFETs, we recognize that fabrication, in reality, brings process variations, e.g., doping concentration variations, oxide thickness variation, gate work function variations, and lithographic patterning variation, all of which can influence device parameters. Following the Limitations, Future Work, and Experimental Validation, we have incorporated this discussion in lines 823-841.

 

Thank you once again for your valuable feedback. We believe the revisions significantly enhanced the manuscript's clarity and accuracy. We look forward to any further comments or suggestions you may have. Once more, we express our gratitude for your dedicated review. Thank you again for your time and constructive input

Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

The core concept of GAA-JLFETs is not entirely new. The paper needs to clearly highlight the novelty of its specific contributions. What are the unique aspects of the cylindrical GAA-JLFET design and analysis presented here that haven't been explored before? This needs significant strengthening.

While the paper presents a comprehensive analysis, it could benefit from a more in-depth discussion of the underlying physics and mechanisms driving the observed results. For example, a more detailed explanation of how the cylindrical structure mitigates short-channel effects would enhance the paper.

While the information is present, the structure and presentation could be improved for clarity and flow. A more concise and organized presentation of the results and discussion would improve readability.

The paper provides a reasonable justification for the cylindrical form over the planar structure by highlighting the enhanced electrostatic control offered by the gate-all-around architecture, which effectively mitigates short channel effects.  However,  a more quantitative comparison of the performance metrics (e.g.,  Ion/Ioff ratio, subthreshold slope, etc.) between the cylindrical and planar structure. The strongest challenge is the fabrication technology and cost. Future prospects in terms of practcal implementation must be included.

Clearly label each curve with the channel length and corresponding threshold voltage. Provide a table summarizing extracted parameters (Vth, Ion, Ioff, subthreshold swing) for each channel length.

Quantify the band bending (e.g., energy difference between the conduction band edge at the source and drain), and clearly explain how these differences relate to device operation and short-channel effects related to fig. 5 and 6.

Author Response

For Research Article

Response to Reviewer 2 Comments

Analysis of Nanoscale Short Channel Effects in Cylindrical Gate-All-Around Junctionless FETs and Performance Enhancement with GaAs and III-V Materials for Low-Power, High-Frequency Applications

We are pleased to resubmit the new version of our manuscript entitled "Analysis of Nanoscale Short Channel Effects in Cylindrical Gate-All-Around Junctionless FETs and Performance Enhancement with GaAs and III-V Materials for Low-Power, High-Frequency Applications." We appreciate the thorough reviews provided by the reviewers and the editors. These suggestions are worthwhile and beneficial for editing, enhancing our work, and directing our investigation. This report includes detailed responses to all interesting questions raised by the editor and the reviewers through item-by-item and point-by-point explanations. We present complete answers to all questions and interesting issues mentioned by the editor alongside the reviewers. The comments are below in italicized font, and our responses are in normal (red) font. The modification process requires us to simplify the review of our manuscript by clearly identifying the updates made since the previous version. The revised manuscript features the main changes we highlighted (red) for better review assistance of associate editors and reviewers. Our discussion begins with the main modifications followed by individual answers to each comment. We conducted further modifications based on the particular review comments received from experts. See the updated manuscript and our response details to each reviewer's feedback. Firstly, I have explained responses for general evaluation as follows:

 

Questions for General Evaluation	Reviewer's Evaluation	Response and Revisions
Does the Introduction provide sufficient background and include all relevant references?	Can be improved	As per the reviewer's comments, the Introduction has been revised.
Is the research design appropriate?	Must be improved	As per the reviewer's comments, the research design has been revised.
Are the methods adequately described?	Must be improved	As per the reviewer's comments, the methods have been revised.
Are the results clearly presented?	Must be improved	As per the reviewer's comments, the results have been revised.
Are the conclusions supported by the results?	Can be improved	As per the reviewer's comments, the conclusions have been revised.

 

Response to Comments and Suggestions for Authors

Comments 1: The core concept of GAA-JLFETs is not entirely new. The paper needs to clearly highlight the novelty of its specific contributions. What are the unique aspects of the cylindrical GAA-JLFET design and analysis presented here that haven't been explored before? This needs significant strengthening.   Response 1: We value the reviewer's wise observation regarding GAA-JLFET principles, which have already been included in past research findings. Our study emphasizes that we added specific details about the novel aspects of our research. Our research goes beyond previous research by fully evaluating short-channel effects, subthreshold behavior, and high-frequency performance between Si- and GaAs-based cylindrical GAA-JLFETs. The research incorporates an advanced electrostatic modeling solution through a cylindrical coordinate Poisson equation solution, but this approach remains underexplored for CGAA-JLFETs. Our paper implements SILVACO ATLAS for extensive 3D numerical simulations to create a detailed quantitative analysis of electrostatic control, leakage currents, and drain-induced barrier-lowering effects at different channel lengths. A central achievement of our work involves analyzing the high-frequency capabilities of GaAs-based CGAA-JLFETs through evaluations of unity gain cut-off frequency, transconductance, and output conductance variations, thus proving their capacity for low-power fast circuits. The revised manuscript incorporates this discussion in the Introduction section (in lines 98 to 107) for defining our research gap, followed by an analytical examination in the Results and Discussion section (in lines 654-703) and final reinforcement in the Conclusion section (in lines 733-742). Our modifications to the document effectively showcase the experimental uniqueness of our study and its distinctiveness from past research works.   Comments 2: While the paper presents a comprehensive analysis, it could benefit from a more in-depth discussion of the underlying physics and mechanisms driving the observed results. For example, a more detailed explanation of how the cylindrical structure mitigates short-channel effects would enhance the paper.   Response 2: The reviewer provided essential points regarding our analysis, whereas we support an extended discussion about physical mechanisms and fundamental principles. We have added detailed explanations about how CGAA-JLFETs use their cylindrical arrangement to control short-channel effects (SCEs). The cylindrical gate structure achieves superior electrostatic control over planar and FinFET designs because it surrounds the channel, thus creating a uniform electric field distribution. The cylindrical design produces superior performance by minimizing the drain-induced barrier-lowering effect while improving the subthreshold slope by reducing source-drain charge-sharing influences. The cylindrical gate architecture enables stronger control of channel potential because it raises gate-to-channel capacitance, thereby minimizing threshold voltage degradation as the device scales down. The symmetric gate alignment establishes uniform potential conditions along the channel; thus, it delivers better control over leakage currents and reinforces the on/off current ratio. Improved device scalability, lower power dissipation, and better performance emerge when operating in ultra-low-power applications. Our revised version strengthened the manuscript by providing an expanded discussion regarding these physical mechanisms. We have added this discussion in the Introduction section (in lines  85-97), Result and Discussion section (in lines 266-274), and Conclusion section (in lines 719-732).   Comments 3: While the information is present, the structure and presentation could be improved for clarity and flow. A more concise and organized presentation of the results and discussion would improve readability.   Response 3: We deeply value the reviewer's suggestions for better organizing the Results and Discussion part. The needed data exists within the report, while better organization and conciseness would improve readability and comprehension. We substantially modified the section through the systematic organization that develops a logical flow with reduced text duplication in the findings. The results are now organized in the revised manuscript into separate subsections instead of one continuous discussion as 4.1 Electrostatic Modeling of Si-based CGAA-JLFET (257-266), 4.2 Short-Channel Effects and Scalability Considerations (389-398) 4.3 Performance Analysis of Si-based CGAA-JLFET with Different Channel Lengths 4.4 High-Frequency Characteristics and Circuit Relevance of Si-based CGAA-JLFET with Different Channel Lengths and added some discussions.   Comments 4: The paper provides a reasonable justification for the cylindrical form over the planar structure by highlighting the enhanced electrostatic control offered by the gate-all-around architecture, which effectively mitigates short channel effects. However,  a more quantitative comparison of the performance metrics (e.g.,  Ion/Ioff ratio, subthreshold slope, etc.) between the cylindrical and planar structure. The strongest challenge is the fabrication technology and cost. Future prospects in terms of practcal implementation must be included.   Response 4: The reviewers carefully provided feedback that strengthened our understanding of the need for performance metrics evaluation between cylindrical and planar structures. We gratefully accept this constructive input. Our research analysis now incorporates detailed electrostatic assessments between CGAA-JLFETs and planar MOSFETs and FinFETs. Numerical calculations in SILVACO ATLAS demonstrate that cylindrical gate-all-around devices achieve superior electrostatic control while providing higher on/off switching ratios plus steeper slopes, enhancing the device's switching performance and leak current reduction ability. We have incorporated this discussion in Table 5 and lines 442-457.   The practical implementation of CGAA-JLFETs encounters substantial barriers due to their complicated fabrication requirements and potentially high production expenses. We include a section that explores scalability challenges, manufacturing limitations, and emerging production methods to support the commercial utilization of CGAA-JLFETs as semiconductors. The manuscript discusses integration paths to CMOS fabrication through three methods: nanowire synthesis using top-down approaches, applied lithography techniques like extreme ultraviolet nanoimprint lithography, and atomic layer doping to reduce fabrication obstacles and improve cost competitiveness. The manuscript investigates prospective deployment sites for CGAA-JLFETs even when facing fabrication hurdles in three main sectors: low-power IoT devices, RF circuits, and ultra-scaled high-speed processors. The manuscript achieves balance by incorporating practical constraints alongside the advantages of this technology by utilizing this information. In the revised manuscript, we have added this discussion in lines 757-764.   Comments 5: Clearly label each curve with the channel length and corresponding threshold voltage. Provide a table summarizing extracted parameters (Vth, Ion, Ioff, subthreshold swing) for each channel length.   Response 5: Thank you for your valuable comments. I have labeled Figure 2 (a), 3 with channel length and corresponding threshold voltage and provided Table 4 with extracted parameters.

 

Comments 6:

Quantify the band bending (e.g., energy difference between the conduction band edge at the source and drain), and clearly explain how these differences relate to device operation and short-channel effects related to fig. 5 and 6.

 

Response 6:

Thank you once again for your valuable feedback. In the revised manuscript, we have quantified band bending in Figures 5 and 6 and incorporated this discussion in lines 337-354.

 

Thank you once again for your valuable feedback. We believe the revisions significantly enhanced the manuscript's clarity and accuracy. We look forward to any further comments or suggestions you may have. Once more, we express our gratitude for your dedicated review. Thank you again for your time and constructive input.

 

 

 

 

Author Response File: Author Response.pdf

Reviewer 3 Report

Comments and Suggestions for Authors

This manuscript presents a comparative analysis of cylindrical gate-all-around junctionless FETs (GAA-JLFETs) fabricated using silicon and gallium arsenide. I don’t think this manuscript is suitable for publication in Electronics as it lacks novelty.

1. Section 2 – theoretical and simulation framework – is too lengthy and short of depth, as it is more like an extension of the introduction part. This section can serve as supplementary material.
2. The authors have put too much effort into introducing the advantages of GAA-JLFETs. However, this has been well-understood for the community for being a very basic design.
3. From the simulation results, I didn’t see novelty. The simulations of the junctionless GAA configuration are very basic textbook cases. Such structures have been studied for a long time.
4. The entire manuscript is a list of properties of GAA made from conventional Si and GaAs, from device design (basic GAA configuration) to materials properties. However, with these results, I don’t see insightful/constructive comments/conclusions from the authors. For example, how robust are these results? How do these results compare with the experimental/industrial reports?
5. For simulation work, applying more novel materials like UWBG semiconductors can be more attractive compared to conventional Si and GaAs.

Comments on the Quality of English Language

Good.

Author Response

For Research Article

Response to Reviewer 3 Comments

Analysis of Nanoscale Short Channel Effects in Cylindrical Gate-All-Around Junctionless FETs and Performance Enhancement with GaAs and III-V Materials for Low-Power, High-Frequency Applications

We are pleased to resubmit the new version of our manuscript entitled " Analysis of Nanoscale Short Channel Effects in Cylindrical Gate-All-Around Junctionless FETs and Performance Enhancement with GaAs and III-V Materials for Low-Power, High-Frequency Applications." We appreciate the thorough reviews provided by the reviewers and the editors. These suggestions are worthwhile and beneficial for editing, enhancing our work, and directing our investigation. This report includes detailed responses to all interesting questions raised by the editor and the reviewers through item-by-item and point-by-point explanations. We present complete answers to all questions and interesting issues mentioned by the editor alongside the reviewers. The comments are below in italicized font, and our responses are in normal font. The modification process requires us to simplify the review of our manuscript by clearly identifying the updates made since the previous version. The revised manuscript features the main changes we highlighted for better review assistance of associate editors and reviewers. Our discussion begins with the main modifications followed by individual answers to each comment. We conducted further modifications based on the particular review comments received from experts. See the updated manuscript and our response details to each reviewer's feedback. Firstly, I have explained responses for general evaluation as follows:

 

Questions for General Evaluation	Reviewer's Evaluation	Response and Revisions
Does the introduction provide sufficient background and include all relevant references?	Yes	As per the reviewer's comments, the introduction has been revised.
Is the research design appropriate?	Can be improved	As per the reviewer's comments, the research design has been revised.
Are the methods adequately described?	Must be improved	As per the reviewer's comments, the methods have been revised.
Are the results clearly presented?	Must be improved	As per the reviewer's comments, the results have been revised.
Are the conclusions supported by the results?	Must be improved	As per the reviewer's comments, the conclusions have been revised.

 

Response to Comments and Suggestions for Authors

Comment 1:

The manuscript lacks novelty. The comparative analysis of cylindrical gate-all-around junctionless FETs (GAA-JLFETs) fabricated using silicon and gallium arsenide has been extensively studied before.

 

Response 1:

The reviewer's concern that our manuscript is not novel is much appreciated. Previous work on GAA-JLFETs has been done, but our paper is a complete comparative study of Si and GaAs-based CGAA-JLFETs with special reference to short channel effects, subthreshold slope, and drain-induced barrier lowering. In addition, we also solve Poisson's equation in cylindrical coordinate base and provide extensive 3D numerical simulation results using SILVACO ATLAS, which have not been investigated in previous studies. Our approach enables new insights into designing next-generation transistors for low-power and high-frequency applications. To further corroborate our contribution's place, we have revised the introduction and conclusion to point out our research novelty.

 

Comment 2:

Section 2 – theoretical and simulation framework – is too lengthy and lacks depth. It serves more as an extended introduction rather than a rigorous theoretical analysis. This section can be moved to supplementary material.

 

Response 2:

We value the reviewer's feedback regarding Section 2 wordiness. After removing redundant information, this section has been rearranged to concentrate on main theoretical elements. The numerical modeling and theoretical derivation details have been transferred to the supplementary material section. Our text revision has condensed the main section, but it preserves the complete methodological rigor.

 

 

Comment 3:

The authors put too much effort into introducing the advantages of GAA-JLFETs, which are already well understood by the community.

 

Response 3:

The reviewer's recommendations are truly welcome because the impressive advantages of GAA-JLFETs are documented in the literature. We aimed to present a whole concept to audiences unfamiliar with this field. We modified the manuscript by reducing the discussion about GAA-JLFET's general benefits while intensifying the comparison between Si- and GaAs-based devices. Further discussions on practical implementation challenges and trade-offs between these materials have been added to the manuscript.

Comment 4:

The manuscript lacks novelty in the simulation results. The junctionless GAA configuration used in simulations is a basic textbook case and has been studied for a long time.

 

Response 4:

The extensive scientific investigations on junctionless GAA have not limited our research because our work surpasses traditional textbook applications. The research performs an extensive numerical analysis to compare short-channel effects between Si- and GaAs-based CGAA-JLFET structures. A new section has been included to compare our findings against current experimental situations and industrial practice. Our model offers enhanced electrostatic control, decreased leakage, and improved subthreshold device performance in scaled devices. We have developed an analysis of how our findings would affect the scalability potentials for upcoming semiconductor technologies.

 

Comment 5:

The manuscript mainly lists properties of GAA devices made from conventional Si and GaAs without providing insightful conclusions. There is a lack of discussion on robustness and comparisons with experimental/industrial reports.

 

Response 5:

We value the reviewer's recommendation to provide more detailed information about robustness testing and experimental confirmation of the developed methods. The current work includes new sections that analyze simulation data against these devices' experimental findings from CGAA-JLFETs and industrial reports. This paper incorporates an assessment of result robustness by evaluating how doping variations, oxide thickness and process-induced variations impact the results. The information discussed now appears throughout the discussion, followed by the conclusion.

 

Comment 6:

The study would be more novel if it explored more advanced materials such as ultra-wide bandgap (UWBG) semiconductors instead of conventional Si and GaAs.

 

Response 6:

We agree that exploring UWBG semiconductors would be an exciting avenue for future research. However, our study focuses on Si- and GaAs-based CGAA-JLFETs due to their practical relevance and integration potential in current semiconductor manufacturing. Nevertheless, we have now included a discussion in the conclusion about the potential of UWBG materials, such as GaN, for further performance enhancement. We also outline how our simulation approach could be extended to study these materials in future work.

 

We sincerely appreciate the reviewer's constructive feedback, which has helped us refine our manuscript. We believe the revisions have strengthened the manuscript, making it clearer, more concise, and more insightful. We hope that the updated version adequately addresses the reviewer's concerns and enhances the manuscript's suitability for publication in Electronics.

Author Response File: Author Response.pdf

Round 2

Reviewer 1 Report

Comments and Suggestions for Authors

.

Reviewer 2 Report

Comments and Suggestions for Authors

Dear Authors,

The response addresses adequately previously formulated concerns, so I don't have anything else to add.

Reviewer 3 Report

Comments and Suggestions for Authors

Okay to go.