High Step-Up Interleaved DC–DC Converter with Voltage-Lift Capacitor and Voltage Multiplier Cell

Abstract

In this article, a new high step-up interleaved DC–DC converter is presented for renewable energy systems. The converter circuit is based on the interleaved two-phase boost converter and integrates a voltage-lift capacitor and a voltage multiplier cell. A high voltage gain of the converter can be achieved with a reasonable duty ratio and the voltage stresses of semiconductor devices are reduced. Because of low voltage stress, the switches with low on-resistance and the diodes with low forward voltage drops can be adopted to minimize the conduction losses. Additionally, the switching losses are reduced because the switches are turned on under zero-current switching (ZCS) conditions. Due to the existence of leakage inductances of the coupled inductors, the diode reverse-recovery problem is alleviated. Moreover, the leakage energy is recycled and the voltage spikes during switch turn-off are avoided. The parallel input architecture and interleaved operation reduce the input current ripple. The operating principles, steady-state characteristics, and design considerations of the presented converter are proposed in detail. Furthermore, a closed-loop control is designed to maintain a well-regulated output voltage despite variations in input voltage and output load. A prototype converter with a rated 1000 W output power is realized for demonstration. Finally, experimental results show the converter effectiveness and verify the theoretical analysis.

1. Introduction

The impact of climate change is a major focus of global attention. Many countries have introduced declarations and actions to mitigate global warming [1]. The adoption of renewable energy sources, such as wind power, photovoltaic (PV) power, and fuel cells, is one of the primary strategies for development in many countries. A typical schematic diagram of a general renewable energy power system is presented in Figure 1. In general, a single-phase 220 V AC power system requires a high voltage DC bus of 380–400 V to meet the demands of a full-bridge inverter, while a half-bridge inverter requires a 760 V DC bus. However, the output voltage of individual PV panels or fuel cell stacks is typically low in residential power systems. Therefore, a high voltage gain DC–DC converter is necessary to provide the required DC bus voltage for the inverter [2,3]. Additionally, high step-up DC–DC converters are also required in applications such as DC microgrids [4] and energy conversion in electric vehicles [5].

There are two general types of high step-up DC–DC converters: isolated and non-isolated. Isolated converters can achieve high voltage gain by adjusting the transformer turns ratio, as seen in traditional flyback, forward, push–pull, and full-bridge DC–DC converters. However, a high turns ratio leads to high leakage inductance and significant voltage spikes, which increase copper losses, cause electromagnetic interference (EMI) problems, and reduce efficiency. In non-isolated converters, if all components are ideal, conventional boost converters and interleaved boost converters can theoretically achieve high static gain at very high duty ratios.

In practice, the voltage conversion ratio of a boost converter is limited when non-ideal components are considered. Additionally, the efficiency decreases significantly at a very high duty ratio [6]. Moreover, the voltage stress on the switch and diode is equal to the output voltage, which necessitates the use of MOSFETs with high on-resistance and diodes with high forward voltage drops, resulting in increased conduction losses. Therefore, minimizing voltage stress on the switch and diode is a critical factor in the design of high step-up DC–DC converters.

Numerous non-isolated DC–DC converter topologies have been presented to achieve high voltage gain and high efficiency in the literature. These converters utilize various voltage-boosting techniques, such as coupled inductors [7,8,9,10], voltage multiplier cells [11,12,13,14,15,16,17,18,19], switched capacitors/inductors [20,21,22], built-in transformers [23,24], and voltage lift/stack techniques [25,26,27], among others.

The presented high step-up DC–DC converter, which consists of an interleaved parallel input structure, a clamped circuit, and a voltage multiplier cell, is illustrated in Figure 2. It can be applied to the renewable energy power systems. The circuit configuration combines the conventional interleaved boost converter with a voltage-lift capacitor and a voltage multiplier cell to enhance the voltage conversion ratio and reduce the switch and diode voltage stresses. The voltage multiplier cell consists of the series secondary windings of the coupled inductors, two diodes, and two capacitors. The characteristics of the presented converter are as follows:

(1)

The voltage gain is determined by two parameters: the duty ratio and the turns ratio of the coupled inductor. A high voltage gain of the presented converter can be realized with a reasonable duty ratio.

(2)

MOSFETs with low R_DS(ON) can be adopted to reduce conduction losses because of low switch voltage stress. Additionally, the switches are turned on under zero-current switching (ZCS), which helps minimize switching losses.

(3)

Diodes with low forward voltage drops can be used to help cut down on conduction losses because of the lower voltage stress.

(4)

The leakage energy can be recycled to prevent voltage spikes during switch turn-off.

(5)

The parallel input architecture and interleaved operation help cut down on the current stress on each switch and decrease the input current ripple.

Based on these features, the suggested converter is well-suited for applications requiring high voltage gain and high efficiency. A prototype converter with 36 V input, 400 V output, and 1000 W output power rating has been implemented. Experimental verifications are presented to illustrate its performance.

2. Converter Circuit and Operating Principles

The new high step-up interleaved DC–DC converter presented in this paper is depicted in Figure 2, where $S_1$ and $S_2$ are the switches, $C_f$ is a voltage-lift capacitor, $C_1$ is a voltage-doubler capacitor, $C_2$ and $C_3$ are voltage-multiplier capacitors, $C_o$ is an output capacitor, $D_1$ and $D_2$ are clamped diodes, $D_3$ and $D_4$ are voltage-multiplier diodes, and $D_o$ is an output diode. There are two coupled inductors in the circuit. Each coupled inductor is modeled as a combination of magnetizing inductance and leakage inductance, and an ideal transformer. Its coupling references are denoted by the marks of “$•$” and “$\circ$”. $L_{m1}$ and $L_{m2}$ represent the magnetizing inductances; $L_{k1}$ and $L_{k2}$ denote the leakage inductances, and the turns ratio of the ideal transformer is defined by $n=N_{s1}/ N_{p1}=N_{s2}/ N_{p2}$. The primary windings, with $N_{p1}$ and $N_{p2}$ turns, serve as the filter inductors in the conventional interleaved boost converter. The secondary windings, with $N_{s1}$ and $N_{s2}$ turns, are connected in series within the voltage multiplier cell, which is added to increase the output voltage. The equivalent circuit of the presented converter is depicted in Figure 3. The switches operate with the same duty ratio greater than 0.5 and are interleaved with a 180° phase shift.

The key waveforms of the presented converter, operating in continuous conduction mode (CCM), are illustrated in Figure 4. There are eight operating stages within one switching period. The corresponding equivalent circuits for each stage are depicted in Figure 5a–h.

First stage [$t_0-t_1$]: Switch $S_1$ begins to turn on at $t_0$ and $S_2$ remains in the on-state, and the diodes $D_1$, $D_2$, and $D_o$ are reverse-biased as shown in Figure 5a. Due to the existence of leakage inductance $L_{k1}$ and its initial current $i_{Lk1}(t_0) = 0$, $S_1$ turns on at the ZCS condition. The leakage current $i_{Lk1}$ rises rapidly from its initial value of zero. The magnetizing energy stored in $L_{m1}$ is still transmitted to the secondary side of the coupled inductor in the voltage multiplier cell if $i_{Lk1}<i_{Lm1}$, which causes $D_3$ and $D_4$ to conduct. Thus, the capacitors $C_2$ and $C_3$ are charged. The currents $i_{D3}$ and $i_{D4}$ decrease and their falling rate is affected by the leakage inductances. The output capacitor $C_o$ provides the load power. The current through $L_{m1}$ is obtained as follows:

$$i_{Lm1}\left(t)=i_{Lk1}\right(t)+n\hspace{0.17em}[i_{D3}(t)+i_{D4}(t\left)\right]$$

(1)

This stage ends when the condition $i_{Lk1}=i_{Lm1}$ is satisfied. At that instant, the currents $i_{D3}$ and $i_{D4}$ decrease to zero. Thus, $D_3$ and $D_4$ naturally turn off at the ZCS condition.

Second stage [$t_1-t_2$]: At the start of this stage, both switches $S_1$ and $S_2$ are in the on-state, and all diodes are reverse-biased, as shown in Figure 5b. The magnetizing inductances and leakage inductances are charged by input voltage $V_{in}$. The currents $i_{Lk1}$ and $i_{Lk2}$ rise linearly with a positive slope. The output load receives energy from the output capacitor $C_o$. The currents through $L_{k1}$ and $L_{k2}$ are given by the following:

$$i_{Lk1}\left(t\right)=i_{Lk1}\left(t_1\right)+{\displaystyle \frac{V_{in}}{L_{m1}+L_{k1}}}\left(t-t_1\right)$$

(2)

$$i_{Lk2}\left(t\right)=i_{Lk2}\left(t_1\right)+{\displaystyle \frac{V_{in}}{L_{m2}+L_{k2}}}\left(t-t_1\right)$$

(3)

Third stage [$t_2-t_3$]: At $t=t_2$, switch $S_2$ is turned off, which causes diode $D_1$ to be in forward bias due to the continuity of the leakage current. $i_{Lk2}$ flows through $D_1$, $C_f$, and $S_1$. The drain-source voltage on $S_2$ is clamped at the capacitor voltage $V_{Cf}$. The current $i_{Lk2}$ decreases and the magnetizing energy stored in $L_{m2}$ begins to transmit to the secondary side of the coupled inductor, which causes diode $D_o$ to be in forward bias. At this stage, the series secondary windings, $C_1$, $C_2$, and $C_3$ charge the output load via $D_o$. This stage ends when $i_{Lk2}$ falls to zero and $D_1$ naturally turns off.

Fourth stage [$t_3-t_4$]: At $t=t_3$, the stored energy in the leakage inductance $L_{k2}$ is completely released as shown in Figure 5d. The magnetizing current $i_{Lm2}$ is completely reflected from the primary winding to the secondary winding of the ideal transformer. The switch current through $S_1$ is equal to the sum of the two magnetizing currents.

$$i_{S1}(t)=i_{Lm1}\left(t\right)+n{i}_{Ns1}\left(t\right)=i_{Lm1}\left(t\right)+n{i}_{Ns2}\left(t\right)=i_{Lm1}(t)+i_{Lm2}(t)$$

(4)

The operation of the voltage multiplier cell in this stage is similar to that of the previous stage. This stage ends when $S_2$ is turned on.

Fifth stage [$t_4-t_5$]: In this short interval, switch $S_2$ begins to turn on and $S_1$ remains in the on-state, and the diodes $D_1$, $D_2$, $D_3$, and $D_4$ are in the off-state, as shown in Figure 5e. Due to the existence of $L_{k2}$ and $i_{Lk2}(t_4) =0$, the switch $S_2$ turns on at the ZCS condition. The current $i_{Lk2}$ rises quickly from its initial condition of zero. The current $i_{Np2}$ drops, which leads to a decrease in current $i_{Do}$. The stored energy in $L_{m2}$ still transmits to the secondary side of the coupled inductor if $i_{Lk2}<i_{Lm2}$. The other circuit operation is the same as that of the fourth stage. When the current $i_{Lk2}$ increases to reach $i_{Lm2}$, the current through $D_o$ will fall to zero. Diode $D_o$ naturally turns off. In this stage, the following applies:

$$i_{Lm2}(t)=i_{Lk2}(t)+n{i}_{Do}(t)$$

(5)

Sixth stage [$t_5~t_6$]: At $t=t_5$, both switches $S_1$ and $S_2$ are in the on-state and all diodes are in the off-state, as shown in Figure 5f. The circuit operation is the same as that of the second stage. The stage ends when the turn-off gate signal is applied to switch $S_1$. The currents through $L_{k1}$ and $L_{k2}$ are given by the following:

$$i_{Lk1}\left(t\right)=i_{Lk1}\left(t_5\right)+{\displaystyle \frac{V_{in}}{L_{m1}+L_{k1}}}\left(t-t_5\right)$$

(6)

$$i_{Lk2}\left(t\right)=i_{Lk2}\left(t_5\right)+{\displaystyle \frac{V_{in}}{L_{m2}+L_{k2}}}\left(t-t_5\right)$$

(7)

Seventh stage [$t_6~t_7$]: At the start of this stage, switch $S_1$ is turned off. Due to the continuity of the leakage current $i_{Lk1}$, diode $D_2$ changes to be in forward bias. The drain-source voltage of switch $S_1$ is clamped at the voltage of $-V_{Cf}+V_{C1}$. At this stage, the input voltage $V_{in}$, the primary winding of coupled inductor, and the voltage-lift capacitor $C_f$ are in series to charge $C_1$ through $D_2$. The leakage current $i_{Lk1}$ decreases and the energy stored in $L_{m1}$ transmits to the secondary side of the coupled inductor, which causes $D_3$ and $D_4$ to turn on, and capacitors $C_2$ and $C_3$ are then charged. The output capacitor $C_o$ supplies the load power. This stage ends when $i_{Lk1}$ decreases to zero and $D_2$ automatically turns off.

Eighth stage [$t_7~t_8$]: At $t=t_7$, diode $D_2$ is turned off as shown in Figure 5h. The magnetizing current $i_{Lm1}$ is completely reflected from the primary winding to the secondary winding of the ideal transformer. The switch current through $S_2$ is equal to the sum of the two magnetizing currents.

$$i_{S2}(t)=i_{Lm1}(t)+i_{Lm2}(t)$$

(8)

The operation of the voltage multiplier cell in this stage is similar to that of the seventh stage. This stage ends and the next period starts when the turn-on gate signal is applied to switch $S_1$ at $t=t_8$.

3. Steady-State Analysis

To simplify the analysis, the stages with very short intervals, the first and fifth stages, are ignored and the following conditions are assumed:

(1)

All the semiconductors, including switches and diodes, are ideal.

(2)

All the capacitors are large enough to regard their voltages as constant.

(3)

The parameters of the two coupled inductors are assumed to be identical, including the magnetizing inductance, the leakage inductance, the turns ratios, and the coupling coefficient defined as $k=L_m/(L_m+L_k)$.

3.1. Voltage Gain Derivation

According to the operating principles, there are two main states for each magnetizing inductance. For the magnetizing inductance $L_{m2}$, one state is magnetized by the voltage $k{V}_{in}$, and the other state is demagnetized by the voltage $k(V_{in}-V_{Cf})$. By using the volt-second balance principle on $L_{m2}$, i.e., that the average voltage on $L_{m2}$ during a switching period is zero, this can be expressed as follows:

$${\displaystyle \frac{1}{T_s}}{\displaystyle {\int }_0^{T_s}{v}_{Lm2}} dt={\displaystyle \frac{1}{T_s}}\left({\displaystyle {\int }_0^{D{T}_s}k{V}_{in} dt}+{\displaystyle {\int }_{D{T}_s}^{T_s}k(V_{in}-V_{Cf}) dt}\right)=0$$

(9)

where $T_s$ is the switching period and D is the duty ratio. The voltage across the voltage-lift capacitor $C_f$ can be given by the following:

$$V_{Cf}={\displaystyle \frac{1}{1-D}}{V}_{in}$$

(10)

Similarly, using the volt-second balance principle on $L_{m1}$ results in the following:

$$-V_{Cf}+V_{C1}={\displaystyle \frac{1}{1-D}}{V}_{in}$$

(11)

Therefore, the voltage across the voltage-doubler capacitor $C_1$ can be expressed as follows:

$$V_{C1}={\displaystyle \frac{2}{1-D}}{V}_{in}$$

(12)

In the seventh stage, the voltages across each magnetizing inductance can be written as follows:

$$v_{Lm1}=k(V_{in}+V_{Cf}-V_{C1})={\displaystyle \frac{-kD}{1-D}}{V}_{in}$$

(13)

and

$$\hspace{0.33em}{v}_{Lm2}=k{V}_{in}$$

(14)

Thus, the secondary winding voltages of each coupled inductor can be expressed as $v_{Ns1}=n{v}_{Lm1}$ and $v_{Ns2}=n{v}_{Lm2}$. The capacitor voltages $V_{C2}$ and $V_{C3}$ can be derived by applying the Kirchhoff’s Voltage Law (KVL) to the two loops of the secondary windings, $C_2$ and $D_3$ as well as $C_3$ and $D_4$ in the voltage multiplier cell. The equation and result are given by the following:

$$V_{C2}=V_{C3}=v_{Ns2}-v_{Ns1}=nk{V}_{in}-n\hspace{0.17em}({\displaystyle \frac{-kD}{1-D}}{V}_{in})={\displaystyle \frac{nk}{1-D}}{V}_{in}$$

(15)

In the third stage, the voltages across each magnetizing inductance are given by the following:

$$v_{Lm1}=k{V}_{in}$$

(16)

and

$$v_{Lm2}=k(V_{in}-V_{Cf})$$

(17)

Therefore, the secondary winding voltages of each coupled inductor are expressed by $v_{Ns1}=n{v}_{Lm1}$ and $v_{Ns2}=n{v}_{Lm2}$. Based on Figure 5c, applying KVL to the loop of $C_1$, $C_2$, the secondary windings, and $C_3$ and $C_o$, the loop equation can be expressed as follows:

$$V_{C1}+V_{C2}-v_{Ns2}+v_{Ns1}+V_{C3}-V_o=0$$

(18)

Substituting the results of Equations (12) and (15)–(17) into Equation (18), the output voltage can be derived as follows:

$$V_o={\displaystyle \frac{3nk+2}{1-D}}{V}_{in}$$

(19)

The voltage gain plot under different coupling coefficients, k = 1, 0.95, 0.9, and turns ratio n = 1, is illustrated in Figure 6a. It can be observed that the coupling coefficient has only a minor influence on the voltage gain.

Due to the small value of the leakage inductance compared to the magnetizing inductance, if the leakage inductance is neglected (i.e., assuming the coupling coefficient $k=1$), the step-up voltage conversion ratio can be rewritten as follows:

$${\displaystyle \frac{V_o}{V_{in}}}={\displaystyle \frac{3n+2}{1-D}}$$

(20)

From Equation (20), it can be seen that there are two degrees of freedom in designing the voltage gain of the presented converter: the duty ratio D and the turns ratio n. Clearly, the presented converter can achieve a high voltage gain with a reasonable duty ratio by selecting an appropriate turns ratio. Figure 6b shows the voltage gain versus duty ratio for various turns ratio values. The voltage gain reaches 20 times when $n=2$ and $D=0.6$. Clearly, the duty ratio does not need to be very large to achieve a high voltage gain.

3.2. Voltage Stresses on Semiconductors

To simplify the voltage stress analysis, the small leakage inductance is neglected. The voltage stress on $S_1$ and $S_2$ can be obtained from the seventh stage and the third Stage, respectively.

$$V_{S1}=V_{C1}-V_{Cf}={\displaystyle \frac{1}{1-D}}{V}_{in}={\displaystyle \frac{1}{3n+2}}{V}_o$$

(21)

$$V_{S2}=V_{Cf}={\displaystyle \frac{1}{1-D}}{V}_{in}={\displaystyle \frac{1}{3n+2}}{V}_o$$

(22)

The switch voltage stress is only $1/(3n+2)$ of the output voltage. MOSFETs with small on-resistance can be employed to reduce conduction losses and costs. From Equations (21) and (22), it can be observed that the switch voltage stress decreases significantly as the turns ratio n increases.

Furthermore, the voltage stresses on the diodes $D_2$, $D_3$, and $D_4$ can be derived from the third stage as follows:

$$V_{D2}=V_{C1}-V_{Cf}={\displaystyle \frac{1}{1-D}}{V}_{in}={\displaystyle \frac{1}{3n+2}}{V}_o$$

(23)

$$V_{D3}=V_o-V_{C3}-V_{C1}={\displaystyle \frac{2n}{1-D}}{V}_{in}={\displaystyle \frac{2n}{3n+2}}{V}_o$$

(24)

$$V_{D4}=V_o-V_{C2}-V_{C1}={\displaystyle \frac{2n}{1-D}}{V}_{in}={\displaystyle \frac{2n}{3n+2}}{V}_o$$

(25)

The voltage stresses on the diodes $D_1$ and $D_o$ can be derived from the seventh stage.

$$V_{D1}=V_{C1}={\displaystyle \frac{2}{1-D}}{V}_{in}={\displaystyle \frac{2}{3n+2}}{V}_o$$

(26)

$$V_{Do}=V_{Co}-(V_{C1}+V_{C2})={\displaystyle \frac{2n}{1-D}}{V}_{in}={\displaystyle \frac{2n}{3n+2}}{V}_o$$

(27)

From Equations (23)–(27), it can be observed that the voltage stresses on the diodes are always lower than the output voltage. As a result, diodes with low forward voltage drops can be adopted to cut down on conduction losses and costs.

3.3. Key Performance Comparison

The comparison of the presented converter with other similar topologies [28,29,30,31,32,33] is shown in

Table 1. Comparisons of the presented converter with other similar topologies.

Converter	[28]	[29]	[30]	[31]	[32]	[33]	Presented Converter
Voltage gain	${\displaystyle \frac{2n+2}{1-D}}$	${\displaystyle \frac{2n+2}{1-D}}$	${\displaystyle \frac{3n+2}{1-D}}$	${\displaystyle \frac{2n+D+1}{1-D}}$	${\displaystyle \frac{2n+1-2nD}{1-D}}$	${\displaystyle \frac{2N+n+D+1}{1-D}}$	${\displaystyle \frac{3n+2}{1-D}}$
Voltage stress	${\displaystyle \frac{V_o}{2n+2}}$	${\displaystyle \frac{V_o}{2n+2}}$	${\displaystyle \frac{V_o}{3n+2}}$	${\displaystyle \frac{V_o}{2n+D+1}}$	${\displaystyle \frac{V_o}{2n+1-2nD}}$	${\displaystyle \frac{V_o}{2N+n+D+1}}$	${\displaystyle \frac{V_o}{3n+2}}$
Max. diode voltage stress	${\displaystyle \frac{V_o}{2}}$	${\displaystyle \frac{\left(2n+1\right)V_o}{2n+2}}$	${\displaystyle \frac{(2n+1)V_o}{3n+2}}$	${\displaystyle \frac{(n+1)V_o}{2n+D+1}}$	${\displaystyle \frac{n{V}_o}{2n+1-2nD}}$	${\displaystyle \frac{(2N+n+1)V_o}{2N+n+D+1}}$	${\displaystyle \frac{\left(2n+1\right)V_o}{3n+2}}$
No. of switches	2	2	2	2	2	2	2
No. of diodes	6	6	8	4	4	6	5
No. of capacitors	6	5	6	6	3	7	5
No. of cores	2	2	2	4	2	5	2
No. of windings	6	6	6	6	4	9	4
Voltage gain $n=N=1,\hspace{0.33em}D=0.6$	10	10	12.5	9	10.5	11	12.5

, where n represents the turns ratio of the coupled inductor and N represents the turns ratio of the built-in transformer. The competitors are the interleaved high step-up DC–DC converters with the coupled inductor-based voltage multiplier technique. The following observations can be made: The voltage gain of the presented converter and the converter in [30] is the highest, and the switch voltage stress is the lowest. It is seen that the presented converter has a smaller number of components than that in [30]. The maximum diode voltage stress of the presented converter is lower. Except for the converter in [32], the presented converter uses the fewest components. However, the voltage gain, switch voltage stress, and diode voltage stress in the converter [32] are inferior to those of the presented converter. As a result, considering performance in terms of voltage gain, switch and diode voltage stresses, and component count, the presented converter offers distinct advantages for applications.

4. Design Considerations

4.1. Coupled Inductor Design

The turns ratio of the coupled inductor is a key parameter, as it influences the converter voltage gain and the voltage stresses on the semiconductors. Based on Equation (20), if a suitable duty ratio is chosen, the turns ratio can be derived as follows:

$$n={\displaystyle \frac{\left(1-D\right)V_o}{3V_{in}}}-{\displaystyle \frac{2}{3}}$$

(28)

The magnetizing inductance can be designed by setting an acceptable current ripple and CCM operation. The following inequality must be satisfied for CCM operation:

$$I_{Lm}>{\displaystyle \frac{1}{2}}\Delta i_{Lm}$$

(29)

where $I_{Lm}$ is the average current of the magnetizing inductance and $\Delta i_{Lm}$ is the ripple current. The magnetizing inductance of the coupled inductor can be derived as follows:

$$L_m>{\displaystyle \frac{{(1-D)}^2{V}_o^{2}D}{{(3n+2)}^2{P}_o{f}_s}}$$

(30)

where $P_o$ is the output power and $f_s$ is the switching frequency.

4.2. Capacitor Design

The capacitors can be designed to suppress the voltage ripple in a reasonable range and serve as a DC voltage source. The capacitor voltages are written in Equations (10), (12), (15), and (19). If the voltage ripples on each capacitor are specified, the derived results of each capacitor are given by the following:

$$C_1={\displaystyle \frac{3n+2}{2R_o{f}_s(\Delta V_{C1}/V_{C1})}}$$

(31)

$$C_2={\displaystyle \frac{3n+2}{n{R}_o{f}_s(\Delta V_{C2}/V_{C2})}}$$

(32)

$$C_3={\displaystyle \frac{3n+2}{n{R}_o{f}_s(\Delta V_{C3}/V_{C3})}}$$

(33)

$$C_f={\displaystyle \frac{3n+2}{R_o{f}_s(\Delta V_{Cf}/V_{Cf})}}$$

(34)

The output capacitor can be chosen as follows:

$$C_o={\displaystyle \frac{D}{R_o{f}_s(\Delta V_{Co}/V_{Co})}}$$

(35)

5. Feedback Control System Design

A feedback control system is designed to maintain a well-regulated output voltage despite variations in input voltage and output load. The closed-loop control block diagram using the voltage-mode method is illustrated in Figure 7, where K is the sensing gain of output voltage, $P\left(s\right)$ is the duty ratio-to-output transfer function of the presented converter, $1/V_P$ is the transfer function of the pulse-width modulation (PWM) circuit with a sawtooth waveform of amplitude $V_P$, and $C\left(s\right)$ is the controller transfer function.

For the control system design methodology, the prototype converter is first established, then the Bode plot is measured on the plant and the transfer function is obtained by the curve fitting method. Finally, the controller is designed using the K-factor method [34]. The design specifications for the control system include a gain crossover frequency of 1 kHz and a phase margin of at least 45°.

In order to design the controller, the small-signal transfer function of the controlled plant needs to be derived. At the operating point of the prototype converter, the frequency response from the control signal ${\tilde{v}}_{ctrl}$ to the sensing output voltage signal $K{\tilde{v}}_o$ in the Figure 7 is measured using the frequency response analyzer NF FRA51602 (NF Corporation, Yokohama, Japan). The actual measured conditions for the prototype converter are as follows: input voltage 36 V, output voltage 400 V, and output power 500 W. The resulting Bode plot is illustrated in Figure 8. The curve-fitting method, using the MATLAB software (R2021a), is then applied to obtain the desired transfer function $G\left(s\right)$ from the control-to-sensing output, where the following applies:

$$G(s)={\displaystyle \frac{K{\tilde{v}}_o(s)}{{\tilde{v}}_{ctrl}(s)}}=K\cdot P(s)\cdot {\displaystyle \frac{1}{V_p}}$$

(36)

The resulting transfer function by the curve-fitting method is obtained as follows:

$$G\left(s\right)=1.236{\displaystyle \frac{\left(s+980\right)}{\left(s^2+1554s+1.232\times {10}^6\right)\times \left(s+700\right)}}$$

(37)

Figure 9 illustrates the Bode plots of the measured result (in red) together with the curve-fitting result $G\left(s\right)$ (in blue). Based on the plots, there is a good agreement between the curves up to the angular frequency of ${10}^4\hspace{0.17em}\mathrm{rad}/\mathrm{s}$. As a result, the small-signal transfer function $G\left(s\right)$ is suitable for use in controller design.

The K-factor method [34] is employed to design a Type III controller, which is widely designed in the feedback control for DC–DC converters. This controller can achieve a phase plot above zero degrees at certain frequencies, providing the necessary phase boost to ensure a reasonable phase margin around the gain crossover frequency.

The analog circuit of the Type III controller is depicted in Figure 10, where six passive components are required. Its transfer function is given by the following:

$${\displaystyle \frac{{\tilde{v}}_{ctrl}\left(s\right)}{K{\tilde{v}}_o(s)}}=-{\displaystyle \frac{R_1+R_3}{R_1{R}_3{C}_2}}{\displaystyle \frac{\left(s+\frac{1}{R_2{C}_1}\right)\left(s+\frac{1}{(R_1+R_3)C_3}\right)}{s\left(s+\frac{1}{R_2{C}_1{C}_2/(C_1+C_2)}\right)\left(s+\frac{1}{R_3{C}_3}\right)}}$$

(38)

Assuming $C_2\ll C_1$ and $R_3\ll R_1$, then a simplified transfer function can be derived as follows:

$${\displaystyle \frac{{\tilde{v}}_{ctrl}\left(s\right)}{K{\tilde{v}}_o(s)}}\approx -{\displaystyle \frac{1}{R_3{C}_2}}{\displaystyle \frac{\left(s+\frac{1}{R_2{C}_1}\right)\left(s+\frac{1}{R_1{C}_3}\right)}{s\left(s+\frac{1}{R_2{C}_2}\right)\left(s+\frac{1}{R_3{C}_3}\right)}}=\hspace{0.33em}-C(s)$$

(39)

The Type III controller features three poles and two zeros, with one pole at the origin. From a control perspective, it includes an integrator and two phase-leader networks. The integrator ensures zero steady-state error for a constant reference input. The phase leaders provide the required phase boost to achieve the desired phase margin, which is crucial for stability around the loop gain crossover frequency. Using the K-factor approach [34], the controller is given by the following:

$$C\left(s\right)=3.68\times {10}^6\times {\displaystyle \frac{(s+1176.47)(s+1347.71)}{s(s+2.57\times {10}^4)(s+2.38\times {10}^4)}}$$

(40)

The six component values in the realized Type III controller are as follows: $R_1=200 \mathrm{k}\Omega$, $R_2=1.7 \mathrm{M}\Omega$, $R_3=12 \mathrm{k}\Omega$, $C_1=0.5 \mathrm{nF}$, $C_2=24 \mathrm{pF}$, and $C_3=3.5 \mathrm{nF}$.

The Bode plots of plant $G\left(s\right)$, controller $C\left(s\right)$, and loop gain $T_{OL}\left(s) =C\right(s\left)G\right(s)$ are displayed together in Figure 11. It is evident and worth noting that the control system meets the specifications, with a gain crossover frequency of 1 kHz ($6.28\times {10}^3 \mathrm{rad}/\mathrm{s}$) and a phase margin of 50°, achieved through the well-designed controller.

6. Experimental Verifications

In order to verify the performance of the presented converter, a 1000 W laboratory prototype with input 36 V and output 400 V is implemented. The key parameters and components of the laboratory prototype are listed in

Table 2. Parameters and components of the prototype.

Components	Parameters
$\mathrm{Switching} \mathrm{frequency} f_s$	$50 \mathrm{kHz}$
Turns ratio of coupled inductor $n$	1
$\mathrm{Magnetizing} \mathrm{inductances} L_{m1}$$, \hspace{0.33em}{L}_{m2}$	$78 \mathsf{\mu }\mathrm{H}$
$\mathrm{Leakage} \mathrm{inductances} L_{k1}$$, \hspace{0.33em}{L}_{k2}$	$0.5 \mathsf{\mu }\mathrm{H}$
Voltage-lift $\mathrm{capacitors} C_f$	$100 \mathsf{\mu }\mathrm{F}$
Voltage-doubler $\mathrm{capacitor} C_1$	$82 \mathsf{\mu }\mathrm{F}$
Voltage-multiplier $\mathrm{capacitors}\hspace{0.33em}{C}_2$$, \hspace{0.33em}{C}_3$	$68 \mathsf{\mu }\mathrm{F}$
$\mathrm{Output} \mathrm{capacitor} C_o$	$100 \mathsf{\mu }\mathrm{F}$
$\mathrm{Switches} S_1$$, \hspace{0.33em}{S}_2$	FDP036N10A
$\mathrm{Diodes} \hspace{0.33em}{D}_o$$, D_1$$, D_3$$, D_4$	DSEC29-02A
$\mathrm{Diode} D_2$	V30120C

. A picture of the prototype converter with the experimental setup is presented in Figure 12. The experimental setup is composed of the prototype converter with a driving circuit and a controller, a switching mode power supply, and an electronic load. The power analyzer HIOKI 3390 (HIOKI E.E. Corporation, Nagano, Japan) is utilized to measure the efficiency of the implemented converter. The frequency response analyzer NF FRA51602 is utilized to measure the Bode plot of the plant.

A powered toroid core made of sendust material with an inductance coefficient of $A_L=281{ \mathrm{nH}/\mathrm{N}}^2$, model number CS467125, is chosen for the implementation of the coupled inductor. The primary number of turns and secondary number of turns are both selected as 16, giving a turns ratio of 1. Based on Equation (30), the magnetizing inductance is designed to operate in CCM when the output power is more than 200 W. The PWM IC KIA494 is used to implement the driving circuit and the designed controller in the closed-loop control system. The sensing gain of the output voltage in the control system is 0.01.

The circuit simulation software Is-Spice (ICAP/4 Rx: 8.8.10) is utilized to verify the converter performance. The simulation and experimental results under full-load condition (1000 W) are shown in Figure 13, Figure 14, Figure 15, Figure 16, Figure 17, Figure 18 and Figure 19.

Figure 13 shows the input voltage, output voltage, and gate signals. With the conditions of turns ratio n = 1, input voltage $V_{in}=$ 36 V, and output voltage $V_o=$ 400 V, the theoretical duty ratio calculated by Equation (20) is equal to 0.55. The simulation and experimental results of the duty ratio are 0.57 and 0.6, respectively. The main reason for this slight difference is the assumption that the semiconductor devices are ideal in the theoretical analysis. It is evident that the voltage gain is over 11 times without an extreme duty ratio.

Figure 14 presents the gate signals and the drain-to-source voltages of the switches $S_1$ and $S_2$. It can be seen that the switch voltage stress is electively clamped to around 80 V, which is one-fifth of the output voltage, in agreement with the theoretical analysis of Equations (21) and (22) with turns ratio n = 1 and output voltage 400 V. Hence, the low-voltage-rated MOSFETs with low on-resistance can be used to decrease the losses.

Figure 15 illustrates the voltages and currents across the clamped diodes. The voltage stress on the clamped diodes $D_1$ and $D_2$ is approximately 160 V and 80 V, respectively, which agrees with the mathematical analysis of Equations (26) and (23) with the conditions of turns ratio n = 1 and output voltage 400 V. Figure 16 shows the voltages and currents across the voltage-multiplier diodes. The voltage stress on the voltage-multiplier diodes $D_3$ and $D_4$ is around 160 V, which is only two-fifths of the output voltage, matching the theoretical analysis of Equations (24) and (25) with turns ratio n = 1 and output voltage 400 V. The voltage stresses on these diodes are significantly lower than the high output voltage. Therefore, diodes with low forward voltage drops can be adopted to decrease the conduction losses. Additionally, it is seen that there is almost no reversed recovery current, which alleviates the reverse recovery losses.

Figure 17 displays the input current and the leakage currents. Although the leakage current ripple is about 30 A, the input current ripple is only about 3 A due to the interleaving effect. Furthermore, the average leakage currents are nearly equal, which helps share the input current between the phases and reduce current stress on the components.

Figure 18 shows the capacitor voltages on $C_f$, $C_1$, $C_2$, and $C_3$. The capacitor voltages $V_{Cf}$, $V_{C2}$, and $V_{C3}$ are approximately 80 V, while the voltage $V_{C1}$ is around 160 V, which matches the calculated results from Equations (10), (12), and (15). The capacitors are designed and chosen to suppress the voltage ripple less than 1% of the DC value by Equations (31)–(35) without considering the capacitor ESR (equivalent series resistance). As can be seen, the voltage ripples are small.

Figure 19 shows the ZCS turn-on performance of the switches. It is evident that the switch currents $i_{ds1}$ and $i_{ds2}$ rise linearly from zero during the turn-on transition, which helps reduce the switching losses.

For checking the performance of the control system, Figure 20 shows the output voltage dynamic response as the input voltage varies between 36 V and 40 V, while Figure 20a,b show the measured results using the oscilloscope’s DC and AC modes, respectively. It is seen that the maximum voltage variation in the output voltage is about 6 V and the settling time is about 70 ms. The output voltage remains relatively insensitive to input voltage fluctuations. Furthermore, Figure 21 illustrates the output voltage dynamic response under the step load changes between half load (500 W) and full load (1000 W). It is evident that the output voltage variation is very small during both step-up and step-down load changes. The results demonstrate that the well-designed controller ensures excellent output voltage regulation performance for the control system.

Figure 22 shows the efficiency at different output power levels. The maximum efficiency of 95.69% at a 200 W light load and the efficiency of 92.0% at a 1000 W full load are measured for the prototype converter with a 36 V input and 400 V output conversion.

7. Conclusions

A new interleaved high step-up DC–DC converter utilizing a voltage-lift capacitor and voltage multiplier cell techniques is presented in this article. The presented converter offers several advantages such as high voltage gain, low switch voltage stress, low diode voltage stress, and low input current ripple. These features allow the use of MOSFETs with low on-state resistance and diodes with low forward voltage drops, thereby reducing conduction losses. The switches can be turned on under ZCS so that the switching losses are reduced. The operating principles and performance analysis are investigated in detail. A 1000 W prototype converter is implemented and tested, and experimental results are provided to validate both the converter performance and the theoretical analysis. The implemented prototype achieves a maximum efficiency of 95.69%. Additionally, a Type III controller circuit is designed for the feedback control system, and experimental results have shown the excellent output voltage regulation despite variations in input voltage and output load. Finally, the experimental verifications have demonstrated that the presented converter is an excellent candidate for high voltage gain and high efficiency conversion in the renewable energy applications.