Dual-Gate Metal-Oxide-Semiconductor Transistors: Nanoscale Channel Length Scaling and Performance Optimization

Abstract

Dual-gate metal-oxide-semiconductor transistors have attracted considerable interest due to their high threshold voltage control capability, higher drain current, and the ability to alleviate the impact of carrier surface scattering at the channel/dielectric interface. However, their applications in the monolithic integration of scaled devices encounter challenges stemming from the interaction between the pre-treated channel layer and its covering dielectric. Here, we demonstrate the successful realization of a scaled back-end-of-line (BEOL) compatible dual-gate indium–gallium–zinc oxide (IGZO) transistor with a channel length (L_ch) scaled down to 150 nm and a channel thickness (T_ch) of 4.2 nm. After precisely adjusting the metal ratio to In_0.24Ga_0.58Zn_0.18O and employing O₃ as an oxygen precursor for the deposition of Al₂O₃ as the top-gate dielectric layer, a high maximum current of 1.384 mA was attained under top-gate control, while a high current of 1.956 mA was achieved under bottom-gate control. Additionally, a high current on/off ratio (I_on/off > 10⁹) was achieved for the dual gate. Careful calculations reveal that the field-effective mobility (μ_eff) reaches 11.68 cm²V⁻¹s⁻¹ under top-gate control and 22.46 cm²V⁻¹s⁻¹ under bottom-gate control. We demonstrate excellent dual-gate low-voltage modulation performance, with a high current switch ratio of 3 × 10⁵ at L_ch = 300 nm and 2 × 10⁴ at L_ch = 150 nm achieved by only 1 V modulation voltage, accompanied by a normalized current variation higher than 10⁶. Overall, our devices show the remarkable electrical performance characteristics, highlighting their potential applications in high-performance electronic circuits.

1. Introduction

Compared to single-gate devices, dual-gate thin-film transistors (DG-TFTs) exhibit superior electrical performance and stability, despite the increased complexity of their fabrication processes. To maximize the electrical characteristics of dual-gate transistors, a variety of semiconductor materials have been employed as the semiconductor channel layer, including polycrystalline silicon [1], amorphous oxide semiconductors (AOSs) [2], 2D materials [3], organic materials [4], and others. Among these materials, AOSs, particularly In₂O₃ or doped In₂O₃, are favored in DG-TFTs due to their large-area and low-temperature deposition, high mobility, low off-state current, and low leakage current [5,6,7,8]. These characteristics have led to their widespread use in displays [9], optoelectronic systems [10], low-power devices [11], and 3D back-end line devices [12]. As a typical doped In₂O₃ semiconductor material, indium–gallium–zinc oxide (IGZO) demonstrates high field-effect mobility (>10 cm²V⁻¹s⁻¹) and low subthreshold swing (SS). These features make IGZO a vital component in active-matrix liquid-crystal displays (AMLCDs) and active-matrix light-emitting diodes (AMOLEDs).

To achieve lower regulation voltage and SS, while realizing high resolution and high integration in DG-TFTs, scaling down the device size has been considered a crucial strategy. This is especially significant to meet the requirements of low-power circuit design, low-light detection, and biological detection [13,14]. To attain high electrical performance in DG-TFTs, various methods have been explored for depositing the semiconductor layer, including plasma-enhanced chemical vapor deposition, magnetron sputtering, and atomic layer deposition (ALD). The relatively high thickness of the semiconductor layer (approximately tens of nanometers) deposited using the first two methods cannot meet the requirements of downsized DG-TFTs, which necessitate a thinner channel layer and its covering dielectric layer. ALD is a technique that enables the deposition of materials onto a substrate surface in the form of single atomic layers, allowing precise control of the thickness and uniformity of the deposited films. The unique characteristics of ALD enable the successful realization of ultra-thin semiconductor layers and high k dielectric layers (such as HfO₂, Al₂O₃, etc.) in DG-TFTs [15,16,17,18], which facilitates further device size scaling and high integration. However, the ALD process, especially for the top-gate dielectric, can induce abundant defects associated with chemically active substances at the gate dielectric/channel interface [19,20,21]. In dual-gate IGZO thin-film transistors (TFTs), these defects can profoundly affect key electrical characteristics, including off-current (I_off), on/off ratio (I_on/off) [22], SS [23], and threshold voltage (V_T) [23,24], thus impeding the advancement of downsized devices. Consequently, there is an urgent need to elucidate the interaction mechanism between the top-gate dielectric and the pre-treated IGZO layer. A comprehensive understanding of this interaction will guide strategies to suppress defect generation during the ALD process, thereby facilitating the development of ultra-thin dual-gate devices that meet the stringent requirements for low-regulation voltage and size scaling.

Here, we have successfully realized the nanoscale channel length DG-TFTs to elucidate the interaction mechanism between the top-gate dielectric and the IGZO layer, using ALD technology to precisely control the metal ratio of the IGZO semiconductor layer and the covering Al₂O₃ top-gate dielectric layer. The surface interface interactions between the semiconductor layer and its covering dielectric layer were clearly analyzed by comparing the device behavior influenced by different Al₂O₃ oxygen precursors (H₂O and O₃) and the effects of controlling the metal ratio under DC measurements. Based on the transfer characteristic curves, the optimal precursor for Al₂O₃ and the metal ratio of IGZO were successfully determined. According to these results, the downsized IGZO DG-TFTs with L_ch of 150 nm and T_ch of 4.2 nm have been successfully realized, which effectively suppresses the short channel effect. Additionally, the nanoscale channel length device exhibits a high capability for dual-gate modulation, achieving a high current switch ratio of >10⁵ at a 1 V gate voltage modulation. Overall, our work may serve as a guidance for designing and fabricating nanoscale channel length DG-TFTs in the future.

2. Methods

A heavily p-doped silicon wafer was employed as the bottom-gate substrate. To ensure a clean surface, the substrates were first subjected to a standard solvent cleaning process. Subsequently, a 9 nm thick HfO₂ layer was deposited as the bottom-gate dielectric via ALD at 250 °C, using Tetrakis(ethylmethylamino)hafnium (TEMAH) and ozone (O₃) as the Hf and O precursors, respectively. Next, the semiconductor active layer with tunable metal compositions was deposited by ALD at 250 °C. Trimethylindium (TMIn), trimethylgallium (TMGa), diethylzinc (DEZn), and O₃ were used as the precursors for In, Ga, Zn, and O, respectively. The TMIn precursor was maintained at 50 °C, while TMGa and DEZn were kept at room temperature. By precisely adjusting the sub-cycle ratios of In₂O₃, Ga₂O₃, and ZnO to 5:1:1, 5:2:1, and 5:1:3, while keeping the main cycle constant to 12 cycles to ensure the same cycles of In₂O₃ (60 cycles), the metal percentages of In, Ga, and Zn were accurately controlled.

After the deposition of the IGZO layer, the patterned IGZO layer was fabricated through a combination of photolithography and wet etching using concentrated hydrochloric acid. This was followed by a post-annealing step at 300 °C for 2 h in the air to optimize the performance of the device. Subsequently, the source/drain (S/D) electrodes, consisting of a 25 nm Ni/20 nm Au stack with varying L_ch, were patterned using electron beam lithography (EBL, EBPG 5000+, dose: 240 µC/cm²) with PMMA A4 as the e-beam resist (thickness: 200 nm; spin-coating: 4000 rpm). The S/D electrodes were then formed by thermal evaporation and a lift-off process. Next, a 12 nm thick Al₂O₃ layer was deposited by ALD at 200 °C, using trimethylaluminum (TMA) as the Al precursor and O₃/H₂O as the oxygen precursors. Following this, the gate electrode, consisting of a 35 nm Ni/15 nm Au stack, was patterned using photolithography, formed by thermal evaporation, and completed through a lift-off process. The entire fabrication process was concluded with a rapid thermal annealing (RTA) treatment at 300 °C for 5 min in a nitrogen (N₂) environment to mitigate the formation of vacancies and further enhance the device performance.

The thickness and root-mean-square surface roughness (R_q) of the semiconductor thin-film layers were meticulously measured using atomic force microscopy (AFM, Bruker Dimension Icon, Bruker Nano Inc., Santa Barbara, CA, USA). The chemical composition and chemical state of these films were scrutinized through X-ray photoelectron spectroscopy (XPS, Thermo Fisher ESCALAB 250Xi, Thermo Fisher Scientific, Waltham, MA, USA). The electrical characteristics of the IGZO TFTs were comprehensively assessed using a semiconductor parameter analyzer (Keysight B1500A, Agilent Technologies, Inc., Penang, Malaysia). The microstructure of the IGZO device was observed and documented as optical and scanning electron microscopy (SEM) images using light microscopy (LEICA DM2700P, Leica Microsystems CMS GmbH, Wetzlar, Germany) and field emission scanning electron microscopy (Wavetest SUPRA 60, Carl Zeiss Microscopy GmbH, Oberkochen, Germany).

3. Results

3.1. Structure Details and Morphology Characteristics

The proposed nanoscale channel length DG-TFTs were fabricated on a highly p-doped silicon wafer coated with a 9 nm thick HfO₂ layer (Figure 1a). A patterned IGZO thick layer was deposited on the substrate, functioning as the carrier transport channel. A pair of Ni/Au stack electrodes, separated by a nanoscale gap, were placed on the semiconductor layer. These electrodes were fabricated using EBL and high-vacuum deposition techniques, forming a back-gate device. To construct the DG-TFTs, an Al₂O₃ dielectric layer and a patterned top gate were then deposited on the semiconductor. The detailed fabrication progress is illustrated in Figure 1b (see the Section 2). To clearly visualize the morphology of the DG-TFTs, an optical microscope is employed, and the result is shown in Figure 1c. An enlarged SEM micrograph of a typical device reveals the morphology of the nanoscale gap electrodes, indicating that the minimum L_ch of 150 nm can be achieved using EBL. Figure 1e presents the micrograph of In_0.24Ga_0.58Zn_0.18O imaged by AFM. Notably, the height profile extracted along the step confirms that the IGZO thickness is as thin as 4.2 ± 0.1 nm.

3.2. Bottom-Gate IGZO Measurements

To investigate the impact of metal ratios in IGZO and the selection of precursors for the dielectric layer on device performance, a series of bottom-gate microscale TFTs with a channel width of 40 μm and L_ch of 5 μm were fabricated and characterized. Figure 2a–c display the transfer characteristic curves for three different metal ratios measured by XPS of IGZO before and after capping an Al₂O₃ layer of 12 nm thickness, using H₂O and O₃ as the oxygen precursors, namely In_0.54Ga_0.26Zn_0.20O, In_0.24Ga_0.58Zn_0.18O, and In_0.25Ga_0.26Zn_0.49O. The thickness of the bare channel layer is 3.2 ± 0.1 nm, 4.2 ± 0.1 nm, and 4.3 ± 0.1 nm, respectively (Figure S1). As for the bare devices, the results indicate that the electrical performances are relatively insensitive to the variations in the metal ratio. However, after covering Al₂O₃ using H₂O as the oxygen precursor, the measured transfer characteristic curves reveal a negative shift in the V_T, particularly for In_0.54Ga_0.26Zn_0.20O, which has a higher ratio of In (depicted by green lines in Figure 2a–c). In comparison, when Al₂O₃ was deposited using O₃ as the oxygen precursor, the transfer characteristic curves demonstrate a significant improvement in the negative shift behavior for all three distinct IGZO metal ratios (depicted by the red lines in Figure 2a–c). As shown in Figure S2, the results reveal that the devices exhibit significantly similar characteristics compared to the non-ALD processed devices after RTA at 300 °C in N₂ for 5 min.

The result of top-gate measurement for In_0.24Ga_0.58Zn_0.18O using O₃ as the oxygen precursor before and after RTA is shown in Figure S4. The SS and $C_{ox}$ is 198 mv/dec and ~3.81 × 10⁻⁷ F·cm⁻² before RTA and 108 mv/dec and ~4.07 × 10⁻⁷ F·cm⁻² after RTA. The trap state density ($N_{it}$) at the channel and gate dielectric interface can be estimated by the SS value using the following relationship [25]:

$$N_{it}=({\displaystyle \frac{SS}{ln10}}{\displaystyle \frac{q}{k_{B}T}}-1){\displaystyle \frac{C_{ox}}{q}}$$

(1)

where $k_B$ is the Boltzmann constant, $T$ is the absolute temperature, $q$ is the elementary electron charge, and $C_{ox}$ is the capacitance per unit area of the gate dielectric. The calculated $N_{it}$ for the top-gate device is 5.53 × 10¹² eV⁻¹cm⁻² before RTA and 2.07 × 10¹² eV⁻¹cm⁻². After RTA treatment, the $N_{it}$ can be effectively decreased.

We can elucidate the physical reasons underlying the observed phenomena. First, residual hydrogen from the H₂O precursor can induce hydrogen doping in the semiconductor layer. Second, the residual trimethylaluminum (TMA) precursor may strip chemisorbed oxygen or hydroxyl (-OH) groups from the oxide channel, resulting in the generation of oxygen vacancies (Vo) [26,27,28,29]. Third, during the ALD process in Al₂O₃ deposition, chemical reactions may occur at the interface between aluminum (Al) and IGZO, leading to the formation of numerous defects, such as metal interstitials (Mi) and Vo [27,30]. All these doping effects and defects can increase the electron density in the channel, thereby influencing the switching characteristics of the transistors. The comparison of the two precursors indicates that O₃ can effectively passivate the pre-treated IGZO surface, reducing the formation of vacancies and reintroducing -OH groups into the channel, thereby suppressing the interfacial reactions that lead to defect formation (further analysis and validation can be seen in Figure 3). Notably, increasing the ratio of Ga is found to be more effective in suppressing the negative shift than increasing the ratio of In and Zn. This can be attributed to the high ionic potential of Ga³⁺, which allows it to form stronger bonds with oxygen ions [31]. The Ga-O bond dissociation energy is higher than that of Zn-O, enabling Ga to more effectively inhibit the formation of oxygen vacancies and reduce the concentration of free electrons in the channel. Based on the data presented in Figure 2a–c and Figure S3 and the comprehensive analysis of electrical characteristics in Table S1, we ultimately selected In_0.24Ga_0.58Zn_0.18O with the sub-cycle of 5:2:1, O₃ as the oxygen precursor in Al₂O₃ deposition, and RTA for the fabrication of scaled dual-gate IGZO transistors. As shown in Figure 2d, when employing the above process, the transfer characteristic curves of the device exhibit the similar V_T for L_ch larger than 400 nm. When scaling down L_ch from 400 nm to 150 nm, the negative shift behavior and switching characteristics remain well-preserved with I_on/off > 10⁹, indicating that the short channel effect can be effectively suppressed.

To further analyze and validate the influence of the precursors in the ALD process, we compared the chemical states using XPS among bare IGZO with the metal ratio of In–Ga–Zn = 0.24:0.58:0.18, IGZO covered with Al₂O₃ using O₃ as the precursor (Al₂O₃ -O₃), and IGZO covered with Al₂O₃ using H₂O as the precursor (Al₂O₃ -H₂O). As shown in Figure 3a,b, the In 3d and Ga 3d peaks of Al₂O₃ -O₃ capped IGZO exhibit notable shifts toward lower binding energies by 0.1 eV and 0.13 eV, respectively, compared to the bare IGZO sample. In contrast, the corresponding peaks for the Al₂O₃-H₂O capped IGZO show more pronounced shifts of 0.25 eV and 0.2 eV, respectively. These reduced binding energies are attributed to the Mi defects or Vo defects on the IGZO surface, as well as the residual reaction products that may form during the Al₂O₃ deposition process. These defects and reaction products can alter the local electronic environment, thereby influencing the binding energies of the In and Ga. When O₃ is used as the oxygen precursor for the deposition of the Al₂O₃ layer, the magnitude of the peak shift is less than that using H₂O. As shown in Figure S5, the Vo of Al₂O₃ deposited using O₃ (12.57%) is less than that deposited using H₂O (28.94%), which shows that the Al₂O₃ deposited using O₃ possesses better film quality and the process can lead to less impact of the pre-treated IGZO channel layer (the O 1s spectrum for IGZO is largely influenced by the Al-O-Al peak of Al₂O₃ around 531.2 eV) [32]. AFM was employed to investigate the surface morphology of the IGZO thin films with and without Al₂O₃ capping layers, as shown in Figure 3c–e. The R_q values were measured to be 0.326 nm for the bare IGZO layer, 0.321 nm for the IGZO/Al₂O₃-H₂O bilayer, and 0.306 nm for the IGZO/Al₂O₃-O₃ bilayer. The similarity in surface roughness between the uncapped IGZO and the Al₂O₃ capped IGZO bilayers indicates that the Al₂O₃ capping process does not significantly degrade the interfacial roughness between Al₂O₃ and IGZO. Moreover, the more substantial reduction in R_q observed for the IGZO/Al₂O₃-O₃ bilayer compared to the IGZO/Al₂O₃-H₂O bilayer confirms the superior uniformity achieved in the ALD process when using O₃ as the oxygen precursor.

We can now determine that a defect-rich and uneven channel/dielectric interface, characterized by the presence of abundant donor-like defects, trap states, or residual impurities, can introduce additional carriers. This phenomenon significantly impacts both top-gate and bottom-gate electrical characteristics. Minimizing the interfacial defects is crucial for preserving the desired transistor characteristics, particularly in downsized transistors where such defects can severely degrade performance. Based on the findings presented in Figure 2 and Figure 3, we demonstrate that optimizing the ratio of Ga and employing O₃ as the precursor for Al₂O₃ deposition can effectively reduce interfacial defect density, enabling the realization of enhanced electrical properties.

3.3. Scaled Dual-Gate IGZO Transistors Measurements

Based on the parameters derived from our previous experiments, which enabled the devices to achieve high electrical performance, we fabricated nanoscale channel length DG-TFTs with the semiconductor layer composition of In_0.24Ga_0.58Zn_0.18O and utilized O₃ as the oxygen precursor for the Al₂O₃ dielectric layer. Thereafter, the devices were subjected to RTA at 300 °C for 5 min in a nitrogen (N₂) atmosphere, aiming to reduce the density of vacancies in the devices. Figure 4a illustrates the transfer characteristic curves controlled solely by the top gate for a device with L_ch of 1 µm. By fitting the linear part of the transfer characteristic curve in linear coordinates, we measured V_T values of 1.12 V and 1.05 V at drain voltages (V_DS) of 0.05 V and 1 V, respectively. Detailed calculations reveal a remarkably low drain-induced barrier lowering (DIBL) of 75.68 mV/V, highlighting the excellent subthreshold characteristics of the fabricated devices, which suggests a minimal presence of defects at the IGZO/Al₂O₃ interface. This indicates that the fabrication process and post-treatment effectively mitigated interfacial defects. Figure 4b presents the output characteristic curves controlled only by the top gate, with gate voltage (V_GS) changing from −5 V to 7 V in 0.5 V steps. The curves demonstrate that the maximum current can reach 248.2 μA at V_DS = 2 V and V_GS= 7 V. Moreover, the output characteristic curves show nearly linear behavior without deterioration, suggesting that our devices exhibit a weak self-heating effect. Transfer characteristics of the DG-TFTs were further examined with the V_DS at 1 V and the bottom-gate voltage (V_BG) varying from −2 V to 2 V in 0.5 V increments, as illustrated in Figure 4c. The results indicate that the V_T shifts toward the negative direction as the V_BG is gradually increased to 2 V, demonstrating that the top gate remains effective in modulating the device behavior. Conversely, when the V_BG decreased from 0 V to −2 V, the V_T shifts toward the positive direction. This behavior illustrates the robust dual-gate control and the ability to finely tune the device characteristics through both top- and bottom-gate voltage bias.

The electrical performance of DG-TFTs was also examined when the L_ch was reduced to 300 nm. The transfer characteristic curves revealed that the V_T remained nearly unchanged compared to devices with L_ch of 1 µm, indicating that the short channel effect was effectively mitigated through the optimized processes for IGZO layer deposition and Al₂O₃ precursor treatment (Figure 4a,d). Furthermore, the DIBL (78.9 mv/V) was found to be comparable to DG-TFTs with a L_ch of 1 µm, suggesting minimal interface defects that could impact the transfer characteristics. The maximum drain current achieved was 742.3 µA at a V_DS of 2 V, which is approximately three times higher than that observed in devices with a L_ch of 1 µm (Figure 4e). The output curves also exhibit nearly linear behavior, indicating that the devices maintain a weak self-heating effect even with the reduced channel length. Figure 4f presents the transfer characteristic curves controlled by both the top gate and bottom gate. The results show that the V_T shifts in the negative direction as the V_BG is gradually increased to 2 V, and in the opposite direction when V_BG is decreased to −2 V. This behavior is consistent with the observations in Figure 4c, demonstrating that the dual-gate modulation remains effective even with the reduced channel length. At V_BG of 0 V, 0.5 V, and 1 V, the drain current is 6 pA, 27.2 nA, and 1.76 μA under V_TG of −0.6 V, respectively. A high current switching ratio of 3 × 10⁵ is achieved with only 1 V modulation, demonstrating exceptional gate control efficiency with low modulated voltage.

Utilizing EBL technology, the L_ch of the DG-TFTs can be further scaled down to 150 nm without compromising their performance. As shown in Figure 5a, the transfer characteristic curves modulated solely by the top gate exhibit a negative shift in the V_T to −0.75 V and −0.88 V at V_DS of 0.05 V and 1 V, respectively. Precise calculations reveal that I_on/off exceeds 10⁹, while the μ_eff is measured at 11.68 cm²V⁻¹s⁻¹. Compared to DG-TFTs with a L_ch of 300 nm, the DIBL increases to 136.9 mV/V. This increase is attributed to the enhanced electric field between the source and drain electrodes, which can adversely affect the V_T and DIBL. Figure 5b displays the output characteristic curves modulated solely by top-gate voltage, which varies from −5 to 7 V in 0.5 V increments. When the bottom-gate voltage is held constant, the device can be effectively modulated by the top gate without any noticeable performance degradation (Figure 5c). This behavior demonstrates that the dual-gate configuration can efficiently control the device performance, even with a further reduced channel length. A current switch ratio of 2 × 10⁴ can be achieved only with 1 V modulation, which can be used in high-sensitive detectors or low-power circuitry with outstanding performance. Figure 5d presents the transfer characteristic curves when the device is controlled exclusively by the bottom gate. The transfer characteristic curves in Figure 5b,e exhibit nearly linear behavior, suggesting that the device with such a short channel length also shows a weak self-heating effect despite its 150 nm channel length. For the transfer characteristic curves shown in Figure 5f, the results are obtained under dual-gate modulation with the top gate held constant. These results show that the V_T shift to a negative direction under positive bias and the shift to a positive direction under negative bias are consistent with those in Figure 5c. Collectively, these findings confirm the stability and reliability of dual-gate modulation even at the hundred-nanometer scale.

To clearly illustrate the performance of the nanoscale channel length DG-TFTs, we conducted a comprehensive summary of the modulation characteristics of the devices with channel length ranging from 1 µm to 150 nm. The data points are derived from the average of at least five individual devices, ensuring the reliability and reproducibility of the results. Figure 6a illustrates the variation in the V_T of the DG-TFTs with the V_BG ranging from −2 V to 2 V in 0.5 V increments. The shift in V_T exhibits a linear relationship with the bottom-gate voltage for channel lengths of 150 nm, 300 nm, and 1 µm. Notably, even under low modulation voltages, the shift in V_T is significant. Figure 6b,c present the V_T and DIBL of the devices modulated by the top gate and bottom gate, respectively. As the channel length scales down, the V_T shifts towards the negative direction due to the short channel effect. However, the DIBL remains relatively low, attributed to the high-quality, few-defect-contaminated interfaces between the semiconductor and the dielectric layers of both the top gate and bottom gate. As illustrated in Figure 6d, the effective mobility decreases from 21.54 cm²V⁻¹s⁻¹ to 11.68 cm²V⁻¹s⁻¹ for the top-gate measurement, while this value deceases from 29.7 cm²V⁻¹s⁻¹ to 22.46 cm²V⁻¹s⁻¹ for the bottom-gate measurement as the channel length is reduced. The decline in µ_eff can be attributed to the enhancement of interfacial scattering and the increased contact resistance when the L_ch is scaled down to 150 nm [33]. The difference can be attributed to the better interface between IGZO and HfO₂ (annealing at 350 °C in air for 2 h) and relatively poor interface between IGZO and Al₂O₃ (limited by thermal budge due to the metal electrode and worsened by TMA during the ALD process) [34]. Figure 6e shows the SS as a function of L_ch under top-gate and bottom-gate modulation, respectively. Minimum SS values of 102.4 mV/dec for the top gate and 94.8 mV/dec for the bottom gate are achieved. The observed SS degradation predominantly originates from interface defects that concurrently degrade device performance [35,36,37]. These defects act as scattering centers that diminish carrier mobility while simultaneously functioning as charge-trapping sites that impede carrier transport. On-current (I_ON) curves show that the devices predominantly follow a 1/L scaling trend, which can be attributed to the low drain-source voltage and the suppression of the self-heating effect.

To comprehensively elucidate the electrical characteristics of the DG-TFTs after increasing the ratio of Ga, we employed the transmission-line modeling (TLM) method to calculate the contact resistance (R_c) [38]:

$$R_{tot}={\displaystyle \frac{L}{W{\mu C}_{ox}\left(V_G-V_T\right)}}+R_c$$

(2)

Here, $R_{tot}$, $V_T$, and $R_c$ are the total resistance, threshold voltage, and contact resistance, respectively. The $R_{tot}$ exhibits a linear decrease as the channel length is reduced, particularly for devices under top-gate control (Figure 7a) and bottom-gate control (Figure 7b). Figure 7b illustrates the dependence of $R_c$ on the top-gate voltage, as extracted from TLM measurements at V_DS = 0.06 V. A low contact resistance of 628 ± 112 Ω·μm at V_GS = 7 V for the top gate and 402 ± 64 Ω·μm at V_GS = 4 V was obtained from the y-axis intercept for the top-gate and bottom-gate measurements, indicating effective electrical contact between the electrodes and the semiconductor. The difference in $R_c$ extracted from top-gate and bottom-gate measurements can contribute to the effect of transverse source-drain electric field and the quality of the interface between IGZO and the top dielectric [39]. To further highlight the superior electrical performance of our devices, we compared them with previously reported works, as shown in Figure 7c. The benchmark is defined as the normalized current divided by the modulation voltage (ΔI/V_M), where ΔI represents the current change under various modulation voltages (V_M). Our devices achieve a high normalized current variation exceeding 10⁶, despite their nanoscale channel lengths. This performance underscores their suitability for the fabrication of high-performance detectors.

4. Conclusions

In summary, we have successfully demonstrated nanoscale channel length DG-TFTs with semiconductor and dielectric layers deposited using ALD technology. By carefully optimizing the deposition parameters, we achieved a high maximum current of 1.384 mA for the top gate and 1.956 mA for the bottom gate, as well as a low contact resistance of approximately 628 Ω·μm for the top gate and 402 Ω·μm for the bottom gate. Excellent low-voltage modulation capabilities were realized through dual-gate control. Notably, high current switching ratios of 3 × 10⁵ for L_ch of 300 nm and 2 × 10⁴ for L_ch = 150 nm were achieved with only 1 V of gate modulation voltage. We further demonstrated that increasing the Ga ratio and using O₃ as the precursor can significantly suppress the defects at the interface between the IGZO and dielectric layers. Additionally, when scaling down the L_ch to 150 nm, these processes effectively mitigate short channel effects while maintaining robust device performance. These findings are crucial for the advancement of dual-gate IGZO transistor research and open up vast new opportunities for applications in high-performance detectors, BEOL integration, and 3D integration technologies.