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Article

Modeling and Optimization of Structural Tuning in Bandgap-Engineered Tunneling Oxide for 3D NAND Flash Application

by
Zhihong Xu
,
Shibo Xie
,
Zhijun Ying
,
Wenlong Zhang
and
Liming Gao
*
State Key Laboratory of Metal Matrix Composites, School of Material Science and Engineering, Shanghai Jiao Tong University, Shanghai 200240, China
*
Author to whom correspondence should be addressed.
Electronics 2025, 14(7), 1461; https://doi.org/10.3390/electronics14071461
Submission received: 4 March 2025 / Revised: 31 March 2025 / Accepted: 2 April 2025 / Published: 4 April 2025
(This article belongs to the Section Electronic Materials, Devices and Applications)
Browse Figures
Versions Notes

Abstract

:
The bandgap-engineered tunneling oxide (BE-TOX) structure has been proposed to address the incompatibility between erase efficiency and retention performance in NAND flash memory. Previous studies have primarily focused on single flash memory cells, whose architecture significantly differs from that of 3D NAND flash memory. Thus, the BE-TOX structure requires further research and optimization to improve device performance. In this study, the impact of varying proportions of the SiO2/SiOxNy/SiO2 (O1/N/O2) structure on performance is investigated using Technology Computer-Aided Design (TCAD) simulations. The results indicate that as the thickness of the N layer increases, the program/erase (P/E) speed improves, but reliability deteriorates. By adjusting the ratio of the O1 and O2 layers, the P/E speed can be optimized, and an optimal thickness can be identified. The simulation results demonstrate that the phenomenon is attributed to the combined effects of different barrier heights for charge tunneling and variations in band bending across the material layers. This study paves the way for further designing BE-TOX structures with balanced P/E performance and reliability.

1. Introduction

NAND flash memory has emerged as a mainstream storage device widely used in various mobile equipment due to its increasing memory capacity and rapid operational capabilities [1,2]. The basic operational principle of its work relies on charge tunneling to the charge-trapping layer (CTL) or floating gate (FG) structure, which in turn directly impacts the performance of the flash memory device [3]. Previous studies have demonstrated that enhanced program/erase (P/E) cycling speed can be achieved through tunneling oxide (TOX) layer thickness reduction [4]. However, this geometric scaling inevitably reduces the data retention capability [5,6]. To address this issue, the bandgap-engineered tunneling oxide (BE-TOX) structure has been proposed [7,8,9,10]. In this structure, the single tunneling oxide is replaced by a “U-shaped” SiO2/SiOxNy/SiO2 (O1/N/O2) barrier. SiOxNy is a high-k material whose dielectric constant is higher than that of SiO2. And by adjusting its atomic composition, it can be fabricated with a wide range of barrier heights and dielectric constants [7,11]. During program and erase operations, as illustrated in Figure 1a,b, band bending reduces the effective tunneling barrier, allowing charges to tunnel efficiently. Furthermore, under flat-band conditions, as shown in Figure 1c, charges must tunnel through the full barrier. Due to the higher dielectric constant of SiOxNy, the BE-TOX structure exhibits a greater physical thickness compared to a single-layer SiO2 oxide layer while maintaining the same equivalent oxide thickness (EOT). Given the relatively large thickness of this structure, tunneling becomes significantly less probable, thereby ensuring excellent data retention.
Previous studies on the effects of BE-TOX have primarily focused on hole and electron tunneling rates, program/erase characteristics, retention performance, and gate leakage currents [8,12,13,14,15]. And experimental studies have demonstrated that the erase speed exhibits pronounced sensitivity to the O1 layer thickness [9]. Beyond a certain O1 layer thickness, the erase speed degrades substantially, whereas the program speed achieves an optimal value under specific thickness conditions [16]. Moreover, modulation of the dielectric constant in the N layer enables a balance between erase speed and retention performance [11]. Concurrently, parameters such as the N layer thickness and the O2 layer fabrication process exert intricate effects on device characteristics including P/E efficiency and retention properties [7,17,18].
However, experimental implementations are inevitably constrained by process limitations and cost considerations, typically yielding data points within fragmented thickness regimes that inadequately map the continuous variation trend. And these studies have primarily examined the single MOS device, which is different from current mainstream NAND flash products. Since the introduction of 3D NAND products [19], there have been significant changes in both memory array architectures and program/erase schemes. For instance, in 2D NAND flash memories, the channel is formed on p-type wells of a silicon substrate that can supply an sufficient amount of holes, which means that the body erase operation can be conveniently performed [20,21]. But in CMOS-under-array-type flash memories, the device channel is isolated from the substrate, leading to the development of a novel gate-induced drain leakage (GIDL) erase scheme. Therefore, it is essential to investigate the impact of the BE-TOX structure in 3D NAND devices and to optimize it accordingly.
In this study, the BE-TOX structure in 3D NAND flash memory was systematically investigated using Technology Computer-Aided Design (TCAD) simulations. The impact of varying proportions of the O1/N/O2 structure on device performance and reliability was thoroughly examined. Through comprehensive comparisons, an optimized BE-TOX structure was identified. This research aims to provide a deeper understanding of the influence of BE-TOX structures and to explore the potential for parameter optimization.

2. Materials and Methods

Figure 2 illustrates the structure of a 3D NAND flash memory string used in the TCAD simulation. From the outside to the inside, it consists of a tungsten word line (WL), blocking oxide layer, charge-trapping layer, tunneling oxide layer, polysilicon channel, and oxide core filler. From the bottom to the top it contains a source-side select gate (SGS), Cell 1, Cell 2, Cell 3, and drain-side select gate (SGD), with the same WL pitch of 30 nm. Due to its vertical channel structure and isolation from the silicon substrate, an n-type doping with a peak concentration of 6 × 1019 cm−3 is applied at both the bit line (BL) and source line (SL) to form the shared source and drain. The polysilicon channel remains undoped. Within the charge-trapping layer, the nitride electron trap density and nitride hole trap density are both 8 × 1019 cm−3 [22]. Table 1 presents the stacking structure parameters of the flash memory cells. In this paper, the total thickness of the BE-TOX is set to 9 nm, which differs from prior research that primarily focused on modulating single-layer thickness to investigate tunneling-related issues such as program/erase (P/E) speed and data retention characteristics, while inadvertently altering the overall thickness of the tunnel oxide layer. And through TCAD simulation, the influence on device performance is systematically investigated by adjusting the thicknesses of the SiOxNy and SiO2 layers.
Several physical models were adopted for simulation. The Shockley–Read–Hall Recombination model [23] and the Poole–Frenkel model were adopted to simulate recombination through deep defect levels in the bandgap of Si3N4 [24,25]. The doping-dependent mobility degradation model and high-field mobility saturation model were used to simulate scattering of carriers by charged impurity ions and the carrier drift velocity in high electric fields. The nonlocal tunneling model was used for electron/hole transport during the P/E operations [26]. Other models, such as the trap model and band-to-band tunneling model, were also taken into consideration.
The simulation was conducted at a constant temperature (300 K) and the bandgap of SiOxNy was set to 7.1 eV, which is smaller than that of SiO2 (9 eV) but bigger than Si3N4 (5.3 eV). The relative permittivity of SiOxNy can be tuned across a range spanning from SiO2 (3.9) to Si3N4 (7) through precise adjustment of its atomic composition [16]. In this simulation work, the relative dielectric constant of SiOxNy was specified as 6.5, and that of SiO2 is set to 3.9 [27]. For the sake of discussion, we used constant program voltage (Vp) and erase voltage (Ve) instead of the more complex incremental step pulse programming (ISPP) scheme. The maximum transconductance method is used to extract the threshold voltage (Vt) from the drain current–WL voltage curve, while the WL voltage for the remaining cells in the memory string is set to 7 V.

3. Results and Discussion

3.1. Effect of N Layer Thickness Variation on Device Performance in O-N-O Architecture

The BE-TOX structure utilizes the N layer to regulate the configuration of the tunneling layer. Initially, we investigate the impact of N layer thickness on device performance. In this section, for simplicity, the thicknesses of the O1 layer and O2 layer are set to be identical, allowing us to examine how the proportion of low-barrier regions affects the program/erase speed, retention, and program disturb performance.

3.1.1. Performance Analysis of Program and Erase Speed

Firstly, we investigate the program speed under various BE-TOX structures, obtaining the Vt shift corresponding to the same program voltage of 16 V but various program time ranges, as shown in Figure 3a. Different BE-TOX structures exhibit different program speeds: as the N layer increases, the program speed gradually improves. When the N layer exceeds 3 nm, the traps in the CTL gradually become saturated after 10−3 s, resulting in negligible differences in the Vt shift. The generation rate of electron tunneling at the initial stages of the program is depicted in Figure 3b, showing the considerable variation in different structures.
Taking the case of the Fowler–Nordheim (F-N) tunneling, the tunneling current can be expressed as [28,29]:
J F N = A × E 2 · e x p ( − B / E )
A = q 3 m S i 8 π h m o x φ b ,
B = 8 π 2 m o x φ b 3 3 q h ,
where E is the electric field at the injecting interface, q is the elementary charge, mSi and mox are the effective electron mass in the polysilicon channel and SiO2, respectively, h is the Planck constant, and φb is the barrier height. Since the dielectric constant of SiOxNy is greater than that of SiO2, an increasing proportion of SiOxNy leads to a smaller equivalent oxide thickness (EOT), which enhances the electric field, increases the tunneling current, and improves the program speed. Generally, the program process of modern 3D NAND flash takes about 10−4 s [30], which means a reasonably thicker N layer is better for program operation.
Figure 4 shows the distribution of trapped electrons in the charge-trapping layer under a program time of 1 × 10−4 s. In CTL-based flash memory, charge trapping primarily relies on the traps within the Si3N4 layer. As a result, the trapped electrons are non-uniformly distributed in the CTL of the memory cell, and the charge coupling effect is weaker compared to FG-based flash memory. It is observed that when the N layer thickness is below 3 nm, only a limited number of electrons are trapped in the CTL even after the reasonable program time. In contrast, when the N layer thickness exceeds 3 nm, a significantly higher concentration of trapped electrons is achieved in the CTL. Therefore, it is proposed that the N layer thickness should be at least 3 nm to ensure adequate program efficiency.
The erase operation primarily involves two processes: electrons tunneling back from the electron traps in the CTL to the channel, and holes tunneling from the channel into the CTL. The program behavior varies significantly under different BE-TOX structures and is challenging to regulate to be uniform, as shown in Figure 4. Therefore, to ensure identical initial conditions across all groups in the TCAD simulations, all the electron traps were initially set to be fully occupied, while all the hole traps were set to be totally unoccupied. Then, a voltage of 20 V was applied at the BL and SL, 15 V at the SGD/SGS, and 0 V bias at the WLs. This configuration triggers the GIDL effect at the junction of the both select gates, generating a substantial number of hole carriers. Under the influence of the voltage difference along the channel, these holes rapidly migrate into the channel, thereby increasing the channel potential of the NAND string and establishing a boosting potential between channel and gate for all memory cells, which completes the erase operation [31,32]. As shown in Figure 5a, with an increase in the N layer thickness, the magnitude of the erase Vt shift significantly increases. In 3D NAND flash memories, compared to program operation, the erase time is relatively long—approximately 10−3 to 10−2 s [33,34]. Within this timescale, for our experiments, the N layer thickness should exceed 4 nm, as these groups have Vt shift nearly three times faster than groups with the N layer thickness less than 4 nm.
In this simulation, both the release of electrons from the CTL and the tunneling of holes from the channel into the CTL are involved, as illustrated in Figure 5b,c. For the electrons trapped in the CTL, as shown in Figure 5b and Figure 6a, with increasing N layer thickness, the number of electrons back-tunneling from the CTL to the channel increases, leading to a gradual reduction in the trapped electron concentration starting from the CTL away from the BE-TOX interface. This phenomenon occurs because the high potential in the channel causes trapped electrons in the CTL to preferentially accumulate near the BE-TOX interface. Once the trapped electrons tunnel away, the remaining electrons are subsequently driven by the electric field to occupy these vacant trap sites. Moreover, since the initially high concentration of trapped electrons and the fact that the effective mass of holes is greater than that of electrons, and the valence band presents a higher energy barrier compared to the conduction band [35,36,37], a greater number of electrons tunnel from the CTL to the channel than holes injected from the channel. Therefore, in this simulation, the decrease in Vt during the erase operation is primarily governed by the variation in trapped electron concentration over the entire simulation time range. Furthermore, the Vt shift exhibits a more pronounced decrease compared with the increase observed during the program operation in Figure 3a. In practice, as shown in Figure 4, the CTL is not completely saturated with electrons; therefore, the actual Vt shift is expected to be lower than the simulated result.
In summary, under band bending conditions, charges only need to overcome a partial barrier, and due to the increased proportion of the N layer, the barrier distance that needs to be overcome during tunneling is reduced. Additionally, the decrease in EOT leads to an enhanced interfacial electric field. These combined effects promote F-N tunneling, leading to improved program and erase speeds, which aligns with the trend observed in experimental results reported in previous works [7,9,16].

3.1.2. Reliability Analysis of Data Retention and Program Disturb

For flash memories, data retention is important as data are supposed to be stored for many years. In this simulation, the selected cells are first programmed to the same Vt. Then, at 300 K and without any applied bias, the Vt shift is measured over various retention times, as shown in Figure 7a.
It is worth noting that, even under flat-band conditions—where charges must tunnel through the entire barrier—the retention performance varies among different BE-TOX structures. As the proportion of the N layer increases, the retention performance gradually deteriorates, and when the N layer becomes too thick, the Vt shift accelerates significantly. This is because, even without any externally applied bias, the electrons trapped within the CTL cause the energy bands along the WL direction to remain imbalanced, as shown in Figure 7b. The CTL adjacent to the polysilicon channel captures more electrons, which raises its conduction band to a higher level. Consequently, electron tunneling from the CTL to the polysilicon channel remains a process closely linked to the BE-TOX band structure. Furthermore, it is foreseeable that a higher program state will result in inferior retention performance due to the elevated conduction band. This indicates that the BE-TOX structure must be optimized to balance program/erase performance with retention.
Program disturb in NAND flash manifests as unintended threshold voltage shifts in unselected memory cells during program operations, which is exacerbated in 3D NAND flash memory [38]. Previous studies have identified three types of program disturb modes in 3D NAND flash, as shown in Figure 8, among which the Y mode is the most severe due to its lowest channel boost potential [38,39,40]. Here, we investigate the program disturb characteristics of different BE-TOX structures under the Y mode condition. In the simulation under Y mode conditions, the bit line and source line are both set to 0 V. The gate voltages at SGD/SGS are configured to 0 V to maintain their off-state. A voltage of 7 V is applied to the gates of the remaining cells in the memory string to enable conduction. For the cell that is experiencing program disturb, the WL voltage is set to 16 V, consistent with the program simulation configuration.
Since the dielectric constant of SiOxNy is higher than that of SiO2, an increasing proportion of SiOxNy reduces the EOT, leading to a higher effective potential in the channel due to the self-boosting effect [41], as shown in Figure 9a. However, a higher SiOxNy proportion also enhances the electron tunneling. Figure 9b illustrates the Vt shift of cells under the Y mode over different durations, reflecting the competition between these two opposing mechanisms. The result shows that as the SiOxNy proportion increases, the Y mode program disturb effect becomes more pronounced, which is consistent with the result of the program speed simulation.
To quantitatively compare the performance and reliability of devices with different BE-TOX structures, as shown in Figure 10, the Vt shifts obtained from program/erase (P/E), retention, and program disturb simulations are used as metrics. Here, the performance is quantified as the sum of the absolute Vt shifts during program (t = 1 × 10−4 s) and erase (t = 1 × 10−2 s) operations. And the reliability is defined as the negative value of the combined unwanted Vt shifts during retention (t = 1 × 108 s) and Y mode program disturb (t = 1 × 10−4 s) simulations, since the negative value ensures that a larger Vt shift corresponds to worse reliability. The result shows that as the N layer thickness increases from 1 nm to 4 nm, the device performance improves rapidly with only a minor degradation in reliability. However, when the N layer thickness exceeds 5 nm, further increases lead to diminishing performance gains accompanied by a significant deterioration in reliability. Therefore, an N layer thickness of 4 or 5 nm seems to provide an optimal trade-off, enabling the device to achieve enhanced program/erase (P/E) speed performance while maintaining sufficient reliability.

3.2. Optimization of O1 and O2 Layer Thickness for Enhancing Performance

As discussed previously, increasing the proportion of the N layer improves the P/E speed; however, if the N layer becomes too thick, data retention performance deteriorates and program disturb issues are exacerbated. Therefore, it is advisable to fabricate the N layer within an acceptable range. Among the structures simulated in this work, an N layer thickness of either 4 nm or 5 nm is deemed acceptable. In this section, with the N layer fixed at 5 nm, the thicknesses of the O1 and O2 layers are varied to investigate their effect on performance and reliability.
Firstly, Figure 11a illustrates the Vt shift under different program operation times. When the O1 layer thickness varies from 0.5 nm to 2.5 nm, the program speed increases; while as the O1 layer thickness continues to increase beyond 2.5 nm, the program speed decreases. The fastest program speed is observed when the O1 layer thickness is about 2 nm. This phenomenon can be explained by their band diagrams, as shown in Figure 11b, depicting the initial band diagrams for different BE-TOX structures during program operation. Due to the higher dielectric constant of SiOxNy, the band bending at SiOxNy occurs more gradually. When the O1 layer is too thin, as the thicknesses of O1 layer decrease, the tunneling distances become longer, resulting in a decrease in program speed. As the O1 layer thickens sufficiently, the electrons only need to tunnel through part of the O1 layer’s barrier, thus causing the program speed to decrease with increasing O1 layer thickness, which is similar to normal conditions.
For the erase simulation, each group was first programmed to the same Vt, followed by GIDL erase operations. The results are shown in Figure 12a, which reveals a two-stage process: initially, electrons reverse-tunnel from the CTL back to the channel, leading to a decline in threshold voltage; subsequently, holes tunnel from the channel into the CTL, causing further Vt reduction. Prior to t = 10−4 s, the dominant mechanism is the tunneling of trapped electrons, as shown in Figure 12b. Notably, the tunneling rate increases as the thickness of the O2 layer decreases. All the trapped electrons are completely swept out of the CTL before 10−4 s. Beyond this point of time, holes gradually tunnel into the CTL as the erase operation continues. Similar to the program scenario, the hole tunneling rate into the CTL accelerates with decreasing O1 layer thickness in the 0.5–2.5 nm range but decelerates in the 2.5–3.5 nm range due to variations in the effective barrier length. Analysis of the Vt shift results demonstrates that, within practical erase time windows, faster erase speeds are achieved when the O1 layer thickness is optimized to 2.5 nm.
Similarly, Figure 13 presents a comparative analysis of performance and reliability between different O1 and O2 layers. In program/erase operations, significant band bending occurs under external electric fields, enabling charges to tunnel through only a portion of the BE-TOX barrier. Consequently, modifying the thickness of O1 and O2 layers can effectively regulate charge tunneling characteristics. However, for reliability evaluation which includes retention and program disturb, the potential difference across BE-TOX is insignificant, resulting in limited band bending. Under these conditions, charges need to tunnel through the entire BE-TOX barrier, explaining why devices with varying thicknesses of O1 and O2 layers but identical N layer thickness demonstrate similar reliability performance.
Based on the simulation results and considering both performance and reliability, we can conclude that the O1/N/O2 structure with thicknesses of 2.5/5/1.5 nm demonstrates superior performance. It is worth noting that certain non-ideal factors, such as the presence of trap states in the BE-TOX layers, the different energy levels of electron and hole traps in the CTL, and the complexities of the P/E schemes, were not considered in this study. The trap states in the BE-TOX can assist tunneling, leading to variations in the P/E speed and degradation of the retention characteristics. Additionally, the different energy levels of the electron and hole traps in the CTL, as well as variations in the P/E schemes, could result in more complex trends. These non-ideal factors necessitate further investigation with additional experimental data to gain a deeper understanding in future studies.

4. Conclusions

In this study, the performance of various BE-TOX structures in 3D NAND flash memory was investigated using TCAD simulations. The research revealed that in the O1/N/O2 structures with varying proportions, as the ratio of the narrow bandgap N layer increases, the program and erase speeds improve accordingly. However, this enhancement comes at the cost of rapid degradation in retention performance and an increase in program disturb. By maintaining a fixed N layer thickness, adjusting the O1/O2 ratio can optimize the program and erase speed, as modifying the thickness can affect the effective tunneling barrier of electrons and holes under band bending. Among the experimental groups in this study, we infer that the O1/N/O2 structure with thicknesses of 2.5/5/1.5 nm exhibits the best overall performance in this experiment. This study provides actionable guidelines for improving BE-TOX structures in high-density 3D NAND flash memories.

Author Contributions

Conceptualization, Z.X., S.X. and Z.Y.; Data curation, Z.X., S.X. and Z.Y.; Formal analysis, Z.X., S.X. and Z.Y.; Investigation, Z.X.; Methodology, Z.X., S.X. and Z.Y.; Project administration, W.Z. and L.G.; Software, Z.X.; Supervision, W.Z. and L.G.; Validation, Z.X., S.X. and Z.Y.; Visualization, Z.X.; Writing—original draft, Z.X., S.X. and Z.Y.; Writing—review and editing, W.Z. and L.G. All authors have read and agreed to the published version of the manuscript.

Funding

This research received no external funding.

Data Availability Statement

The original contributions presented in the study are included in the article.

Conflicts of Interest

The authors declare no conflicts of interest.

References

  1. Kim, S.S.; Yong, S.K.; Kim, W.; Kang, S.; Park, H.W.; Yoon, K.J.; Sheen, D.S.; Lee, S.; Hwang, C.S. Review of Semiconductor Flash Memory Devices for Material and Process Issues. Adv. Mater. 2023, 35, 2200659. [Google Scholar] [CrossRef]
  2. Kim, B.; Lee, S.; Hah, B.; Park, K.; Park, Y.; Jo, K.; Noh, Y.; Seol, H.; Lee, H.; Shin, J.; et al. 28.2 A High-Performance 1Tb 3b/Cell 3D-NAND Flash with a 194MB/s Write Throughput on over 300 Layers. In Proceedings of the 2023 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 19–23 February 2023; pp. 27–29. [Google Scholar]
  3. Monzio Compagnoni, C.; Goda, A.; Spinelli, A.S.; Feeley, P.; Lacaita, A.L.; Visconti, A. Reviewing the Evolution of the NAND Flash Technology. Proc. IEEE 2017, 105, 1609–1633. [Google Scholar] [CrossRef]
  4. Chung, S.S.; Chiang, P.-Y.; Chou, G.; Huang, C.-T.; Chen, P.; Chu, C.-H.; Hsu, C.C.-H. A Novel Leakage Current Separation Technique in a Direct Tunneling Regime Gate Oxide SONOS Memory Cell. In Proceedings of the IEEE International Electron Devices Meeting 2003, Washington, DC, USA, 8–10 December 2003; pp. 26.6.1–26.6.4. [Google Scholar]
  5. Vianello, E.; Driussi, F.; Palestri, P.; Arreghini, A.; Esseni, D.; Selmi, L.; Akil, N.; van Duuren, M.; Golubovic, D.S. Impact of the Charge Transport in the Conduction Band on the Retention of Si-Nitride Based Memories. In Proceedings of the ESSDERC 2008 —38th European Solid-State Device Research Conference, Scotland, UK, 15–19 September 2008; pp. 107–110. [Google Scholar]
  6. Goda, A. Recent Progress on 3D NAND Flash Technologies. Electronics 2021, 10, 3156. [Google Scholar] [CrossRef]
  7. Lue, H.-T.; Lai, S.-C.; Hsu, T.-H.; Du, P.-Y.; Wang, S.-Y.; Hsieh, K.-Y.; Liu, R.; Lu, C.-Y. Modeling of Barrier-Engineered Charge-Trapping Nand Flash Devices. IEEE Trans. Device Mater. Reliab. 2010, 10, 222–232. [Google Scholar] [CrossRef]
  8. Lue, H.-T.; Wang, S.-Y.; Lai, E.-K.; Hsieh, K.-Y.; Liu, R.; Lu, C.Y. A BE-SONOS (Bandgap Engineered SONOS) NAND for Post-Floating Gate Era Flash Memory. In Proceedings of the 2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, 23–25 April 2007; pp. 1–2. [Google Scholar]
  9. Lue, H.-T.; Wang, S.-Y.; Lai, E.-K.; Shih, Y.-H.; Lai, S.-C.; Yang, L.-W.; Chen, K.-C.; Ku, J.; Hsieh, K.-Y.; Liu, R.; et al. BE-SONOS: A Bandgap Engineered SONOS with Excellent Performance and Reliability. In Proceedings of the IEEE International Electron Devices Meeting, 2005. IEDM Technical Digest, Washington, DC, USA, 5–7 December 2005; pp. 547–550. [Google Scholar]
  10. Lai, S.-C.; Lue, H.-T.; Yang, M.-J.; Hsieh, J.-Y.; Wang, S.-Y.; Wu, T.-B.; Luo, G.-L.; Chien, C.-H.; Lai, E.-K.; Hsieh, K.-Y.; et al. MA BE-SONOS: A Bandgap Engineered SONOS Using Metal Gate and Al2O3 Blocking Layer to Overcome Erase Saturation. In Proceedings of the 2007 22nd IEEE Non-Volatile Semiconductor Memory Workshop, Monterey, CA, USA, 26–30 August 2007; pp. 88–89. [Google Scholar]
  11. Liao, J.-H.; Hsieh, J.-Y.; Lue, H.-T.; Yang, L.-W.; Yang, T.; Chen, K.-C.; Lu, C.Y. Performance and Reliability Optimizations of BE-SONOS NAND Flash Using SiON Bandgap-Tuning Tunneling Barrier. In Proceedings of the 2010 IEEE International Reliability Physics Symposium, Anaheim, CA, USA, 2–6 May 2010; pp. 639–643. [Google Scholar]
  12. Wang, S.-Y.; Lue, H.-T.; Hsu, T.-H.; Du, P.-Y.; Lai, S.-C.; Hsiao, Y.-H.; Hong, S.-P.; Wu, M.-T.; Hsu, F.-H.; Lian, N.-T.; et al. A High-Endurance (≫100K) BE-SONOS NAND Flash with a Robust Nitrided Tunnel Oxide/Si Interface. In Proceedings of the 2010 IEEE International Reliability Physics Symposium, Anaheim, CA, USA, 2–6 May 2010; pp. 951–955. [Google Scholar]
  13. Kim, M.; Shin, H. Analysis and Compact Modeling of Fast Detrapping from Bandgap-Engineered Tunneling Oxide in 3-D NAND Flash Memories. IEEE Trans. Electron Devices 2021, 68, 3339–3345. [Google Scholar] [CrossRef]
  14. Cho, T.; Jung, S.; Kang, M. Channel Potential of Bandgap-Engineered Tunneling Oxide (BE-TOX) in Inhibited 3D NAND Flash Memory Strings. Electronics 2024, 13, 1573. [Google Scholar] [CrossRef]
  15. Yoon, G.; Ko, D.; Park, J.; Kim, D.; Kim, J.; Lee, J.-S. Impact of P/E Stress on Trap Profiles in Bandgap-Engineered Tunneling Oxide of 3D NAND Flash Memory. IEEE Access 2022, 10, 62423–62428. [Google Scholar] [CrossRef]
  16. Ouyang, Y.; Xia, Z.; Yang, T.; Shi, D.; Zhou, W.; Huo, Z. Optimization of Performance and Reliability in 3D NAND Flash Memory. IEEE Electron Device Lett. 2020, 41, 840–843. [Google Scholar] [CrossRef]
  17. Van den Bosch, G.; Kar, G.S.; Blomme, P.; Arreghini, A.; Cacciato, A.; Breuil, L.; De Keersgieter, A.; Paraschiv, V.; Vrancken, C.; Douhard, B.; et al. Highly Scaled Vertical Cylindrical SONOS Cell With Bilayer Polysilicon Channel for 3-D Nand Flash Memory. IEEE Electron Device Lett. 2011, 32, 1501–1503. [Google Scholar] [CrossRef]
  18. Lue, H.-T.; Shih, Y.-H.; Hsieh, K.-Y.; Liu, R.; Lu, C.-Y. A Transient Analysis Method to Characterize the Trap Vertical Location in Nitride-Trapping Devices. IEEE Electron Device Lett. 2004, 25, 816–818. [Google Scholar] [CrossRef]
  19. Park, K.-T.; Nam, S.; Kim, D.; Kwak, P.; Lee, D.; Choi, Y.-H.; Choi, M.-H.; Kwak, D.-H.; Kim, D.-H.; Kim, M.-S.; et al. Three-Dimensional 128 Gb MLC Vertical Nand Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming. IEEE J. Solid-State Circuits 2015, 50, 204–213. [Google Scholar] [CrossRef]
  20. Jang, J.; Kim, H.-S.; Cho, W.; Cho, H.; Kim, J.; Shim, S.I.; Younggoan; Jeong, J.-H.; Son, B.-K.; Kim, D.W.; et al. Vertical Cell Array Using TCAT (Terabit Cell Array Transistor) Technology for Ultra High Density NAND Flash Memory. In Proceedings of the 2009 Symposium on VLSI Technology, Kyoto, Japan, 15–17 June 2009; pp. 192–193. [Google Scholar]
  21. Hemink, G.; Goda, A. 5-NAND Flash Technology Status and Perspectives. In Semiconductor Memories and Systems; Redaelli, A., Pellizzer, F., Eds.; Woodhead Publishing Series in Electronic and Optical Materials; Woodhead Publishing: Cambridge, UK, 2022; pp. 119–158. ISBN 978-0-12-820758-1. [Google Scholar]
  22. Nam, K.; Park, C.; Yoon, J.-S.; Jang, H.; Park, M.S.; Sim, J.; Baek, R.-H. Origin of Incremental Step Pulse Programming (ISPP) Slope Degradation in Charge Trap Nitride Based Multi-Layer 3D NAND Flash. Solid State Electron. 2021, 175, 107930. [Google Scholar] [CrossRef]
  23. Cuevas, A.; Stocks, M.; McDonald, D.; Kerr, M.; Samundsett, C. Recombination and Trapping in Multicrystalline Silicon. IEEE Trans. Electron Devices 1999, 46, 2026–2034. [Google Scholar] [CrossRef]
  24. Southwick, R.G.; Reed, J.; Buu, C.; Butler, R.; Bersuker, G.; Knowlton, W.B. Limitations of Poole–Frenkel Conduction in Bilayer HfO2/SiO2 MOS Devices. IEEE Trans. Device Mater. Reliab. 2010, 10, 201–207. [Google Scholar] [CrossRef]
  25. Swain, R.; Jena, K.; Lenka, T.R. Modeling of Forward Gate Leakage Current in MOSHEMT Using Trap-Assisted Tunneling and Poole–Frenkel Emission. IEEE Trans. Electron Devices 2016, 63, 2346–2352. [Google Scholar] [CrossRef]
  26. Ieong, M.; Solomon, P.M.; Laux, S.E.; Wong, H.-S.P.; Chidambarrao, D. Comparison of Raised and Schottky Source/Drain MOSFETs Using a Novel Tunneling Contact Model. In Proceedings of the International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217), San Francisco, CA, USA, 6–9 December 1998; pp. 733–736. [Google Scholar]
  27. Yoon, G.; Go, D.; Park, J.; Kim, D.; Kim, J.; An, U.; Kim, J.; Lee, J.-S.; Kong, B.D. Impact of Electron and Hole Trap Profiles in BE-TOX on Retention Characteristics of 3D NAND Flash Memory. IEEE Trans. Nanotechnol. 2024, 23, 733–740. [Google Scholar] [CrossRef]
  28. Lenzlinger, M.; Snow, E.H. Fowler-Nordheim Tunneling into Thermally Grown SiO2. J. Appl. Phys. 1969, 40, 278–283. [Google Scholar] [CrossRef]
  29. Salace, G.; Hadjadj, A.; Petit, C.; Jourdain, M. Temperature Dependence of the Electron Affinity Difference between Si and SiO2 in Polysilicon (N+)–Oxide–Silicon (p) Structures: Effect of the Oxide Thickness. J. Appl. Phys. 1999, 85, 7768–7773. [Google Scholar] [CrossRef]
  30. Siau, C.; Kim, K.-H.; Lee, S.; Isobe, K.; Shibata, N.; Verma, K.; Ariki, T.; Li, J.; Yuh, J.; Amarnath, A.; et al. 13.5 A 512Gb 3-Bit/Cell 3D Flash Memory on 128-Wordline-Layer with 132MB/s Write Performance Featuring Circuit-Under-Array Technology. In Proceedings of the 2019 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 17–21 February 2019; pp. 218–220. [Google Scholar]
  31. Komori, Y.; Kido, M.; Kito, M.; Katsumata, R.; Fukuzumi, Y.; Tanaka, H.; Nagata, Y.; Ishiduki, M.; Aochi, H.; Nitayama, A. Disturbless Flash Memory Due to High Boost Efficiency on BiCS Structure and Optimal Memory Film Stack for Ultra High Density Storage Device. In Proceedings of the 2008 IEEE International Electron Devices Meeting, San Francisco, CA, USA, 15–17 December 2008; pp. 1–4. [Google Scholar]
  32. Fukuzumi, Y.; Katsumata, R.; Kito, M.; Kido, M.; Sato, M.; Tanaka, H.; Nagata, Y.; Matsuoka, Y.; Iwata, Y.; Aochi, H.; et al. Optimal Integration and Characteristics of Vertical Array Devices for Ultra-High Density, Bit-Cost Scalable Flash Memory. In Proceedings of the 2007 IEEE International Electron Devices Meeting, Washington, DC, USA, 10–12 December 2007; pp. 449–452. [Google Scholar]
  33. Hsu, T.-H.; Lue, H.-T.; Du, P.-Y.; Chen, W.-C.; Yeh, T.-H.; Lo, R.; Chang, H.-S.; Wang, K.-C.; Lu, C.-Y. Study of Self-Healing 3D NAND Flash with Micro Heater to Improve the Performances and Lifetime for Fast NAND in NVDIMM Applications. In Proceedings of the 2019 IEEE 11th International Memory Workshop (IMW), Monterey, CA, USA, 12–15 May 2019; pp. 1–4. [Google Scholar]
  34. Choi, S.; Choi, C.; Jeong, J.K.; Song, Y.-H. Innovative Structure to Improve Erase Speed in 3-D Nand Flash Memory with Cell-on-Peri (COP) Applied. IEEE Trans. Electron Devices 2022, 69, 4883–4888. [Google Scholar] [CrossRef]
  35. Keister, J.W.; Rowe, J.E.; Kolodziej, J.J.; Niimi, H.; Madey, T.E.; Lucovsky, G. Band Offsets for Ultrathin SiO2 and Si3N4 Films on Si (111) and Si (100) from Photoemission Spectroscopy. J. Vac. Sci. Technol. B Microelectron. Nanometer Struct. Process. Meas. Phenom. 1999, 17, 1831–1835. [Google Scholar] [CrossRef]
  36. Miyazaki, S. Photoemission Study of Energy-Band Alignments and Gap-State Density Distributions for High-k Gate Dielectrics. J. Vac. Sci. Technol. B Microelectron. Nanometer Struct. Process. Meas. Phenom. 2001, 19, 2212–2216. [Google Scholar] [CrossRef]
  37. Sorokin, A.N.; Karpushin, A.A.; Gritsenko, V.A.; Wong, H. Electronic Structure of Amorphous Silicon Oxynitride with Different Compositions. J. Appl. Phys. 2009, 105, 073706. [Google Scholar] [CrossRef]
  38. Shim, K.S.; Choi, E.S.; Jung, S.W.; Kim, S.H.; Yoo, H.S.; Jeon, K.S.; Hong, S.J. Inherent Issues and Challenges of Program Disturbance of 3D NAND Flash Cell. In Proceedings of the 2012 4th IEEE International Memory Workshop, Milan, Italy, 20–23 May 2012; pp. 1–4. [Google Scholar]
  39. Choi, E.-S.; Park, S.-K. Device Considerations for High Density and Highly Reliable 3D NAND Flash Cell in near Future. In Proceedings of the 2012 International Electron Devices Meeting, San Francisco, CA, USA, 10–13 December 2012; pp. 9.4.1–9.4.4. [Google Scholar]
  40. Yoo, H.; Choi, E.; Oh, J.; Park, K.; Jung, S.; Kim, S.; Shim, K.; Joo, H.; Jeon, K.; Seo, M.; et al. Modeling and Optimization of the Chip Level Program Disturbance of 3D NAND Flash Memory. In Proceedings of the 2013 5th IEEE International Memory Workshop, Monterey, CA, USA, 26–29 May 2013; pp. 147–150. [Google Scholar]
  41. Kang, M.; Kim, Y. Natural Local Self-Boosting Effect in 3D NAND Flash Memory. IEEE Electron Device Lett. 2017, 38, 1236–1239. [Google Scholar] [CrossRef]
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Figure 1. Band diagram of BE-TOX structure during (a) program operation, (b) erase operation, and (c) retention.
Figure 1. Band diagram of BE-TOX structure during (a) program operation, (b) erase operation, and (c) retention.
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Figure 2. Schematic of a 3D NAND string used in TCAD simulation.
Figure 2. Schematic of a 3D NAND string used in TCAD simulation.
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Figure 3. (a) Vt shift with various program times for different BE-TOX and (b) electron tunneling at the beginning (t = 0 s) of program operation.
Figure 3. (a) Vt shift with various program times for different BE-TOX and (b) electron tunneling at the beginning (t = 0 s) of program operation.
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Figure 4. Distribution of trapped electrons in the CTL of different BE-TOX structures when the program time t = 1 × 10−4 s.
Figure 4. Distribution of trapped electrons in the CTL of different BE-TOX structures when the program time t = 1 × 10−4 s.
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Figure 5. (a) Vt shift with various GIDL erase times for different BE-TOX structures and the average density of (b) trapped electrons and (c) trapped holes in the CTL layer measured under erase time.
Figure 5. (a) Vt shift with various GIDL erase times for different BE-TOX structures and the average density of (b) trapped electrons and (c) trapped holes in the CTL layer measured under erase time.
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Figure 6. Distribution of (a) trapped electrons and (b) trapped holes in the CTL of different BE-TOX structures when the erase time t = 1 × 10−2 s.
Figure 6. Distribution of (a) trapped electrons and (b) trapped holes in the CTL of different BE-TOX structures when the erase time t = 1 × 10−2 s.
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Figure 7. (a) Simulated data retention characteristics of different BE-TOX structures under zero bias condition. (b) Conduction band of some groups when electrons are stored in the CTL at zero bias voltage.
Figure 7. (a) Simulated data retention characteristics of different BE-TOX structures under zero bias condition. (b) Conduction band of some groups when electrons are stored in the CTL at zero bias voltage.
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Figure 8. (a) Schematic diagram of the three program disturb modes in 3D NAND flash memory, and (b) the corresponding bias table. (VCC = 2 V, the bias of SGD/SGS is 0 V for the on-state and 7 V for the off-state).
Figure 8. (a) Schematic diagram of the three program disturb modes in 3D NAND flash memory, and (b) the corresponding bias table. (VCC = 2 V, the bias of SGD/SGS is 0 V for the on-state and 7 V for the off-state).
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Figure 9. (a) Channel potential of different BE-TOX structures at the beginning of the Y mode program disturb. (b) The Vt shift at different time intervals.
Figure 9. (a) Channel potential of different BE-TOX structures at the beginning of the Y mode program disturb. (b) The Vt shift at different time intervals.
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Figure 10. The comparison of performance and reliability for different BE-TOX structures. The value of performance is defined as ( | ∆ V p r o g r a m | + | ∆ V e r a s e | ) , where   ∆ V p r o g r a m is the Vt shift when the program time t = 1 × 10−4 s, and the ∆ V e r a s e is the Vt shift when the erase time t = 1 × 10−2 s. The value of reliability is defined as ( − | ∆ V r e t e n t i o n | − | ∆ V d i s t u r b | ) , where   ∆ V r e t e n t i o n is the Vt shift when the retention time t = 1 × 108 s, and the ∆ V d i s t u r b is the Vt shift when the time t = 1 × 10−4 s, and the negative sign indicates degraded reliability with higher values.
Figure 10. The comparison of performance and reliability for different BE-TOX structures. The value of performance is defined as ( | ∆ V p r o g r a m | + | ∆ V e r a s e | ) , where   ∆ V p r o g r a m is the Vt shift when the program time t = 1 × 10−4 s, and the ∆ V e r a s e is the Vt shift when the erase time t = 1 × 10−2 s. The value of reliability is defined as ( − | ∆ V r e t e n t i o n | − | ∆ V d i s t u r b | ) , where   ∆ V r e t e n t i o n is the Vt shift when the retention time t = 1 × 108 s, and the ∆ V d i s t u r b is the Vt shift when the time t = 1 × 10−4 s, and the negative sign indicates degraded reliability with higher values.
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Figure 11. (a) Threshold voltage shift over time for different structures and (b) energy band diagram of the group with O1 layer less than 2.5 nm at the beginning of the program operation.
Figure 11. (a) Threshold voltage shift over time for different structures and (b) energy band diagram of the group with O1 layer less than 2.5 nm at the beginning of the program operation.
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Figure 12. (a) Vt shift with various GIDL erase times for different BE-TOX structures and the density of (b) trapped electrons and (c) trapped holes in the CTL layer measured under erase time.
Figure 12. (a) Vt shift with various GIDL erase times for different BE-TOX structures and the density of (b) trapped electrons and (c) trapped holes in the CTL layer measured under erase time.
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Figure 13. The comparison of performance and reliability for different BE-TOX structures.
Figure 13. The comparison of performance and reliability for different BE-TOX structures.
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Table 1. Structure parameters of the stacked flash memory cells.
Table 1. Structure parameters of the stacked flash memory cells.
ParametersValue (nm)
Thickness of core filler (Tcore)15
Thickness of polysilicon channel (Tchannel)15
Thickness of the first SiO2 tunneling layer (TO1)4/3.5/3/2.5/2/1.5/1/0.5
Thickness of the SiOxNy tunneling layer (TN)1/2/3/4/5/6/7
Thickness of the second SiO2 tunneling layer (TO2)4/3.5/3/2.5/2/1.5/1/0.5
Thickness of charge-trapping layer (TCTL)7
Thickness of SiO2 blocking oxide layer (TBO)8
Thickness of Al2O3 layer (TA)4
Thickness of TiN layer (TTi)3
Thickness of tungsten gate (TW)8
Length of the word line (Lw)30
Length of the spacing between word lines (Ls)30
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Xu, Z.; Xie, S.; Ying, Z.; Zhang, W.; Gao, L. Modeling and Optimization of Structural Tuning in Bandgap-Engineered Tunneling Oxide for 3D NAND Flash Application. Electronics 2025, 14, 1461. https://doi.org/10.3390/electronics14071461

AMA Style

Xu Z, Xie S, Ying Z, Zhang W, Gao L. Modeling and Optimization of Structural Tuning in Bandgap-Engineered Tunneling Oxide for 3D NAND Flash Application. Electronics. 2025; 14(7):1461. https://doi.org/10.3390/electronics14071461

Chicago/Turabian Style

Xu, Zhihong, Shibo Xie, Zhijun Ying, Wenlong Zhang, and Liming Gao. 2025. "Modeling and Optimization of Structural Tuning in Bandgap-Engineered Tunneling Oxide for 3D NAND Flash Application" Electronics 14, no. 7: 1461. https://doi.org/10.3390/electronics14071461

APA Style

Xu, Z., Xie, S., Ying, Z., Zhang, W., & Gao, L. (2025). Modeling and Optimization of Structural Tuning in Bandgap-Engineered Tunneling Oxide for 3D NAND Flash Application. Electronics, 14(7), 1461. https://doi.org/10.3390/electronics14071461

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