A Novel Darlington Structure Power Switch Using a Vacuum Field Emission Transistor

Abstract

This study proposes a power switch combining a vacuum field emission transistor (VFET) as a controlled transistor with a power bipolar Darlington transistor (DT) as an output transistor, termed the VFET–DT structure. Compared to the MOS–bipolar Darlington power switch, the VFET–DT structure achieves an extremely low off-state leakage current and high-voltage withstanding capability due to the field emission mechanism of the VFET. It can also avoid the Miller effect that results from incorporating the load resistance into the feedback loop. The high gain and high-power capacity can be achieved due to the cascade of DT. The device’s typical electrical characteristics were theoretically investigated by simulation. The VFET–DT structure exhibited a high-power capacity of 20 A and 400 V with a minimum conduction voltage drop of 1.316 V and a switching frequency of 100 kHz. The results demonstrated that the combination of a vacuum transistor and a solid-state transistor combines the advantages of both and benefits the performance of the power switch.

1. Introduction

The advent of microfabrication techniques and field emission devices has led to the development of the vacuum field emission transistor (VFET). This device has been miniaturized on chips while having the advantages of high voltage, high frequency, and excellent temperature tolerance. The device was regarded as a possible application for electronic technology in power switches and amplifiers. In recent years, high-voltage and high-frequency VFETs have been extensively studied [1]. The excellent insulating properties of the vacuum medium result in a high critical electric field, enabling the VFET to operate safely at high voltages of up to ~40 kV [2]. Since electrons in a vacuum move by ballistic transport, unaffected by lattice scattering in solid materials, the saturation drift velocity of electrons is extremely high, and the cutoff frequency of VFET can reach up to gigahertz [3]. However, the low emission current and large forward voltage drop of VFET hinder its application in power switches requiring high output currents and low on-state voltage drops. To overcome this drawback, we developed a new Darlington structure to exploit the superior performance of VFET.

The Darlington structure is a compound configuration that employs the cascading of multiple transistors to achieve a current gain far exceeding that of a single transistor. The proposal of this structure was originally made by combining multiple bipolar junction transistors (BJTs) in order to address the issue of inadequate gain in individual BJTs. The Darlington structure facilitates the reduction in size and cost of the base drive circuitry, thereby enabling higher output power. In the course of time, a variety of Darlington structures have been developed by means of cascading different types of transistors. These structures have found wide application in fields such as power amplification, power switching, and integrated circuit design [4,5].

The MOS–bipolar Darlington structure [6,7] is widely regarded as a seminal development in the field of Darlington structures. The device uses a power MOSFET as the driver and a power BJT as the output element. This integration enables the convergence of the MOSFET’s voltage-driven operation, high-speed switching, and low drive power consumption with the BJT’s high-power handling and low conduction voltage drop. The MOS–bipolar Darlington structure underwent a rapid transition from discrete connections to the integrated insulated gate bipolar transistor (IGBT) [8,9], which has subsequently emerged as a pivotal high-speed, high-power switch in industrial applications [10,11].

Subsequently, research was conducted on replacing the transistors’ materials and types at the input and output ends of the Darlington structure in order to obtain better performance. Recently, Wakui et al. employed a Darlington structure integrating a SiC MOSFET and a Si superjunction BJT as a switching device, realizing a power switch with a rating of 600 V and 7 A, accompanied by a forward voltage drop of 0.84 V [12]. The utilization of a Darlington structure for the interconnection of a heterojunction bipolar transistor (HBT) and a high electron-mobility transistor (HEMT) has been demonstrated to be a viable method for achieving an enlarged power-bandwidth device, based on wide-bandgap semiconductor materials such as GaN and GaAs [13,14,15].

However, the switching and power amplification functions of the Darlington structure are inevitably affected by the Miller effect. The Miller effect is the phenomenon by which the effective capacitance at the input terminal is amplified to a level that exceeds the actual capacitance, due to feedback in the circuit. The manifestation of this phenomenon is evident in the delay times observed in the switching processes of turning the system on and off, as well as increased drive losses and reduced switching speeds and bandwidth [16]. This effect is common in MOSFET [17] and IGBT devices [18].

In order to address this issue, a novel Darlington structure for power switches was proposed, which involves cascading a VFET with a bipolar Darlington transistor (DT). The vacuum field emission transistor–bipolar Darlington transistor (VFET–DT) structure is distinct from the MOS–bipolar structure. The device is distinguished by a distinct current-emitting mechanism and a unique connection method, which enables the avoidance of feedback. Consequently, the Miller effect is virtually negligible in this structure, for which the trade-off relation between increasing current gain (β) and increasing switching speed does not need to be considered. As the switching frequency of a commercial MOS–bipolar structure is approximately several tens of kHz [11], the VFET–DT structure has the capacity to achieve a higher switching frequency. In addition, the VFET–DT structure exhibits enhanced robustness, attributable to the fact that the MOS section is susceptible to catastrophic failure, including gate oxide breakdown [19] and electromagnetic interference (EMI) [20].

In this paper, a discrete VFET–DT structure circuit is presented. This has been designed to achieve a blocking voltage of 400 V, a minimum on-state voltage drop (V_CE(sat)) of 1.316 V, and maximum output currents of 10 A under DC conditions and 20 A under pulse conditions. At a switching frequency of 100 kHz, the power loss of the VFET–DT structure is 75.125 W, which is lower than the maximum dissipation of a single BJT at 25 °C. The VFET–DT structure integrates vacuum and solid-state devices, combining the advantages of VFETs (e.g., voltage control, high frequency, and low drive loss) with those of BJTs (e.g., high power and low on-state voltage drop). This combination demonstrates great potential for high-frequency, high-voltage, and power capacity switching applications.

2. Principles and Methods

Firstly, the theoretical origin of the Miller effect is deduced. As demonstrated in Figure 1a,b, the well-known MOS–bipolar Darlington structure and the improved VFET–DT structure proposed in this paper are illustrated, respectively. In the VFET–DT structure, the load resistor (R_L) is connected in parallel with the VFET device at the input terminal, rather than in series as in the traditional MOS–bipolar structure. This modification is predicated on the principle that the anode–cathode voltage V_ac of the VFET remains essentially unaltered during both the on and off states.

The turn-on and turn-off behavior of both VFETs and MOSFETs is controlled by the gate voltage. The application of a drive voltage signal, designated as V_gate, to the gate g results in the emission of electrons from the cathode c of the VFET. These electrons accelerate across the vacuum beneath the high voltage at the anode and are subsequently collected by the anode a to form a field emission current. This process enables the VFET to conduct. The distinction between these two states is that, in the off state, the source–drain of a power MOSFET can withstand almost the entire forward voltage, while the conducting channel formed in the on state exhibits extremely low resistivity, with the forward voltage primarily acting on the load RL. The voltage drop between the cathode and anode of the VFET is not contingent upon the device’s on or off state. It can thus be concluded that, within the VFET–DT structure, anode a of the VFET is directly connected to the DC voltage source Vout, thus ensuring a high voltage is maintained for the purpose of efficient electron collection.

The output section employs a DT formed by cascading transistors T1 and T2 (within the dashed box), with the following output characteristics:

$${\mathrm{I}}_{\mathrm{C}}=\left({\mathrm{\beta }}_1+{\mathrm{\beta }}_2+{\mathrm{\beta }}_1{\mathrm{\beta }}_2\right){\mathrm{I}}_{\mathrm{B}}=\mathrm{\beta }\prime {\mathrm{I}}_{\mathrm{B}}$$

(1)

Here, β′ represents the equivalent current gain of the composite DT. The employment of multiple cascaded transistors at the output results in a higher gain than that achieved by a single transistor. The subsequent section will theoretically demonstrate the advantages of the improved VFET–DT structure.

The arrival of the gate signal V_gate voltage pulse results in the generation of currents I₁ and I₂ across the gate–anode and gate–cathode capacitances, C_ga and C_gc, respectively, of the VFET. This process gives rise to the following set of equations:

$${\mathrm{I}}_1={\mathrm{C}}_{\mathrm{g}\mathrm{a}}{\displaystyle \frac{\mathrm{d}\left({\mathrm{V}}_{\mathrm{g}\mathrm{c}}\mathrm{}-\mathrm{}{\mathrm{V}}_{\mathrm{a}\mathrm{c}}\right)}{\mathrm{d}\mathrm{t}}}={\mathrm{C}}_{\mathrm{g}\mathrm{a}}\left({\displaystyle \frac{\mathrm{d}{\mathrm{V}}_{\mathrm{g}\mathrm{c}}}{\mathrm{d}\mathrm{t}}}\mathrm{}-\mathrm{}{\displaystyle \frac{\mathrm{d}{\mathrm{V}}_{\mathrm{a}\mathrm{c}}}{\mathrm{d}\mathrm{t}}}\right)$$

(2)

$${\mathrm{I}}_2={\mathrm{C}}_{\mathrm{g}\mathrm{c}}{\displaystyle \frac{\mathrm{d}{\mathrm{V}}_{\mathrm{g}\mathrm{c}}}{\mathrm{d}\mathrm{t}}}$$

(3)

$${\mathrm{V}}_{\mathrm{a}\mathrm{c}}={\mathrm{V}}_{\mathrm{o}\mathrm{u}\mathrm{t}}\mathrm{}-\mathrm{}{\mathrm{V}}_{\mathrm{B}\mathrm{E}}$$

(4)

Since V_BE can be considered a constant, we have

$${\displaystyle \frac{\mathrm{d}{\mathrm{V}}_{\mathrm{a}\mathrm{c}}}{\mathrm{d}\mathrm{t}}}=0$$

(5)

Thus, the gate current I_gate of VFET–DT is

$${\mathrm{I}}_{\mathrm{g}\mathrm{a}\mathrm{t}\mathrm{e}}={\mathrm{I}}_1+{\mathrm{I}}_2=\left({\mathrm{C}}_{\mathrm{g}\mathrm{a}}+{\mathrm{C}}_{\mathrm{g}\mathrm{c}}\right){\displaystyle \frac{\mathrm{d}{\mathrm{V}}_{\mathrm{g}\mathrm{c}}}{\mathrm{d}\mathrm{t}}}$$

(6)

In the MOS–bipolar structure illustrated in Figure 1a, the gate–source voltage V_gs exerts a negative feedback effect on the drain–source voltage V_ds. The BJT amplifies the base input current signal, which is then fed back to the drain–source voltage V_ds through the feedback loop involving R_L:

$${\displaystyle \frac{\mathrm{d}{\mathrm{V}}_{\mathrm{d}\mathrm{s}}}{\mathrm{d}\mathrm{t}}}\cong \mathrm{}-\mathrm{}{\mathrm{A}}_{\mathrm{V}}{\displaystyle \frac{\mathrm{d}{\mathrm{V}}_{\mathrm{g}\mathrm{s}}}{\mathrm{d}\mathrm{t}}}$$

(7)

The magnitude of A_V is contingent on the load resistance R_L and the feedback effect represented by the current gain β of the transistor T. It has been demonstrated that an increase in R_L and β results in a more pronounced effect of V_gs on V_ds through feedback, thereby increasing A_V. It can thus be concluded that the gate current, Igate, of the MOS–bipolar structure is as follows:

$${\mathrm{I}}_{\mathrm{g}\mathrm{a}\mathrm{t}\mathrm{e}}={\mathrm{C}}_{\mathrm{g}\mathrm{d}}\left({\displaystyle \frac{\mathrm{d}{\mathrm{V}}_{\mathrm{g}\mathrm{s}}}{\mathrm{d}\mathrm{t}}}\mathrm{}-\mathrm{}{\displaystyle \frac{\mathrm{d}{\mathrm{V}}_{\mathrm{d}\mathrm{s}}}{\mathrm{d}\mathrm{t}}}\right)+{\mathrm{C}}_{\mathrm{g}\mathrm{s}}{\displaystyle \frac{\mathrm{d}{\mathrm{V}}_{\mathrm{g}\mathrm{s}}}{\mathrm{d}\mathrm{t}}}=\left({\mathrm{C}}_{\mathrm{g}\mathrm{d}}+{\mathrm{C}}_{\mathrm{g}\mathrm{s}}+{\mathrm{A}}_{\mathrm{V}}{\mathrm{C}}_{\mathrm{g}\mathrm{d}}\right){\displaystyle \frac{\mathrm{d}{\mathrm{V}}_{\mathrm{g}\mathrm{s}}}{\mathrm{d}\mathrm{t}}}$$

(8)

Equation (8) illustrates the impact of the Miller effect on the input capacitance in the MOS–bipolar structure. The input capacitance C_iss measured with the source and drain shorted is equivalent to (C_gd + C_gs). However, due to the gate–drain capacitance C_gd bridging the input and output ends, it is amplified by a factor of (1 + A_V) under feedback, thereby increasing the effective input capacitance when the circuit is turned on and turned off. The Miller effect extends the charging and discharging time of the input capacitance in the MOS–bipolar structures, resulting in a delay in the propagation of the gate voltage waveform during switching. This delay is known as the Miller plateau [21], and its presence can be observed in the rising and falling edges of gate voltage. In order to mitigate the impact of the Miller effect on the switching performance of the MOS–bipolar structure, it is imperative that the values of R_L and β are not excessively high, thus avoiding the occurrence of excessive feedback.

A comparison of Equations (6) and (8) shows that under ideal conditions, the VFET–DT structure is free from the Miller effect, which indicates that the VFET–DT structure can achieve higher switching speed than the MOS–bipolar structure. In practice, the parasitic resistance of the transmission line and the BJT’s emitter junction resistance r_be will cause a certain voltage drop when the VFET is conducting. This will lead to fluctuations in the anode–cathode voltage V_ac. However, given that V_ac is high (typically over several hundred volts), the approximation of the ideal case remains valid. The VFET–DT’s inherent immunity to the Miller effect renders it well suited for high-power applications, enabling the design of high current gain β′ and high load resistance R_L. Furthermore, the VFET, operating on the basis of field emission principles, exhibits a complete absence of leakage current in the off state. This configuration enables higher gain in the cascaded Darlington structure without the concern of amplifying both leakage and output currents, as seen in the MOS–bipolar structure. This feature suggests that the VFET–DT structure exhibits considerable potential for utilization in high-power applications.

3. Results and Discussion

The construction of a power switch circuit based on the VFET–DT structure was undertaken using the Multisim software (Application version: 14.0.1 (14.0.1081), Database version: 14.0.b), as illustrated in Figure 2. The VFET and BJT components utilized in this study are derived from the Multisim database and are based on real electronic components that exist physically, rather than being purely modeled. A WE300B-type VFET is used on the input side (specific parameters are provided in Appendix A). A maximum cathode emission current of 200 mA can be achieved at the rated anode voltage of 650 V. The gate voltage is set to negative in order to prevent the electrons from being intercepted by the gate and forming a leakage gate current. Consequently, the input power consumption of the gate is essentially zero. A similar vacuum transistor planar structure using a carbon nanotube cold cathode was fabricated in our previous work [22]. The output end incorporates a bipolar Darlington transistor, which is arranged in a cascading configuration with transistors designated as T1 and T2 (transistor type: BUH100G; see Appendix A). A sampling resistor, designated as RS, is inserted between the VFET and transistor T1 with the objective of measuring the base drive current I_B supplied by the VFET. BJTs exhibit a charge storage effect, which affects the overall turn-off speed of the device. By connecting external diodes D1 and D2 to provide a reverse drive current to the bases of T1 and T2, the removal of stored charges is accelerated, thereby improving the overall turn-off speed of the device.

The drive circuit can be subdivided into two sections. The gate voltage of the VFET (V_gate) is controlled by a branch containing an n-channel enhancement-type MOSFET, which switches levels under the signal from the function signal generator XFG1. Diodes D1 and D2 are connected to a p-channel depletion-type MOSFET, which in turn is connected to the negative voltage source V_off. The function of the MOSFET is to provide the reverse current required to turn off the drive transistors. The power consumption of the drive circuit is the source of power consumption at the input end, which is 0.85 W under DC conditions and 0.425 W under pulse conditions (with a duty cycle D = 50%). The simulation is based on the assumption that a default case temperature of 27 °C applies, on the premise that high-power BJTs are characterized by effective heat dissipation conditions. It is imperative to note that all parameters are set below the rated values to ensure that all components operate safely.

By replacing the XFG1 with a fixed 10 V DC voltage source, the static characteristics of the VFET–DT can be measured. Figure 3a illustrates the effect of varying the gate voltage V_{gate_on} on the output current I_B of the VFET and the equivalent output current I_C of the DT (the sum of the collector currents of T1 and T2). When V_{gate_on} is below −103 V, both I_B and I_C are essentially zero, indicating that the VFET–DT is turned off. As V_{gate_on} increases, I_B exhibits an upward trend, reaching a maximum of 160 mA at V_{gate_on} = −70 V. Meanwhile, I_C grows rapidly over the range of V_{gate_on} from −103 V to −88 V, then saturates at 10 A and remains constant regardless of any subsequent increase in V_{gate_on}. The VFET–DT is fully turned on at this point. It demonstrates that the VFET–DT exhibits excellent switching characteristics, with the capacity to switch between a narrow gate voltage range.

Figure 3b illustrates the output characteristic of the VFET–DT, showing the relationship between the output current I_C and the forward voltage drop V_CE. For different gate voltages V_{gate_on}, the I_C–V_CE curves exhibit different operating modes of the DT. In the event of V_{gate_on} being set to −103 V, the DT operates in the cutoff region with I_C fixed at 0. This indicates that the VFET–DT is in the off state. In the event of V_{gate_on} being set to −88 V, the DT operates in the saturation region, with V_CE falling below 1 V. In this case, I_C rises sharply with increasing V_CE, and the I_C–V_CE curve is not controlled by V_{gate_on}. This indicates that the VFET–DT is in the on state. When V_{gate_on} is between −103 V and −88 V, I_C gradually reaches a steady value as V_CE increases. The maximum current that I_C can reach is mainly determined by V_{gate_on}. During this phase, DT enters the active region, corresponding to the switching process of the VFET–DT. At this stage, both V_CE and I_C are relatively high, and the switching losses generated are the main source of power consumption for the VFET–DT.

The operating characteristics of the internal components of the VFET–DT were measured at V_out = 400 V and R_L = 40 Ω (see Figure 4). The relationship between the current gains β₁ and β₂ of transistors T1 and T2 and the output current I_C of the VFET–DT is shown in Figure 4a. The current gain β′ of the DT is determined by β₁ and β₂ according to Equation (1). As I_C decreases from 9.978 A to 9.974 A, β₁ increases rapidly from 4.76 to 18.84, while β₂ remains stable at around 10. This phenomenon can be attributed to the decrease in I_B, which causes a transition from the saturation region to the active region for T1. Consequently, this transition leads to a significant rise in β₁. In the Darlington structure, the collector–base voltage of T2 is equivalent to the collector–emitter voltage of T1, so the collector junction of T2 remains reverse-biased. Therefore, it can be concluded that T2 always operates within the active region. The reduction in I_B is compensated by the gain of T1, resulting in a relatively stable β₂. It is evident that the cascaded amplification of T1 and T2 gives the DT a maximum current gain of β′ = 220 under steady-state conduction conditions at I_C = 9.97 A.

The output characteristic of the VFET is shown in Figure 4b. The influence of the parasitic resistance of the transmission line can be estimated by setting a sampling resistor RS (assuming RS = 1 Ω). When V_{gate_on} is below −103 V, there is no output current I_B of the VFET. The induced potential at the cathode decreases slightly with the reduction in V_{gate_on}, and the anode–cathode voltage V_ac reaches a maximum of 404.3 V (indicated by the red circle). As V_{gate_on} exceeds −103 V and continues to increase, the VFET turns on, I_B gradually increases, and the voltage across RS rises, causing V_ac to decrease. The inset in Figure 4b shows the V_ac–I_B curve under the on-state conditions (a local enlargement excluding the red circle), where the drop in V_ac becomes progressively smaller as I_B increases. The results have demonstrated that V_ac remains essentially around 400 V in both the on and off states of the VFET. Therefore, Equation (5) is still approximately valid when the transmission line parasitic resistance is less than 1 Ω.

The dynamic characteristics of the VFET–DT were measured at a duty cycle of D = 50% and a frequency of f = 10 kHz and 100 kHz. The load resistance R_L was set to 20 Ω in order to achieve higher output power under the pulse-driven conditions, and the gate voltages V_{gate_on} and V_{gate_off} were set to −70 V and −110 V, respectively. The waveform of the VFET output current I_B(on) was measured via the voltage across RS (as shown by the black line in Figure 5), which describes the on-state drive current at the base of the DT. The base current I_B is 0.158 A during the steady on state of the VFET. The overshoot and oscillations on the rising and falling edges of the I_B(on) waveform are due to the cathode–gate capacitance, C_gc, of the VFET. The average power dissipation of VFET is 31.6 W at D = 50%, with the majority of this dissipation occurring during the on state and being irrelevant to the switching process. As a trade-off for eliminating the Miller effect, the output current of the VFET is not fully utilized by the load resistance R_L, which reduces the energy conversion efficiency of V_out. However, the drive loss of the gate input terminal remains low at 0.425 W at D = 50% due to the absence of the Miller effect, ensuring the reliability of the small-signal drive circuit even under high-speed switching conditions.

During the on state of the VFET–DT, a maximum output current of I_CM = 19.93 A and a minimum forward voltage drop of V_CE(sat) = 1.316 V can be achieved in the I_C and V_CE waveforms (green and red lines in Figure 5). In the off state of the VFET–DT, I_C turns to zero, and all of V_out is applied to the VFET–DT. This phenomenon results in a maximum V_CE = 400 V. The rising and falling edges of the I_C and V_CE waveforms become smoother as f increases from 10 kHz to 100 kHz. This observation means that the delay time of the switching process increases. The widths of the rising and falling edges of the V_CE waveform in Figure 5 were measured, and the corresponding delay times in the turn-on and turn-off processes are shown in

Table 1. Dynamic characteristics of VFET–DT.

Switching Condition	f = 10 kHz, D = 50%	f = 100 kHz, D = 50%
Base current IB, A	0.158
Average power loss of VFET, W	31.6
Maximum output current ICM, A	19.93
Forward voltage drop VCE(sat), V	1.316
Turn-on time ton, ns	164	285.2
Turn-off time toff, ns	118	145.7
Switching time tsw, ns	282	430.9
Average power loss of DT, W	16.2	43.1
Total power loss of VFET–DT, W	48.225	75.125

. The power dissipation waveform of the DT (P_DT, blue line in Figure 5) can be obtained by multiplying the I_C and V_CE waveforms, and the average power loss of DT is obtained by integrating the P_DT waveform over a single period and dividing by the period duration. The average power loss of the DT is 16.2 W at f = 10 kHz and 43.1 W at f = 100 kHz, which is less than the total dissipation (P_D = 100 W) of a single BJT.

The base–emitter voltage waveforms V_BE1 and V_BE2 of transistors T1 and T2 are illustrated in Figure 6. The waveform V_BE1 is modulated by the waveform I_B(on), as illustrated in Figure 5, for which they exhibit a comparable morphology. The overshoot spikes in the rising edge of waveform V_BE1 and I_B(on) are caused by the charging behavior of the parasitic capacitance of VFET (see Appendix A). The base and emitter of T1 are connected to V_off through diodes D1 and D2, respectively. During the turn-off period, the potentials of the base and emitter of T1 are identical, resulting in the value of V_BE1 being zero. However, during the turn-off period, V_BE2 is −4.3 V (with a diode D2 voltage drop of 0.7 V), for which in the T2, the emitter is grounded while the base is connected to V_off. Consequently, both transistors T1 and T2 are in the cutoff region when VFET–DT is in the off state. When the VFET–DT is in the on state, both V_BE1 and V_BE2 are 0.16 V, indicating that the emitter junctions of T1 and T2 are forward-biased. As was discussed in the preceding paragraph, transistors T1 and T2 function in the saturation region and the active region, respectively.

4. Conclusions

A novel VFET–DT structure, which integrates a VFET and a DT with the advantages of gate voltage control, large power capacity, and high frequency, was introduced. The configuration, theory, and simulation results of the static/dynamic characteristics of the VFET–DT were reported. Through mathematical derivation, it was proven that the immunity to the Miller effect of VFET–DT is superior to the traditional MOS–bipolar structure in high-frequency applications. Taking advantage of this, the VFET–DT was able to operate over a wide frequency range from DC to 100 kHz while maintaining a high-power capability of 20 A and 400 V. The low forward voltage drop V_CE(sat) and short delay time allow the VFET–DT device to have a low power dissipation of 75.125 W at a high switching frequency of 100 kHz. The results demonstrated that the combination of vacuum and solid-state transistors enhances the performance of the power switch. This would make it suitable for applications requiring high-voltage transformation and high-frequency conversion, such as industrial control, automotive electronics, and home appliances. Further experimental verification of the performance of the VFET–DT structure will be carried out in the near future.