A Critical Review of Techniques for the Experimental Extraction of the Thermal Resistance of Bipolar Transistors from DC Measurements—Part II: Approaches Based on Intersection Points

Abstract

This work constitutes Part II of a comprehensive three-part study critically reviewing techniques for the indirect extraction of the thermal resistance in bipolar transistors using simple DC current/voltage measurements. While Part I focused on thermometer-based methods, this study examines techniques that rely on intersection points between electrical characteristics. The accuracy of these methods is assessed by applying them to DC curves obtained through PSPICE simulations of an in-house transistor model incorporating nonlinear thermal effects, and comparing the extracted thermal resistance data with the thermal resistance formulation embedded in the model. An InGaP/GaAs HBT and a Si/SiGe HBT for high-frequency applications are considered as case-studies. The analysis highlights key drawbacks affecting the methods, including theoretical approximations and sensitivity to the selection of intersection points. Among the techniques examined, only one adequately accounts for the nonlinear thermal behavior, though its original formulation presents practical limitations. To tackle this problem, we propose an improved and refined version of the approach that offers enhanced accuracy at the cost of increased complexity.

1. Introduction

Electrothermal (ET) effects are of paramount importance in modern high-speed bipolar transistors, regardless of technology. The multiple adverse consequences of strong ET feedback can be broadly categorized as follows. In single-finger devices, ET effects distort the $I-V$ characteristics, altering the DC bias and shrinking the safe operating area [1,2,3,4,5,6]; in multi-finger devices, the ET feedback can cause current hogging, in turn leading to performance reduction, and, in severe cases, to irreversible failure [7,8,9,10,11,12,13,14,15,16]; the characteristics of analog electronic building blocks in bipolar technology are modified, which compromises their performance [17]; the small-signal low-frequency response of individual devices may also deteriorate [18]; finally, the cut-off frequency can drop, as dictated by the higher scattering rate [19].

The pronounced ET effects in modern bipolar devices stem from their high operating current (and power) densities and self-heating thermal resistances.

The current densities are steadily increasing as a consequence of miniaturization and advanced doping approaches, driven by the need for faster switching speeds. Meanwhile, high thermal resistance values emerge from various technology-related factors. Gallium arsenide (GaAs)-based heterojunction bipolar transistors (HBTs) like InGaP/GaAs and AlGaAs/GaAs suffer from high thermal resistances due to (i) the low thermal conductivity of the GaAs substrate compared to silicon, (ii) the lateral heat confinement induced by mesa isolation, and (iii) the presence of interlevel dielectric films [6,7,8,9,10,11,12,13,16,17,20,21,22]. These thermal resistances are further growing due to the scaling efforts aimed at extending the device bandwidth, resulting in higher power densities for a given level of dissipated power. In silicon/silicon-germanium (Si/SiGe) HBTs for mm-wave and near-THz applications, namely, wireless and optical communication, medical equipment, and automotive radars, thermal resistances have rapidly increased due to technology strategies focused on enhancing frequency performance. These include (i) the adoption of oxide-based shallow/deep trenches and reduction of the spacing between intrinsic transistor and trenches, which hampers the lateral heat propagation away from the power dissipation region, and (ii) the horizontal scaling of the emitter, which drives higher current (and power) density. Such factors have contributed to push the thermal resistances of single-finger Si/SiGe HBTs into the range of thousands of K/W [19,23,24,25,26,27,28,29].

Accurately estimating the thermal resistances of individual bipolar transistors with experimental procedures is of utmost importance, as this would improve the self-heating description in compact device models used for computer aided design simulations.

In Part I of this work [30], it was clarified that indirect thermal resistance extraction techniques based on DC current/voltage measurements are very popular due to their simplicity and the cost-effectiveness of the equipment required, in contrast to direct methods (relying on infrared imaging and liquid crystal) and to indirect low-frequency AC or pulsed approaches. It was also pointed out that indirect techniques can be in turn subdivided into

• Techniques using a thermometer, i.e., the relation between a temperature-sensitive electrical parameter (TSEP), typically the base-emitter voltage $V_{BE}$, and the average temperature over the base-emitter junction $T_j$ [26,31,32,33,34,35,36,37,38].
• Techniques exploiting intersection points [27,29,39,40,41].
• Techniques based on the measurement of the base current $I_B$ [42,43,44,45,46].
• A technique relying on analytical assumptions that allows for the full evaluation of nonlinear thermal effects [47].

Part I of this work was exclusively focused on thermometer-based techniques; in that paper, we explored the principles behind those methods and discussed their advantages and limitations.

In this follow-up paper, we expand on the analysis by introducing and critically comparing techniques that rely on intersection points. Such approaches are worthy of attention since they are believed to offer good accuracy by eliminating thermometer-related uncertainties, as stated in [29,40].

The remainder of this paper is structured as follows. Section 2 provides an extensive theoretical background, including the definition of thermal resistance, an explanation of the physics governing nonlinear thermal effects, and a description of the most accurate strategy for modeling them. Section 3 revisits some important features of the devices under test (already described in Part I [30] and references therein) and outlines the circuit-based simulation methodology used to assess the accuracy of the analyzed techniques, enabling an objective and rigorous comparison. Section 4 offers a tutorial-style overview of the theoretical foundations of these techniques with a unified nomenclature and highlights their limitations and approximations. The techniques are then applied to the simulated characteristics of the devices under test, and the results are discussed. Section 5 concludes the paper.

2. Thermal Resistance: Theoretical Background

As mentioned in Section 1, the most important parameter describing the static heat removal in an electronic device is the (self-heating) thermal resistance $R_{TH}$ [K/W], which is an indicator of the inability of the component to transfer heat from the power dissipation region (simply denoted as heat source in the following) to the environment. By specifically referring to a bipolar transistor, $R_{TH}$ is defined as

$$R_{TH}={\displaystyle \frac{T_j-T_B}{P_D}}={\displaystyle \frac{\mathrm{\Delta }{T}_j}{P_D}}$$

(1)

where $T_j$ [K] is the temperature averaged over the base-emitter junction, $T_B$ [K] is the temperature of the substrate backside (imposed by a thermochuck or heater), and $P_D$ [W] is the dissipated power, given by

$$P_D=I_B\cdot V_{BE}+I_C\cdot V_{CE}=I_E\cdot V_{BE}+I_C\cdot V_{CB}$$

(2)

where $I_B$, $I_C$, $I_E$ [A] are the base, collector, and emitter currents, and $V_{BE}$, $V_{CE}$, $V_{CB}$ [V] are the base-emitter, collector-emitter, and collector-base voltages.

The definition (1) is commonly accepted since the electrical characteristics of a bipolar transistor significantly depend on $T_j$.

The thermal resistance depends on (i) device and heat source geometry, (ii) thermal conductivities of the materials through which heat dissipates from the source, and (iii) boundary conditions. A transistor with a horizontally- and/or vertically-scaled heat source suffers from a higher $R_{TH}$ since for the same $P_D$ the dissipated power density is higher, and therefore also $T_j$ is higher. Similarly, the adoption of materials with low thermal conductivities hinders the heat flow, thus leading to an increase in $R_{TH}$.

In addition, it must be considered that the thermal conductivities $k$ [W/µmK] of materials traversed by the heat flow in a transistor decrease with temperature ([48] and references therein), thereby lowering the heat transfer efficiency. The thermally-induced $k$ degradation introduces a nonlinearity in the heat conduction equation, and the resulting effects are referred to as nonlinear thermal effects. The device temperature in turn increases for two distinct physical mechanisms: (i) the raise in backside temperature $T_B$ (nonlinear thermal effect due to backside temperature) in the absence of power dissipation and (ii) the increase in dissipated power $P_D$ (nonlinear self-heating effect). Consequently, $R_{TH}$ is a monotonically-growing function of both $T_B$ and $P_D$, and it should be more properly formulated as $R_{TH}\left(T_B,P_D\right)$, where the dependence on $T_B$ and $P_D$ implicitly comes from the $k$ reduction with increasing temperature [48,49]. Consequently, from (1),

$$T_j=T_B+R_{TH}\left(T_B,P_D\right)\cdot P_D$$

(3)

Let us denote as $T_0$ the temperature used as a reference, equal to 300 K in our analysis. Henceforth, $R_{TH00}$ will conventionally denote the thermal resistance of the bipolar transistor at $T_B=T_0$ and very low $P_D$ (ideally for $P_D\to 0 \mathrm{W}$, i.e., in the absence of the nonlinear self-heating effect), that is,

$$R_{TH00}=R_{TH}\left(T_B=T_0,P_D\to 0\right)$$

(4)

In simple words, $R_{TH00}$ would be the thermal resistance of the transistor if the thermal conductivities of all materials were ideally equal to their $k\left(T_0\right)$ value.

In [29,33,49,50], the following theoretical approach was used to account for both nonlinear thermal effects. The low-power thermal resistance $R_{THB0}=R_{TH}\left(T_B,P_D\to 0\right)$ at an arbitrary $T_B$ in the range 250 to 450 K (nonlinear thermal effect due to the backside temperature) can be expressed as

$$R_{THB0}=R_{TH00}\cdot {\left({\displaystyle \frac{T_B}{T_0}}\right)}^{\alpha }$$

(5)

where $\alpha$ (>0) is a dimensionless fitting parameter. The further thermal resistance growth due to the increase in $P_D$ (nonlinear self-heating effect) can be accounted for by invoking Kirchhoff’s transformation [51,52] as

$$R_{TH}\left(T_B,P_D\right)={\displaystyle \frac{T_B}{P_D}}\cdot \left\{{\left[1-\left(\alpha -1\right)\cdot {\displaystyle \frac{R_{THB0}\cdot P_D}{T_B}}\right]}^{{\displaystyle \frac{-1}{\alpha -1}}}-1\right\}$$

(6)

with $\alpha$ being the same parameter applied in (5). Using (5) in (6), the following $R_{TH}$ expression is obtained:

$$R_{TH}\left(T_B,P_D\right)={\displaystyle \frac{T_B}{P_D}}\cdot \left\{{\left[1-\left(\alpha -1\right)\cdot {\displaystyle \frac{R_{TH00}\cdot P_D}{T_B\cdot {\left(\frac{T_0}{T_B}\right)}^{\alpha }}}\right]}^{{\displaystyle \frac{-1}{\alpha -1}}}-1\right\}$$

(7)

Such an approach can also be referred to as single-semiconductor assumption, as it implicitly considers the device to be homogeneously composed of only one semiconductor, the thermal conductivity of which obeys

$$k\left(T\right)=k\left(T_0\right)\cdot {\left({\displaystyle \frac{T}{T_0}}\right)}^{-\alpha }$$

(8)

with $\alpha$ being a fitting parameter. In [48], an extensive numerical analysis relying on 3-D finite-element method simulations allowed verifying that the single-semiconductor assumption correctly works for InGaP/GaAs and Si/SiGe HBT technologies. Consequently, such an approach, already exploited for Part I of this work, will also be used for the following analysis.

It is worth noting that many papers use the ambient temperature $T_{amb}$ instead of the substrate backside temperature $T_B$ in the above formulas [18,29,33,40,50]. This is justified since, under low-power dissipation, the device temperature is uniform and closely follows the externally-imposed boundary condition—whether it is the backside temperature set by a thermochuck or the ambient temperature of the surrounding environment when no active thermal control is applied.

3. Devices Under Test and Methodology

3.1. Devices Under Test

Similar to [30,48], the analysis was conducted on two NPN HBT technologies, namely, a mesa-isolated InGaP/GaAs NPN HBT with four 2 × 20.5 µm² emitter fingers fabricated by Qorvo (Greensboro, NC, USA) and a Si/SiGe NPN HBT with a drawn emitter area equal to 0.2 × 2.8 µm² manufactured by Infineon Technologies AG (New Bieberg, Germany) in the framework of the European Project DOTFIVE. The choice fell on these technologies since they suffer from pronounced electrothermal effects compared to conventional Si bipolar junction transistors (BJTs), which only find use in low-cost and low-frequency applications. The most important figures of merit of the devices under test are listed in

Table 1. Key features of the InGaP/GaAs NPN HBT under test.

Parameter	Value
Common-emitter current gain βF at 300 K and medium current levels	150
Open-emitter breakdown voltage BVCBO	27 V
Open-base breakdown voltage BVCEO	17 V
Peak cut-off frequency fT for VCE = 3 V	40 GHz
Collector current density JC at peak fT for VCE = 3 V	0.2 mA/µm2
Maximum oscillation frequency fMAX for VCE = 3 V	82 GHz

and

Table 2. Key features of the Si/SiGe NPN HBT under test.

Parameter	Value
Common-emitter current gain βF at 300 K and medium current levels	2200
Open-emitter breakdown voltage BVCBO	5.5 V
Open-base breakdown voltage BVCEO	1.6 V
Peak cut-off frequency fT for VCB = 0.5 V	240 GHz
Collector current density JC at peak fT for VCB = 0.5 V	10 mA/µm2
Maximum oscillation frequency fMAX for VCB = 0.5 V	380 GHz

. Additional details are reported elsewhere ([16] for the InGaP/GaAs HBT and [26] for the Si/SiGe HBT) and will be omitted here for the sake of brevity.

3.2. Methodology

The DC behavior of both devices under test was described by means of an analytical model developed in-house in the framework of our research activities. The model is simple, accurate enough, and enables a low-effort parameter extraction procedure, thus ensuring high flexibility throughout the whole investigation. It accounts for all the physical mechanisms influencing the forward active mode, namely, high-current (Kirk, resistive) effects, Early effect, avalanche multiplication due to reiterate impact ionization (hereinafter simply denoted as avalanche effect), and includes the temperature dependence of all the temperature-sensitive parameters. All the model details can be found in Section 3.2 of Part I [30].

The model was implemented in the popular PSPICE circuit simulator [53] as a subcircuit connected to a thermal feedback block (TFB), where the ET feedback is accounted for by invoking the thermal equivalent of Ohm’s law: a temperature rise is a voltage drop, a dissipated power is a current, a thermal resistance is an electrical resistance.

The subcircuit makes use of the standard bipolar transistor instance as a core component at temperature $T_0$, and, besides the collector, emitter, and base terminals, it is equipped with an additional (input) thermal node and an extra (output) power node. The thermal node is fed with the junction temperature rise above backside $\mathrm{\Delta }{T}_j=T_j-T_B$ (a voltage drop), while the power node provides the dissipated power $P_D$ (a current), internally computed according to (2). Apart from the standard transistor, the subcircuit is enriched with linear/nonlinear controlled voltage/current sources. These are adopted (i) to account for high-current, Early, and avalanche effects and (ii) to enable the variation of the temperature-sensitive parameters during the simulation run.

The TFB is based on a nonlinear voltage source [30] implementing (7) (which describes the impact of both nonlinear thermal effects on $R_{TH}$) and it is connected to the power node and the thermal node of the device subcircuit. Given the dissipated power $P_D$, the TFB computes the temperature rise $\mathrm{\Delta }{T}_j$ that is fed back to the thermal node, thus modifying the temperature-sensitive parameters.

In simple words, the connection of subcircuit and TFB gives rise to an ET transistor model based on the thermal equivalent of Ohm’s law, the solution of which is delegated to the optimized and robust PSPICE engine (in principle any other circuit simulation package can be used) without occurrence of convergence issues. With this approach, it is very simple (i) to monitor the behavior of any quantity of interest, e.g., currents/voltages at the terminals, dissipated power, junction temperature, avalanche current, forward current gain, voltage drop across the parasitic resistances, and (ii) to assess the impact of an individual physical mechanism.

The electrical parameters of the model and their temperature dependence, as well as the thermal resistance parameters $R_{TH00}$ and $\alpha$ in (7), were properly tailored for both bipolar technologies under test to ensure a fairly good agreement with experimental data [30]. More specifically, $R_{TH00}=460\hspace{0.33em}\mathrm{K}/\mathrm{W}$, $\alpha =0.95$ for the InGaP/GaAs HBT and $R_{TH00}=6855.8\hspace{0.33em}\mathrm{K}/\mathrm{W}$, $\alpha =1.333$ for the Si/SiGe HBT, as carefully determined from a simulation campaign performed in [48] with COMSOL 5.3a [54].

Then, DC ET simulations of the transistor models are performed in PSPICE to emulate the experimental current/voltage data needed for the application of the extraction techniques based on intersection points (Section 4). The extracted $R_{TH}$ results are then compared to the reference (equivalently denoted as target) data resulting from (7) with the calibrated $R_{TH00}$ and $\alpha$ values embedded in the transistor model. This is equivalent to feeding the techniques with ideal (noiseless) measurements; as a consequence, any disagreement between the extracted data and the reference (7) is only ascribable to the nature of the adopted extraction technique. The approach of using simulation current/voltage data (also referred to as synthetic data) based on a known target formulation has been already applied in many previous papers dealing with bipolar transistors [27,29,38,55,56].

4. Analysis of Experimental R_TH Extraction Techniques Based on Intersection Points

In this section, the extraction techniques relying on intersection points are discussed in chronological order by using a unified and comprehensible nomenclature. First, the theory behind them is explained in detail; then, the techniques are applied to synthetic current/voltage data obtained with DC ET PSPICE (version 16.5) simulations of the transistor models corresponding to the devices under test; finally, the extracted data are compared to the target formulations included in the transistor models.

4.1. Liu and Yuksel [39]

As a first step, Liu and Yuksel [39] measure the $V_{CE}$-constant $I_C-V_{BE}$ characteristics at various $T_B$ values (denoted as calibration curves), the $V_{CE}*$ value being sufficiently high to ensure forward mode operation, but low enough to prevent the avalanche effect. They observe a well-known behavior, that is, at a given $I_C$, $V_{BE}$ decreases with increasing $T_B$ (e.g., [30]). Subsequently, they measure the $I_C-V_{BE}$ curves at $T_B=T_0$ and various $V_{CE}$ values over a range within which avalanche can be reasonably disregarded; such characteristics are obtained by sweeping $I_B$, which allows observing the occurrence of flyback (also referred to as snapback or turnover) points beyond which a thermally-dictated negative differential branch takes place.

By reporting the two families of characteristics in the same graph, some intersection points between the first and the second family can be spotted. The authors assume that, by neglecting the Early and avalanche effects, the collector current $I_C$ can be expressed as

$$I_C=I_B\left(V_{BE},T_j\right)\cdot {\mathsf{\beta }}_F\left(I_C,T_j\right)$$

(9)

By choosing an intersection point A corresponding to a selected current $I_C*$, and considering that at this point the characteristic belonging to the first (at $T_B=T_{BA}$, $V_{CE}=V_{CE}*$) and to the second (at $T_B=T_0$, $V_{CE}=V_{CEA}$) family share the same ($V_{BE},I_C*$) couple, (9) implies that also the junction temperature $T_j$ is the same; using (3), this can be expressed as

$$T_0+R_{TH}\left(T_0,P_{DA}\right)\cdot V_{CEA}\cdot I_C*=T_{BA}+R_{TH}\left(T_{BA},P_D*\right)\cdot V_{CE}*\cdot I_C*$$

(10)

where use has been made of the approximation $P_D\approx V_{CE}\cdot I_C$, so that $P_D*\approx V_{CE}*\cdot I_C*$ on the calibration curve at $T_B=T_{BA}$, and $P_{DA}\approx V_{CEA}\cdot I_C*$ on the characteristic measured at $T_B=T_0$, $V_{CE}=V_{CEA}$.

Liu and Yuksel neglect the dependence of $R_{TH}$ on the backside temperature $T_B$. Thus, (10) becomes

$$T_0+R_{TH}\left(T_0,P_{DA}\right)\cdot V_{CEA}\cdot I_C*=T_{BA}+R_{TH}\left(T_0,P_D*\right)\cdot V_{CE}*\cdot I_C*$$

(11)

Then, other intersection points B, C, D, … corresponding to $I_C*$ are identified, such that

$$T_0+R_{TH}\left(T_0,P_{DB}\right)\cdot V_{CEB}\cdot I_C*=T_{BB}+R_{TH}\left(T_0,P_D*\right)\cdot V_{CE}*\cdot I_C*$$

(12)

$$T_0+R_{TH}\left(T_0,P_{DC}\right)\cdot V_{CEC}\cdot I_C*=T_{BC}+R_{TH}\left(T_0,P_D*\right)\cdot V_{CE}*\cdot I_C*$$

(13)

$$T_0+R_{TH}\left(T_0,P_{DD}\right)\cdot V_{CED}\cdot I_C*=T_{BD}+R_{TH}\left(T_0,P_D*\right)\cdot V_{CE}*\cdot I_C*$$

(14)

and so on. Afterward, the points ($T_{BA},V_{CEA}$), ($T_{BB},V_{CEB}$), ($T_{BC},V_{CEC}$), ($T_{BD},V_{CED}$), … are reported on a graph. From the resulting $T_B-V_{CE}$ behavior, it is possible to extrapolate the $T_B$ value corresponding to $V_{CE}\to 0$ ($P_D\to 0$), referred to as $T_{B0}$. An equation similar to (11), (12), (13), (14), … can be particularized to the couple ($T_{B0},V_{CE}\to 0$), that is,

$$T_0=T_{B0}+R_{TH}\left(T_0,P_D*\right)\cdot V_{CE}*\cdot I_C*$$

(15)

from which $R_{TH}\left(T_0,P_D*\right)$ can be determined as

$$R_{TH}\left(T_0,P_D*\right)={\displaystyle \frac{T_0-T_{B0}}{V_{CE}*\cdot I_C*}}$$

(16)

Once $R_{TH}\left(T_0,P_D*\right)$ is evaluated, from (11), (12), (13), (14), …, it is possible to calculate $R_{TH}\left(T_0,P_{DA}\right)$, $R_{TH}\left(T_0,P_{DB}\right)$, $R_{TH}\left(T_0,P_{DC}\right)$, $R_{TH}\left(T_0,P_{DD}\right)$, …, according to

$$\begin{array}{l}{R}_{TH}\left(T_0,P_{DA}\right)={\displaystyle \frac{T_{BA}+R_{TH}\left(T_0,P_D*\right)\cdot V_{CE}*\cdot I_C*-T_0}{V_{CEA}\cdot I_C*}}\\ R_{TH}\left(T_0,P_{DB}\right)={\displaystyle \frac{T_{BB}+R_{TH}\left(T_0,P_D*\right)\cdot V_{CE}*\cdot I_C*-T_0}{V_{CEB}\cdot I_C*}}\\ R_{TH}\left(T_0,P_{DC}\right)={\displaystyle \frac{T_{BC}+R_{TH}\left(T_0,P_D*\right)\cdot V_{CE}*\cdot I_C*-T_0}{V_{CEC}\cdot I_C*}}\\ R_{TH}\left(T_0,P_{DD}\right)={\displaystyle \frac{T_{BD}+R_{TH}\left(T_0,P_D*\right)\cdot V_{CE}*\cdot I_C*-T_0}{V_{CED}\cdot I_C*}}\end{array}$$

(17)

which allows obtaining the $R_{TH}$ vs. $P_D$ behavior, i.e., the dependence of $R_{TH}$ on the nonlinear self-heating effect. Then the procedure can be repeated by selecting other $I_C*$ values, thus enriching the $R_{TH}-P_D$ dataset.

This technique was first applied to the InGaP/GaAs HBT. Figure 1 shows the two PSPICE $I_C-V_{BE}$ curve families, namely, one obtained for $V_{CE}*=1.5\hspace{0.33em}\mathrm{V}$ by varying $T_B$ in the range 300 to 400 K with a $\mathrm{\Delta }{T}_B=10\hspace{0.33em}\mathrm{K}$ step, and another at $T_B=T_0=300\hspace{0.33em}\mathrm{K}$ by varying $V_{CE}$ in the range 2 to 10 V with a $\mathrm{\Delta }{V}_{CE}=0.5\hspace{0.33em}\mathrm{V}$ step. Four $I_C*$ values were selected, namely, $I_C*$ = 0.014, 0.02, 0.025, and 0.0345 A. Before proceeding with the application of the technique, we want to emphasize its main drawbacks: first, the relevant $R_{TH}$ dependence on $T_B$ is disregarded; in the second place, for an assigned $I_C*$ value, only one true intersection point between curves belonging to the two families can be found, while the other intersection points are approximate, as the two curves do not actually intersect (there is a small $\mathrm{\Delta }{V}_{BE}$ between the characteristics). These aspects will affect the extraction accuracy.

The thermal resistance $R_{TH}$ as a function of $P_D$, as determined by the extraction technique, is shown in Figure 2. In the same figure, also the reference behavior corresponding to (7) with $R_{TH00}=460\hspace{0.33em}\mathrm{K}/\mathrm{W}$, $\alpha =0.95$, and $T_B=T_0$ is represented. As can be seen, due to the aforementioned drawbacks, the technique yields rather inaccurate and noisy results.

Besides providing inaccurate data for the InGaP/GaAs HBT, the technique was revealed to be unviable for the Si/SiGe HBT under test, whose families of characteristics are shown in Figure 3. In this case, $V_{CE}$ cannot exceed 2.5 V, beyond which the junction temperature becomes intolerable and the avalanche effect plays a relevant role. Again, only one true intersection point can be spotted at an assigned $I_C*$, but, unlike the InGaP/GaAs transistor, there are no further approximate intersection points, which makes the technique inapplicable.

4.2. Marsh [40]

The technique developed by Marsh [40] is articulated as follows. Marsh proposes to measure three $I_C-V_{CE}$ characteristics by forcing the same $I_B$ at three backside temperatures $T_{B1}<T_{B2}<T_{B3}$. In HBTs, regardless of the specific technology, a negative-differential-resistance (NDR) region arises ($I_C$ reduces with $V_{CE}$) under forward mode due to the negative temperature coefficient of the current gain ${\mathsf{\beta }}_F$, in turn induced by the wider bandgap of the emitter compared to that of the base [57,58]. The presence of the NDR behavior could in principle allow the identification of three points corresponding to an assigned collector current $I_C*$ and different $V_{CE}$ values ($V_{CE1}>V_{CE2}>V_{CE3}$), in which the transistor dissipates powers $P_{D1}>P_{D2}>P_{D3}$. As $I_C$ and $I_B$ are the same at these points, ${\mathsf{\beta }}_F$ is the same. In the assumption of negligible Early and avalanche effects, ${\mathsf{\beta }}_F$ only depends on $T_j$, so that also $T_j$ is the same. Consequently, using (3), the following equations hold at the three points:

$$\begin{array}{l}{T}_j=T_{B1}+R_{TH}\left(T_{B1},P_{D1}\right)\cdot P_{D1}\\ T_j=T_{B2}+R_{TH}\left(T_{B2},P_{D2}\right)\cdot P_{D2}\\ T_j=T_{B3}+R_{TH}\left(T_{B3},P_{D3}\right)\cdot P_{D3}\end{array}$$

(18)

Marsh assumes that $R_{TH}$ is a linearly increasing function of $T_B$ while disregarding its $P_D$ dependence, that is,

$$R_{TH}\left(T_B,P_D\right)\approx R_{THB0}=A_{Marsh}+B_{Marsh}\cdot T_B$$

(19)

By substituting (18) into (19), it is obtained that

$$\begin{array}{l}{T}_j=T_{B1}+\left(A_{Marsh}+B_{Marsh}\cdot T_{B1}\right)\cdot P_{D1}\\ T_j=T_{B2}+\left(A_{Marsh}+B_{Marsh}\cdot T_{B2}\right)\cdot P_{D2}\\ T_j=T_{B3}+\left(A_{Marsh}+B_{Marsh}\cdot T_{B3}\right)\cdot P_{D3}\end{array}$$

(20)

which can be rewritten in the form

$$\begin{array}{l}{P}_{D1}\cdot A_{Marsh}+T_{B1}\cdot P_{D1}\cdot B_{Marsh}-T_j=-T_{B1}\\ P_{D2}\cdot A_{Marsh}+T_{B2}\cdot P_{D2}\cdot B_{Marsh}-T_j=-T_{B2}\\ P_{D3}\cdot A_{Marsh}+T_{B3}\cdot P_{D3}\cdot B_{Marsh}-T_j=-T_{B3}\end{array}$$

(21)

This represents a three-equation system with the three unknowns $A_{Marsh}$, $B_{Marsh}$, and $T_j$. By solving (21), it is possible to determine the junction temperature $T_j$ at the selected points and $R_{THB0}$ as a function of $T_B$ as given by (19). The linear relation (19) can also be rewritten as

$$R_{THB0}=A_{Marsh}+B_{Marsh}\cdot T_0+B_{Marsh}\cdot \left(T_B-T_0\right)=R_{TH00}+B_{Marsh}\cdot \left(T_B-T_0\right)$$

(22)

It is worth noting that in principle this technique can also be applied to Si BJTs, which show a positive-differential-resistance behavior in the $I_B$-constant $I_C-V_{CE}$ curve due to the positive temperature coefficient of ${\mathsf{\beta }}_F$, in turn induced by the narrower bandgap of the highly-doped emitter compared to that of the base; however, in this case the $R_{TH}$ extraction would be significantly affected by the Early effect, which is not accounted for in the approach and can be misinterpreted as an additional self-heating.

This method was first applied to the InGaP/GaAs HBT for $I_B$ = 0.3 and 0.5 mA, and $T_B$ = 300, 330, and 360 K. Figure 4 shows the $I_C-V_{CE}$ characteristics simulated with PSPICE, along with the intersection points obtained by selecting $I_C*=0.038$ and 0.06 A for the two $I_B$ values. Figure 5 illustrates the extracted $R_{TH}-T_B$ characteristics, which are difficult to interpret and to exploit for modeling purposes, since the dissipated power $P_D$ varies along them. We decided to compare such curves to the low-power $R_{THB0}$ reference given by (5) with $R_{TH00}=460\hspace{0.33em}\mathrm{K}/\mathrm{W}$ and $\alpha =0.95$, and, for the sake of completeness, also to the reference $R_{TH}$ values obtained from (7) by substituting $\left(T_{B1},P_{D1}\right)$, $\left(T_{B2},P_{D2}\right)$, $\left(T_{B3},P_{D3}\right)$, i.e., the target $R_{TH}$ values at the intersection points. As can be seen, the technique provides a slight underestimation of the target $R_{TH}$ data for the following reasons: the $R_{TH}$ dependence on $P_D$ is neglected in (21), and, to a lesser extent, the albeit very low Early effect leads to a small discrepancy in the junction temperatures at the three points $\left(T_{j1}>T_{j2}>T_{j3}\right)$.

Subsequently, the technique was tested on the Si/SiGe HBT. Unfortunately, in this technology, devices suffer from a significant avalanche effect at relatively low $V_{CE}$ values. As avalanche jeopardizes the accuracy of the approach, determining a proper combination of $I_B$ and $I_C*$ to safely apply the technique is a nontrivial task: on one hand, the ET effect should be significant (thus making the slope in the NDR region more pronounced); on the other hand, at the intersection point 1 on the $T_B=300\hspace{0.33em}\mathrm{K}$ characteristic, the avalanche effect must be negligible. For the specific device under test, we forced base currents of 30 and 40 µA, backside temperatures $T_B$ = 300, 320, 340 K, and $I_C*$ = 6.05 and 6.9 mA (for $I_B$ = 30 and 40 µA, respectively); the PSPICE characteristics, alongside the intersection points, are illustrated in Figure 6.

Figure 7 reports the extracted $R_{TH}$ vs. $T_B$ curves in comparison with the low-power $R_{THB0}$ reference behavior given by (5) with $R_{TH00}=6855.8\hspace{0.33em}\mathrm{K}/\mathrm{W}$ and $\alpha =1.333$, as well as with the reference $R_{TH}$ values in the intersection points, obtained from (7) by substituting $\left(T_{B1},P_{D1}\right)$, $\left(T_{B2},P_{D2}\right)$, and $\left(T_{B3},P_{D3}\right)$. It can be inferred that also in this case the technique slightly underestimates the target $R_{TH}$ values for the same reasons mentioned earlier.

4.3. Berkner [41]

The technique conceived by Berkner [41], subsequently also presented and adopted by Balanethiram et al. [27], can be described as follows. Under forward active mode, at $V_{BE}$ not too high to avoid high-current effects, if $V_{CB}$ is sufficiently low to lead to negligible Early and avalanche effects, the collector current is given by

$$I_C\left(V_{BE},T_j\right)=I_S\left(T_j\right)\cdot \exp \left({\displaystyle \frac{V_{BE}}{V_T}}\right)$$

(23)

The technique requires the measurement of two $V_{CE}$-constant $I_C-V_{BE}$ characteristics, the first obtained by assigning ($V_{CE1},T_{B1}$) and the second assigning ($V_{CE2},T_{B2}$), where $V_{CE1}<V_{CE2}$ and $T_{B1}>T_{B2}$. For low $V_{BE}$ values (low self-heating), the junction temperature $T_{j1}$ along the ($V_{CE1},T_{B1}$) curve is higher than the $T_{j2}$ associated to the ($V_{CE2},T_{B2}$) counterpart, as $T_{B1}>T_{B2}$ dominates with respect to $V_{CE1}<V_{CE2}$ ($P_{D1}<P_{D2}$ at the same $I_C$), that is, invoking (3),

$$T_{j1}>T_{j2}\hspace{1em}\iff \hspace{1em}{T}_{B1}+R_{TH}\left(T_{B1},P_{D1}\right)\cdot P_{D1}>\hspace{0.17em}{T}_{B2}+R_{TH}\left(T_{B2},P_{D2}\right)\cdot P_{D2}$$

(24)

On the other hand, by increasing $V_{BE}$, $P_{D2}$ grows faster than $P_{D1}$, thus leading to

$$T_{j1}<T_{j2}\hspace{1em}\iff \hspace{1em}{T}_{B1}+R_{TH}\left(T_{B1},P_{D1}\right)\cdot P_{D1}<T_{B2}+R_{TH}\left(T_{B2},P_{D2}\right)\cdot P_{D2}$$

(25)

As a result, there will be a value of $V_{BE}$ where $T_{j1}=T_{j2}$, that is,

$$T_{B1}+R_{TH}\left(T_{B1},P_{D1}\right)\cdot P_{D1}=T_{B2}+R_{TH}\left(T_{B2},P_{D2}\right)\cdot P_{D2}$$

(26)

In the assumption of validity of (23), this $V_{BE}$ value can be easily identified as the one at which the two characteristics intersect ($V_{BE1}=V_{BE2}$, $I_{C1}=I_{C2}$). Here, Berkner and Balanethiram et al. assume that $R_{TH}$ only depend on the junction temperature $T_j$ at the intersection point, i.e., $R_{TH}\left(T_{B1},P_{D1}\right)=R_{TH}\left(T_{B2},P_{D2}\right)=R_{TH}\left(T_j\right)$. Hence, (26) turns into

$$T_{B1}+R_{TH}\left(T_j\right)\cdot P_{D1}=T_{B2}+R_{TH}\left(T_j\right)\cdot P_{D2}$$

(27)

whence $R_{TH}\left(T_j\right)$ can be calculated as

$$R_{TH}\left(T_j\right)={\displaystyle \frac{T_{B1}-T_{B2}}{P_{D2}-P_{D1}}}$$

(28)

and the corresponding $T_j$ can be evaluated from either the LHS or RHS of (27). In [27], Balanethiram et al. suggest that repeating the procedure for different $T_B$ values, the $R_{TH}$ vs. $T_j$ behavior can be determined.

This technique seems to be well-suited for HBTs (where the Early effect plays a marginal role) and quite easy to apply. However, it is affected by an important theoretical weakness: the authors assume that $R_{TH}$ is only dependent on $T_j$, while in [48,49] it is clearly explained that $R_{TH}$ is not univocally determined by $T_j$, but separately depends on $T_B$ and $P_D$; more specifically, in [48] it is shown that for an assigned $T_j$, $R_{TH}$ can assume infinite values depending on the applied $T_B$. For this reason, the equality $R_{TH}\left(T_{B1},P_{D1}\right)=R_{TH}\left(T_{B2},P_{D2}\right)$ does not hold, and the extracted $R_{TH}-T_j$ behavior is questionable.

Due to its theoretical inconsistency, the technique was only applied to the InGaP/GaAs HBT. The first $I_C-V_{BE}$ curve was simulated by applying $V_{CE1}=1.5\hspace{0.33em}\mathrm{V}$, $T_{B1}=305\hspace{0.33em}\mathrm{K}$, and the second by applying $V_{CE2}=2\hspace{0.33em}\mathrm{V}$, $T_{B2}=T_0=300\hspace{0.33em}\mathrm{K}$. The extraction procedure was then executed by identifying the intersection points in a two-fold way: (i) without data interpolation, by taking the coordinates of the simulated point of the second curve closest to the first characteristic; with a careful data interpolation. Then, the process was repeated by determining again the first characteristic at $T_{B1}$ spanning 310 to 340 K with a $\mathrm{\Delta }{T}_{B1}=5\hspace{0.33em}\mathrm{K}$ step. All the characteristics and the identified intersection points are illustrated in Figure 8. Figure 9 reports the results. As can be seen, the adoption of data interpolation to find the intersection points in an accurate way plays a marginal role. Due to the theoretical flaw of the method, it was not clear with which reference data the extracted $R_{TH}-T_j$ should have been compared. We decided to compare it to the PSPICE-determined (i.e., the true) $R_{TH}-T_j$ characteristic corresponding to the curve evaluated for $V_{CE2}=2\hspace{0.33em}\mathrm{V}$, $T_{B2}=T_0=300\hspace{0.33em}\mathrm{K}$. As can be seen, the approach leads to a significant underestimation of the thermal resistance.

4.4. Huszka et al. [29]

Huszka and his co-workers [29] present an improved variant of the technique from Berkner [41], which deserves higher attention since, differently from [39,40,41], it accounts for the separate $R_{TH}$ dependence on $T_B$ and $P_D$. They recast (26) to obtain

$${\displaystyle \frac{T_{B1}-T_{B2}}{P_{D2}-P_{D1}}}={\displaystyle \frac{R_{TH}\left(T_{B2},P_{D2}\right)\cdot P_{D2}}{P_{D2}-P_{D1}}}-{\displaystyle \frac{R_{TH}\left(T_{B1},P_{D1}\right)\cdot P_{D1}}{P_{D2}-P_{D1}}}$$

(29)

where the LHS is the original Berkner’s thermal resistance given by (28). Then they propose using (7) for $R_{TH}\left(T_{B1},P_{D1}\right)$ and $R_{TH}\left(T_{B2},P_{D2}\right)$ so that (29) becomes an equation with the two unknowns $R_{TH00}$ and $\alpha$. The authors recommend to select two $V_{CE}$ values and to measure for each $V_{CE}$ a family of $I_C-V_{BE}$ characteristics by varying the backside temperature $T_B$ within a wide range. By plotting the two families of characteristics in the same graph, some intersection points can be found at assigned $I_C$ values. By using (29) for each point, an equation system with unknowns $R_{TH00}$ and $\alpha$ is obtained. Subsequently, $\alpha$ (considered as an input) is varied over a reasonably broad range, and parameter $R_{TH00}$ is optimized for each $\alpha$ to minimize the sum of the squared differences between the LHS and RHS of the entire equation system (single-variable least-squared based optimization). The input $\alpha$ and the $R_{TH00}$ ensuring the minimum error are finally chosen as guess values for a two-variable least-squared-based optimization.

Figure 10a represents the two families of $I_C-V_{BE}$ characteristics simulated with PSPICE by varying the temperature $T_B$ in the range 300 to 400 K with a 10 K step (the same step adopted in [29]) for $V_{CE}=1.5\hspace{0.33em}\mathrm{V}$ and $V_{CE}=2.0\hspace{0.33em}\mathrm{V}$. The base-emitter voltage $V_{BE}$ was increased with a very fine step to facilitate the detection of the intersection points. Three $I_C$ levels were selected, namely, $I_C=0.04,\hspace{0.33em}0.07,\hspace{0.33em}0.12\hspace{0.33em}\mathrm{A}$. Twelve intersection points were detected, i.e., four for each $I_C$ value. However, it should be observed that only one point (out of four) in each row corresponds to a true intersection with a reasonable approximation, which is clearly a limit of the original approach considering assigned $I_C$ levels. Figure 11 shows the error resulting from the single-variable optimization, namely, the sum of the squared differences between the LHS and RHS of the 12-equation system for each input value of parameter $\alpha$. It was found that the minimum error is achieved with $\alpha =0.2$ and $R_{TH00}=495.51\hspace{0.33em}\mathrm{K}/\mathrm{W}$. Such values were then used as guess solutions for a two-variable optimization procedure of the 12-equation system, which provided $R_{TH00}=494.69\hspace{0.17em}\mathrm{K}/\mathrm{W}$, $\alpha =0.215$. Unfortunately, such values, once used in (7), lead to an $R_{TH}\left(T_B,P_D\right)$ behavior considerably inaccurate with respect to the reference one, as illustrated in Figure 12. This means that it is highly recommended not to proceed with the original $I_C$-constant approach.

Here we analyze an improved variant of the technique involving the detection of intersection points at various $I_C$ values (i.e., without assigning specific $I_C$ levels). Following this strategy, 27 intersection points were identified from the simulated data without resorting to data interpolation, as shown in Figure 10b. In this case, the single-variable optimization leads to the guess values $\alpha =0.98$ and $R_{TH00}=458.81\hspace{0.33em}\mathrm{K}/\mathrm{W}$ (Figure 11), while the subsequent two-variable optimization yields $R_{TH00}=458.77\hspace{0.17em}\mathrm{K}/\mathrm{W}$, $\alpha =0.98$. As can be inferred from Figure 12, using such values in (7) results in a perceptible, yet tolerable, overestimation of $R_{TH}\left(T_B,P_D\right)$ especially at high $T_B$ and $P_D$ values.

Further accuracy can be gained by determining the intersection points through a careful data interpolation (Figure 10c). In this case, the single-variable optimization gives rise to the guess values $\alpha =0.95$ and $R_{TH00}=460.51\hspace{0.33em}\mathrm{K}/\mathrm{W}$ (Figure 11), while the following two-variable optimization leads to $R_{TH00}=460.33\hspace{0.17em}\mathrm{K}/\mathrm{W}$, $\alpha =0.952$, which are very close to the target values embedded in the transistor model. As can be observed in Figure 12, putting these values in (7) allows obtaining an excellent agreement with the reference $R_{TH}\left(T_B,P_D\right)$ data.

Owing to the above considerations, the technique from Huszka et al. was applied to the Si/SiGe HBT by identifying 27 intersection points through a data interpolation process, as shown in Figure 13. As mentioned earlier, for this device, the target $R_{TH00}$ and $\alpha$ values in the transistor model are equal to 6855.8 K/W and 1.333, respectively. The optimization procedure led to $R_{TH00}=6939.66\hspace{0.33em}\mathrm{K}/\mathrm{W}$ and $\alpha =1.3487$. Unfortunately, in this case the extracted $R_{TH}$ data perceptibly overestimate the reference counterparts, as can be inferred from Figure 14. A careful analysis allowed demonstrating that this inaccuracy is due to the marginal, yet non-negligible, Early effect playing a role in this technology (the forward Early voltage being equal to 110 V) and slightly affecting the equality (29). This was proven by intentionally removing the Early effect from the PSPICE transistor model and repeating the application of the improved variant of the technique; in this case, it was found that $R_{TH00}=6866.53\hspace{0.33em}\mathrm{K}/\mathrm{W}$ and $\alpha =1.338$, which results in very good alignment between extracted and target $R_{TH}$ data. Given this consideration, this technique is expected to provide a relatively high $R_{TH}$ overestimation when applied to Si BJTs, which are more impacted by the Early effect than HBTs [38].

4.5. Summary of the Main Findings

The $R_{TH}$ extraction techniques based on the identification of intersection points were conceived with the aim of getting rid of errors related to the thermometer evaluation.

The technique developed by Liu and Yuksel [39] is fairly intricate, it neglects the nonlinear thermal effect due to the backside temperature $T_B$, and it is based on the identification of intersection points at a given collector current, with all but one being approximate since the characteristics do not truly intersect at those points. The $R_{TH}$ vs. $P_D$ results are inaccurate and noisy. We believe that such problems can be further exacerbated by using actual experimental data due to the unavoidable overlapping noise.

The technique presented by Marsh [40] seems simpler to execute, but in practice the choice of the biasing conditions for safe application is critically limited for the Si/SiGe HBT technology, where the avalanche effect may play a role at relatively low collector-emitter voltages. The presence of an even weak Early effect can adversely impact the accuracy of the results. In addition, the $R_{TH}$ dependence on $P_D$ is not accounted for. Due to the above reasons, the extracted $R_{TH}-T_B$ behavior, besides being somehow inaccurate, is challenging to interpret and difficult to exploit for the development of self-heating models, as the $R_{TH}$ values along the $R_{TH}-T_B$ curve correspond to different $P_D$ values.

The Berkner’s approach [41], although straightforward to apply, suffers from a theoretical flaw, as it assumes that $R_{TH}$ is uniquely determined by the junction temperature $T_j$, which is not true: $R_{TH}$ separately depends on the backside temperature $T_B$ and the dissipated power $P_D$.

The technique proposed by Huszka et al. [29] can be reviewed as a corrected and improved version of the Berkner’s approach, and deserves a separate discussion since it is the only one that accounts for the aforementioned $R_{TH}$ dependence on $T_B$ and $P_D$, which is modeled in an adequate way. However, also this technique suffers from some shortcomings. First, it is quite complicated to apply, as it is based on the measurement of many $I_C-V_{BE}$ characteristics by varying $T_B$ and $V_{CE}$, the identification of a high number of intersection points, and the development of a code for single- and two-variable optimizations. Second, through careful analysis, we have found that the original approach, which is based on detecting intersection points at assigned collector current levels, leads to an intolerable extraction inaccuracy, since at each collector current all points except one are approximate, that is, they do not correspond to true intersections of the characteristics. Hence, we have proposed an improved version relying on the identification of true intersection points at various collector currents. However, although with this approach the extraction accuracy improves significantly, we demonstrated that there is still a perceptible sensitivity to the precision with which the intersection points are taken, and thus a careful data interpolation to identify such points is necessary. On the other hand, this makes the technique even more intricate to apply. The improved and refined approach allowed achieving good agreement between the extracted and target $R_{TH}$ data for the InGaP/GaAs HBT, but provided a slight $R_{TH}$ overestimation for the Si/SiGe HBT due to its weak, yet non-negligible, Early effect. We tend to believe that the price to pay when elaborating real (noisy) measured data (instead of synthetic data) will be high in terms of extraction accuracy due to the high sensitivity to the identification of intersection points.

5. Conclusions

This paper represents Part II of a comprehensive three-part work dedicated to the critical review of techniques for the indirect extraction of the thermal resistance in bipolar transistors from simple DC current/voltage measurements. In Part I [30], the analysis focused on techniques based on the determination of a thermometer. Conversely, Part II has been dedicated to methods that exploit the detection of intersection points between characteristics. The accuracy assessment has been performed by (i) emulating the measurements with PSPICE simulations of a transistor model embedding a thermal resistance formulation that includes nonlinear thermal effects, (ii) applying the extraction techniques to the simulated current/voltage data, and (iii) comparing the extracted thermal resistance data to those obtained from the embedded formulation, taken as a reference. An InGaP/GaAs HBT and a Si/SiGe HBT for high-frequency applications have been considered as case-studies. It has been demonstrated that (i) regardless of the method, the extraction accuracy is highly sensitive to the precision with which the intersection points are detected; (ii) some methods exhibit limitations due to approximations in handling nonlinear thermal effects or even theoretical inconsistencies. Only the technique conceived by Huszka and his coworkers [29] can be considered worthy of attention, as it reasonably describes nonlinear thermal effects; however, it cannot be applied in its original form that implies the selection of approximate intersection points, leading to noticeably inaccurate results. To address this issue, we have proposed an improved and refined version that enhances accuracy but also increases the complexity of the method, making it more intricate and challenging to apply. Part III of this work will focus on techniques that rely on the measurement of base current [42,43,44,45,46], as well as on the approach developed by Menozzi et al. [47], which does not fit into any of the proposed categories.