A ZVS Bidirectional Inverting Buck-Boost Converter Using Coupled Inductors

Abstract

The bidirectional inverting buck-boost converter (BIBBC) has a simple structure and a wide voltage ratio. It can be used in the battery supercapacitor hybrid energy storage system (BSHESS) and the motor drive system. However, the traditional continuous conduction mode (CCM) BIBBC will have severe switching loss. The triangular current mode (TCM) BIBBC can reduce the switching loss, but it will increase core loss and filter capacitance. To solve these problems, this paper proposes a new zero voltage switching (ZVS) BIBBC using a coupled inductor. This ZVS BIBBC will provide ZVS conditions for both transistors whether in positive operation or negative operation. Meanwhile, this ZVS BIBBC has small core losses and filter capacitance, and can be used simply. Finally, experimental results obtained from these BIBBC experimental prototypes are presented to validate the soft-switching achieving and the efficiency improvement performance. Experimental results show that both transistors of the ZVS BIBBC achieve ZVS turn-on conditions. The efficiency of the ZVS BIBBC increased by up to 10 percent compared to the traditional CCM BIBBC at heave load, and by up to 1.5 percent compared to the TCM BIBBC at a light load.

1. Introduction

The nonisolated bidirectional DC/DC converter (NIBDC) can be used in the motor drive system and the battery supercapacitor hybrid energy storage system (BSHESS) [1,2,3,4,5]. In the BSHESS, the NIBDC is used to control the power flow between the supercapacitor and the battery. The energy management system of the BSHESS uses the NIBDC to manage and distribute the energy of the BIHESS to obtain two goals: improve battery life and increase vehicle efficiency [6,7,8]. Commonly-used NIBDCs have two types: The buck/boost converter and the buck-boost converter [9]. These NIBDCs have two operation directions: The positive operation and the negative operation. The buck/boost converter only has the voltage step-down function in positive operation, and only has the voltage step-up function in negative operation. In contrast with the bidirectional buck/boost converter, the bidirectional inverting buck-boost converter (BIBBC) has both voltage step-down and step-up functions whether in positive or negative operation. This means that the BIBBC will improve the performance of the motor drive system and the BSHESS. However, the BIBBC has higher voltage and current stress than the buck/boost converter under the same output voltage and current. Meanwhile the traditional continuous conduction mode (CCM) BIBBC works under hard-switching conditions. These factors introduce serious conducting and switching losses. To improve the efficiency of the BIBBC, the soft-switching technique is required.

For the BIBBC, one of switches can always obtain the soft-switching condition. Therefore the key is the soft-switching condition for another switch. The simplest soft-switching technology for the BIBBC is the triangular current mode (TCM) method [10], which provides soft-switching conditions for both switches by adjusting the value of the main inductor L. This technology does not use any auxiliary circuitry. However with this technology, the inductor current i_L has large current ripples, which will introduce large current stresses, large core losses, and a large filter capacitance. In order to overcome these shortcomings, many new soft-switching technologies are proposed.

The zero voltage transition (ZVT) technology is a commonly used method for the BIBBC [11,12,13,14,15,16]. By adding auxiliary switches, the ZVT technology gives zero voltage switching (ZVS) conditions for the main switches and zero current switching (ZCS) conditions for the auxiliary switches. Some improved ZVT methods use a coupled inductor to reduce core numbers and improve soft-switching performance [11,13,15]. ZVT-based topologies have high efficiency. The main shortcoming is the cost of auxiliary switches and the complex control timing, because the soft-switching condition is dependent on the control timing. The active clamped soft-switching technology was proposed in multiple previous papers [17,18] for the buck/boost converter, and this technology can also be used in the bidirectional buck-boost converter. In this method only one auxiliary switch is used to obtain soft-switching conditions for two main switches. The coupled inductor can also be used in this topology to improve performance [18]. The shortcoming of these active clamped topologies is the cost of auxiliary switches and the complex control timing. In order to reduce the control complexity of soft-switching topologies, some soft-switching technologies without auxiliary switches were proposed previously [19,20]. In these topologies, the auxiliary circuit, composed of inductors and capacitors, is introduced to the BIBBC to obtain soft-switching conditions. These topologies have a simple structure and have no auxiliary switches. However a previously proposed method is based on the special application (battery equalization applications) [19], and another previously proposed method also faces the problem of large current stresses and core losses [20].

For the existing soft-switching BIBBCs, TCM BIBBCs introduces large current stresses, large core losses, and large filter capacitance; ZVT BIBBCs need auxiliary switches and complex control timing. To overcome these shortcomings, this paper proposes a new ZVS BIBBC using a coupled inductor based on the buck-boost converter in literature [21,22], in which the converter can only obtain soft-switching conditions in positive operation. The structural difference between the proposed ZVS BIBBC and the original converter is the introduced diode. With this diode the ZVS BIBBC has a different operation principle to the original converter, and can provide soft-switching conditions for both transistors whether in positive operation or negative operation. The proposed ZVS BIBBC has comprehensive advantages over similar existing converters:

• Higher efficiency than the CCM BIBBC in most power ranges and higher efficiency than the TCM BIBBC in the medium and low power range;
• A simpler control method and lower cost than ZVT converters;
• Lower core losses and filter capacitance than the TCM BIBBC.
• In short, this paper provides the following contributions:
• Proposal of a new ZVS BIBBC using a coupled inductor with abovementioned advantages;
• Detailed theoretical analysis and design guidelines of the new ZVS BIBBC;
• Experimental analysis and comparison between the proposed ZVS BIBBC and two other BIBBCs.

This paper is organized as follows. Section 2 presents the topology description and operating principle; the soft-switching achieving condition, stress and loss analysis, and design guidelines are given in Section 3. Experimental results and the related analysis are presented in Section 4. Section 5 summarizes the content and contributions of the full paper.

2. Topology and Its Principle

2.1. Proposed Converter

The proposed new ZVS BIBBC, which has bidirectional soft-switching capability, is shown in Figure 1. This converter does not use an auxiliary switch and, therefore, the control complexity of the new ZVS BIBBC is the same as a traditional CCM BIBBC. This converter is suitable for nonisolated bidirectional DC/DC applications requiring wide voltage ratios. The drawback of the proposed new ZVS BIBBC is the additional loss caused by auxiliary diodes. Nonetheless, the achieving of soft-switching conditions will improve the efficiency comparing to the hard-switching BIBBC. The proposed ZVS BIBBC also has two operation directions: The positive operation and the negative operation. In positive operation, the power flow is transferred from v_a to v_b. In negative operation, the power flow is transferred from v_b to v_a. As shown in Figure 1, the soft-switching auxiliary circuit of the proposed BIBBC includes two power diodes, D₁ and D₂, a coupled inductor L_c, and a resonance inductor L_r. The main circuit of the new ZVS BIBBC includes two transistors S₁ and S₂, a main inductor L, two snubber capacitors C_r1 and C_r2, and two filter capacitors C_a and C_b. C_r1 and C_r2 are connected to transistors S₁ and S₂ in parallel, respectively. L_r is used to compensate negative effects of C_r1 and C_r2 on ZVS-on conditions. The coupled inductor L_c, and auxiliary diodes D₁ and D₂ will provide ZVS-on conditions for S₁ (the positive operation) and S₂ (the negative operation). Other symbols are defined as follows. v_a and v_b are the DC voltage values, i_c is the current across L_c, i_L is the current across L, and i_r is the current across L.

In the following sections, the mathematical model of the new ZVS BIBBC will be presented. All variables are International System of Units. Based on the circuit conduction state of the ZVS BIBBC, the proposed ZVS BIBBC will have four operation intervals by ignoring the charging and discharging process of snubber capacitors. Equivalent circuits of these intervals are shown in Figure 2. These equivalent circuits can be used to build the mathematical model of the new ZVS BIBBC. For Interval I, the differential equations of currents (i_c, i_L, and i_r) are

$$\{\begin{array}{l}{k}_{L1}=\frac{d{i}_L}{dt}=\frac{-v_a(M-L_r)-v_b(L_c+M)}{(L+M)(L_r-M)+(L_c+M)(L+L_r)}\\ k_{c1}=\frac{d{i}_c}{dt}=\frac{v_a(L+L_r)+v_b(L+M)}{(L+M)(L_r-M)+(L_c+M)(L+L_r)}\\ k_{r1}=\frac{d{i}_r}{dt}=\frac{-v_a(L+M)-v_b(L+L_c+2M)}{(L+M)(L_r-M)+(L_c+M)(L+L_r)}\end{array}$$

(1)

where M is the mutual inductance between L and L_c. If k is the coupling coefficient, then M² = k²LL_c.

For Interval II, they are

$$\{\begin{array}{l}{k}_{L2}=\frac{d{i}_L}{dt}=\frac{-v_b(L_c+L_r)}{(L+M)(L_r-M)+(L_c+M)(L+L_r)}\\ k_{c2}=\frac{d{i}_c}{dt}=\frac{v_b(M-L_r)}{(L+M)(L_r-M)+(L_c+M)(L+L_r)}\\ k_{r2}=\frac{d{i}_r}{dt}=\frac{-v_b(L_c+M)}{(L+M)(L_r-M)+(L_c+M)(L+L_r)}\end{array}$$

(2)

For Interval III, they are

$$\{\begin{array}{l}{k}_{L3}=\frac{d{i}_L}{dt}=\frac{v_a(L_c+M)+v_b(M-L_r)}{(L+M)(L_r-M)+(L_c+M)(L+L_r)}\\ k_{c3}=\frac{d{i}_c}{dt}=\frac{-v_a(L+M)-v_b(L+L_r)}{(L+M)(L_r-M)+(L_c+M)(L+L_r)}\\ k_{r3}=\frac{d{i}_r}{dt}=\frac{v_a(L+L_c+2M)+v_b(L+M)}{(L+M)(L_r-M)+(L_c+M)(L+L_r)}\end{array}$$

(3)

For Interval IV, they are

$$\{\begin{array}{l}{k}_{L4}=\frac{d{i}_L}{dt}=\frac{v_a(L_c+L_r)}{(L+M)(L_r-M)+(L_c+M)(L+L_r)}\\ k_{c4}=\frac{d{i}_c}{dt}=\frac{-v_a(M-L_r)}{(L+M)(L_r-M)+(L_c+M)(L+L_r)}\\ k_{r4}=\frac{d{i}_r}{dt}=\frac{v_a(L_c+M)}{(L+M)(L_r-M)+(L_c+M)(L+L_r)}\end{array}$$

(4)

2.2. Positive Operation

To describe the operation principle clearly, this section gives the analysis of voltage and current waveforms in one switching period (T) of the positive operation. As shown in Figure 3 and Figure 4, the voltage and current waveforms of the proposed ZVS BIBBC can be divided into eight modes based on the circuit conduction state. Figure 3 gives gate signal waveforms (V_GS1 and V_GS2) and drain-source voltage waveforms (V_S1 and V_S2) respectively for S₁ and S₂, and also gives main current waveforms (i_L, i_r, and i_c). In Figure 3, D is the duty cycle of the gate signal (V_GS1) of S₁. Figure 4 gives circuit conduction states of these modes. In positive operation, the mean value of i_L will be positive, and the energy is transferred from v_a to v_b. If the load current is large enough (all waveforms of i_L are above the time-axis), i_L will be continuous. D₁ and D₂ will not conduct at the same time. i_r will be bidirectional in DT and (1 − D)T will provide soft-switching conditions for S₁ and S₂. The detailed analysis of each mode is presented as follows.

Mode 1 (t₀–t₁, Figure 4a): At the beginning of this mode (t₀), S₁ is turned off by the low-level of V_GS1. After t₀ the changing of V_S1 and V_S2 is slow due to the existence of C_r1 and C_r2. The ZVS-off condition of S₁ is obtained. i_L and i_r are positive and start to decrease. i_c is negative and starts to increase.

Mode 2 (t₁–t₂, Figure 4b): In this mode V_S2 decreases to 0 at t₁, and then is kept to 0 due to the conduction of the body diode of S₂.

Mode 3 (t₂–t₃, Figure 4c): Because V_S2 is 0 at t₂, S₂ conducts at ZVS-on condition. In this mode the changing trend of waveforms of i_L, i_r, and i_c is same to Mode 1 and Mode 2.

Mode 4 (t₃–t₄, Figure 4d): At t₃, the current across D₁ decreases to 0, and then D₁ turns off. The current across D₂ starts to increase from 0, therefore, D₂ turns on. i_c is crossing the time-axis and become positive. The increasing rate of i_c slows. The decreasing rate of i_L and i_r also decrease. When i_c is equal to i_L, i_r starts to be negative.

Mode 5 (t₄–t₅, Figure 4e): S₂ is turned off at the beginning of this mode (t₄). Similar to mode 1, the changing of V_S1 and V_S2 is also slow. The ZVS-off condition for S₂ is achieved. After t₄, i_L and i_r start to increase. i_c starts to decrease.

Mode 6 (t₅–t₆, Figure 4f): V_S1 decreases to 0 at t₅, and is clamped to 0 due to the conduction of the body diode of S₁. i_L, i_c, and i_r have the same state as Mode 5.

Mode 7 (t₆–t₇, Figure 4g): Because V_S1 is kept at 0, S₁ starts to conduct at the ZVS-on condition at t₆. When i_c is equal to i_L, i_r starts to become positive. The conducting state in this mode is the same as Mode 6.

Mode 8 (t₇–t₈, Figure 4h): At t₇, the current across D₂ decreases to 0, and then D₂ turns off. And the current across D₁ starts to increase from 0, therefore, D₁ turns on. i_c is crossing the time-axis and becomes negative. The decreasing rate of i_c reduces. The rising rate of i_L and i_r also reduce.

2.3. Negative Operation

Similar to the positive operation, the negative operation also has eight modes. Figure 5 presents the key voltages and current waveforms, and Figure 6 presents the circuit conductive states of the negative operation. Comparing the negative operation to the positive operation, the mean value of i_L is negative, and the energy will be transferred to v_a. i_c of the negative operation has the same state as the positive operation. i_r moves to the negative direction compared to the positive operation. Therefore, the zero crossing position of i_r (mode 3 and mode 8) is different from the positive operation (mode 4 and mode 7). A detailed mode analysis of the negative operation can refer the mode analysis of the positive operation in Section 2.2.

3. Converter Analysis and Design

3.1. Soft-Switching Conditions

The introduction of C_r1 and C_r2 can reduce the rising rate of V_S1 and V_S2 to provide passive ZVS-off conditions for S₁ and S₂. But the existence of C_r1 and C_r2 has an adverse effect on achieving ZVS-on conditions. Therefore, the resonant inductor L_r is used to compensate the capacitive feature of switches (S₁ and S₂) introduced by C_r1 and C_r2. Based on the capacitor and inductor energy storage formula [23], the compensation energy formula is

$$\frac{(C_{r1}+C_{r2}){(v_a+v_b)}^2}{2}=\frac{L_r{i}_r^2}{2}$$

(5)

Based on the above operation mode analyses, soft-switching conditions of the proposed ZVS BIBBC are shown in Figure 7. Figure 7a is the ZVS-on condition for the positive operation. In positive operation, S₂ will always obtain the ZVS-on condition. The ZVS-on condition of S₁ is that i_r must be negative at t₆. Figure 7b is the ZVS-on condition for the negative operation. In negative operation, S₁ will always obtain the ZVS-on condition. The ZVS-on condition of S₂ is that i_r must be positive at t₂. Then the soft-switching conditions of the proposed BIBBC are that i_r must be negative at t₆ and be positive at t₂.

Then soft-switching achieving equations are

$$\begin{array}{l}\mathrm{at}{t}_6:i_r=i_L-i_c<0\\ \mathrm{at}{t}_2:i_r=i_L-i_c>0\end{array}$$

(6)

i_ave is set as the average value of i_L, i_L is marked as i_L6 at t₆, and i_L is marked as i_L2 at t₂. i_ave can be used to represent the load level of the new ZVS BIBBC. Because i_ave will be roughly equal to the median value of i_L, i_L can be estimated by

$$\{\begin{array}{l}{i}_{L6}=i_{ave}+\frac{k_{L1}(t_3-t_0)+k_{L2}(t_4-t_3)}{2}+k_{L3}(t_6-t_4)\\ i_{L2}=i_{ave}+\frac{k_{L3}(t_7-t_4)+k_{L4}(t_8-t_7)}{2}+k_{L1}(t_2-t_0)\end{array}$$

(7)

At t₆, i_c is marked as i_c6, and at t₂, i_c is marked as i_c2, then i_c will be

$$\{\begin{array}{l}{i}_{c6}=k_{c2}(t_4-t_3)+k_{c3}(t_6-t_4)\\ i_{c2}=k_{c4}(t_8-t_7)+k_{c1}(t_2-t_0)\end{array}$$

(8)

Substituting (7) and (8) into (6),the soft-switching achieving equations can be rewritten as

$$\begin{array}{l}\mathrm{at}{t}_6:i_{ave}+\frac{k_{L1}(t_3-t_0)+(k_{L2}-2k_{c2})(t_4-t_3)}{2}+(k_{L3}-k_{c3})(t_6-t_4)<0\\ \mathrm{at}{t}_2:i_{ave}+\frac{k_{L3}(t_7-t_4)+(k_{L4}-2k_{c4})(t_8-t_7)}{2}+(k_{L1}-k_{c1})(t_2-t_0)>0\end{array}$$

(9)

To guarantee the achieving of ZVS-on conditions, the first equation of (9) limits the maximum value of the positive load (the maximum value of i_ave is positive), and the second equation of (9) limits the maximum value of the negative load (the minimum value of i_ave is negative). Equation (9) is the initial soft-switching achieving condition of the proposed converter. Because values of the time in (9) are unknown, Equation (9) cannot be used in the actual design. To further simplify (9), setting d₁ = t₃ − t₀, d₂ = t₄ − t₃, d₃ = t₇ − t₄, d₄ = t₈ − t₇, x₁= d₁/(d₁ + d₂), x₂= d₃/(d₃ + d₄). Then

$$\{\begin{array}{l}{d}_1+d_2=(1-D)T\\ d_3+d_4=DT\end{array}$$

(10)

In one period, the changing of i_r and i_c is zero. Then

$$\{\begin{array}{l}{k}_{r1}{d}_1+k_{r2}{d}_2+k_{r3}{d}_3+k_{r4}{d}_4=0\\ k_{c2}{d}_3+k_{c3}{d}_3=0\\ k_{c1}{d}_1+k_{c4}{d}_4=0\end{array}$$

(11)

Based on (10) and (11), x₁ and x₂ are

$$\{\begin{array}{l}{x}_1=\frac{D(M-L_r)}{L+M}\\ x_2=\frac{(1-D)(M-L_r)}{L+M}\end{array}$$

(12)

Based on (9) and (10), the soft-switching achieving equation can be rewritten as

$$\begin{array}{l}{i}_{ave}+\frac{T(1-D)\left[k_{L1}{x}_1+(k_{L2}-2k_{c2})(1-x_1)\right]}{2}+(k_{L3}-k_{c3})t_{de}<0\\ i_{ave}+\frac{DT\left[k_{L3}{x}_2+(k_{L4}-2k_{c4})(1-x_2)\right]}{2}+(k_{L1}-k_{c1})t_{de}>0\end{array}$$

(13)

t_de is the dead time, t_de = t₆ − t₄ = t₂ − t₀. Then substituting (1)–(4), and (12) into (13), the soft-switching achieving condition is

$$\begin{array}{l}\frac{2(i_{ave}+k_{r3}{t}_{de})}{T{v}_b(1-D)}<\frac{(1-2D){(M-L_r)}^2+(L+M)(L_c+2M-L_r)}{(L+M)\left[(L+M)(L_r-M)+(L_c+M)(L+L_r)\right]}\\ \frac{2(i_{ave}+k_{r1}{t}_{de})}{DT{v}_a}>\frac{(1-2D){(M-L_r)}^2-(L+M)(L_c+2M-L_r)}{(L+M)\left[(L+M)(L_r-M)+(L_c+M)(L+L_r)\right]}\end{array}$$

(14)

Equation (14) is the soft-switching limited condition. From (14), we can determine that this equation limits the range of i_ave from the negative value to the positive value. The negative value of i_ave represents the negative power flow, and the positive value of i_ave represents the positive power flow. This soft-switching limited condition gives a load limiting soft-switching condition. For a designed converter, if the absolute value of i_ave is smaller than the designed i_ave, the soft-switching conditions will always be obtained. We can also know that a large L_c and small L is beneficial to achieving ZVS-on. However a small L will lead to large current ripples of i_L. Therefore, L_c is the best parameter to adjust the soft-switching range.

3.2. Stress and Losses Analysis

In the proposed ZVS BIBBC, no extra voltage stress is introduced by auxiliary circuits. However the BIBBC has higher voltage stress than the buck/boost converter. The maximum voltage of main semiconductor devices (S₁, S₂, D₁, and D₂) is v_a + v_b in both the traditional buck-boost converter and the proposed converter. Figure 8 shows the current stress analysis for S₁, S₂, D₁, and D₂. Due to the soft-switching requirement, i_r crosses the 0-axis two times in one period, and has large ripples. These large ripples give the S₁ and S₂ of the proposed BIBBC larger current stress than the traditional CCM BIBBC. In zero-power condition, S₁ and S₂ have minimum current stress, and the current stress increases with increasing output power (whether positive power or negative power). In the maximum transmission power, S₁ and S₂ have maximum current stress. In this condition, the maximum absolute value of i_r is

$$i_{rpp}=\frac{DT{v}_a(2M+L_c-L_r)}{(L+M)(L_r-M)+(L_c+M)(L+L_r)}$$

(15)

i_c determines the current stress of D₁ and D₂. The maximum current values for D₁ and D₂ are

$$\begin{array}{l}{i}_{cp1}=\frac{v_{b}T(1-D)(M-L_r)\left[L+L_r+DM-D{L}_r\right]}{(L+M)\left[(L+M)(L_r-M)+(L_c+M)(L+L_r)\right]}\\ i_{cp2}=\frac{v_{b}T(1-D)(M-L_r)(L+M+D{L}_r-DM)}{(L+M)\left[(L+M)(L_r-M)+(L_c+M)(L+L_r)\right]}\end{array}$$

(16)

The loss of the proposed converter includes three parts: the on-loss and switching loss for S₁ and S₂, the auxiliary circuit loss, and the core loss. Thanks to the achieving of ZVS-on and ZVS-off conditions for S₁ and S₂, the turn-on loss is eliminated and the turn-off loss is reduced. The on-loss is larger than the traditional CCM BIBBC due to the existence of large ripples of i_r. The auxiliary circuit loss is caused by diodes D₁ and D₂, and can be reduced using low forward voltage diodes. The core loss is related to the current ripple and the core material. In the proposed converter, i_c and i_r both have large ripples. So to reduce core losses, low-loss cores should be used. By rational design, the switching loss and the core loss will be reduced by the soft-switching achieving and the use of low loss cores. So for the proposed BIBBC, the conduction loss (the on-loss of S₁ and S₂, the on-loss of D₁ and D₂) is dominant.

3.3. Design Guidelines

Equation (14) can be used in the actual soft-switching design of the proposed BIBBC. i_ave can represent the load level of the BIBBC. It is known from (14) that the maximum absolute value of i_ave can be used to design the soft-switching converter. Thus soft-switching conditions can be guaranteed when the absolute value of i_ave is smaller than the design value. According to the above soft-switching condition analysis, the design steps are presented:

Step 1: Determine the voltage level (v_a, v_b) and the load level (maximum absolute value of i_ave) according to the application environment and the stress analysis in Section 3.2. Then

$$D=\frac{\left|v_b\right|}{\left|v_a\right|+\left|v_b\right|}$$

(17)

Step 2: Snubber capacitors (C_r1, C_r2) are used to reduce the increasing rate of drain-source voltages (V_S1, V_S2) to obtain ZVS-off conditions. Based on the increasing time and the voltage level, C_r1 and C_r2 can be selected. L_r is the resonant inductor, which is used to compensate the snubber capacitors (C_r1, C_r2). L_r can be designed based on (5).

Step 3: Current ripples of i_L can be calculated based on

$$i_{Lpp}=\frac{v_{a}DT}{L+M}\frac{{(M-L_r)}^2+(L_c+L_r)(L+M)}{(L+M)(L_r-M)+(L_c+M)(L+L_r)}$$

(18)

If ignoring the magnetic coupling effect, the current ripple equation will be

$$i_{Lpp}=\frac{v_{a}DT}{L+L_r}$$

(19)

Then, based on the ripple requirement of i_L, the initial value of L can be calculated by (19).

Step 4: Equation (14) is the soft-switching achieving condition. Based on the above calculation, all parameters except L_c and M are known. Considering k = 0.7, substituting the positive maximum value of i_ave in the first equation of (14), and substituting the negative minimum value of i_ave in the second equation of (14), L_c and M can be calculated.

Step 5: Based on (18), the final value of L can be calculated.

4. Experimental Results

4.1. Experimental Setup

In this section, a 200 W experimental prototype was built to illustrate the features and benefits of the proposed BIBBC. The experimental platform is composed of the experimental prototype, the control signal generator (a XC2267M board, Qianqin Technology, Beijing, China), the DC voltage source, the resistive load, and measuring tools, as shown in Figure 9. The main experimental parameters of the components of the experimental prototype are presented in

Table 1. Proposed converter parameters.

Parameter	Value	Parameter	Value
va	DC 70 V	Cr1, Cr2	2.2 nF
vb	DC 70 V	Ca, Cb	1000 μF
D	0.5	M	18.9 μH
f	100 kHz	Lc	4.1 μH
L	159.2 μH	S1, S2	IRFP4668
Lr	2.4 μH	L, Lc core	Kool mu
D1, D2	DSSK60-02A	Lr core	Kool mu

. This experimental platform uses the open-loop method to test the experimental prototype in the voltage level of 70 V to 70 V. Switching waveforms of main voltages and currents are measured by voltage probes, current probes (CP8150A and CP9012S by CYBERTEK, ShenZhen ZhiYong Electronics Co., Ltd., Shenzhen, Guangdong, China), and by oscilloscope (TDS 2024C by Tektronix, Tektronix, Inc., Beaverton, OR, USA). The efficiency is measured by the power analyzer Yokogawa WT1800 (Yokogawa Test & Measurement, Musashino-shi, Tokyo, Japan). These measuring tools have appropriate precisions to reduce the effect of measurement errors on the experimental results. To prove the superiority of the proposed converter, efficiency measurement results are compared to a traditional BIBBC respectively with CCM and TCM.

4.2. Results Analysis

Soft-switching achieving: Switching waveforms of the main switches (S₁ and S₂) are presented in Figure 10 and Figure 11. Figure 10 shows the switching waveforms of V_GS1, V_GS2, V_S1, V_S2, i_S1, and i_S2 in positive operation. From these waveforms, it can be seen that the PWM gate signal V_GS1 rises to a high level after V_S1 decreases to 0. The ZVS turn-on condition of S₁ is obtained. Similar to the switching waveforms of S₁, V_GS2 also rises to a high level after V_S2 decreases to 0. The ZVS condition of S₂ is also obtained. Figure 11 shows the switching waveforms for S₁ and S₂ in negative operation. ZVS conditions for S₁ and S₂ were also obtained based on the same analysis method. Based on these experimental waveforms, the proposed converter provides ZVS turn-on conditions for both S₁ and S₂, whether in positive operation or negative operation. These waveforms are measured at an output power of approximately 115 w.

Current waveforms: To prove the current waveform analysis in Section 2, current waveforms of i_r, i_c, and i_L were measured as shown in Figure 12. We can see that i_L is continuous and has a lower ripple than i_r and i_c. i_c is composed of currents in D₁ and D₂. Because D₁ and D₂ will not conduct at the same time, the current in D₁ and D₂ can be obtained from i_c. i_r has larger ripples, which are used to provide soft-switching conditions. These waveforms are consistent with the analysis shown in Figure 3 and Figure 5.

Efficiency comparison: The measured efficiency of the proposed BIBBC is presented in Figure 13. It is compared with a traditional BIBBC with regard to CCM and TCM. The CCM BIBBC has the same L as the proposed BIBBC, and it works under hard-switching conditions. The value of L in the TCM BIBBC is 18.95 μH, and it works under soft-switching conditions. From these efficiency curves in Figure 13, the proposed BIBBC and the TCM BIBBC have higher efficiency than the CCM BIBBC in most output power range. The proposed BIBBC has a higher efficiency at medium and low output power, but a lower efficiency at heavy output power than the TCM BIBBC. With the increase of the output power, the proportion of auxiliary circuit losses in the whole power reduces, efficiency curves rise rapidly. For the proposed BIBBC, efficiency curves of the positive operation and the negative operation are roughly the same. For the CCM BIBBC, the efficiency is approximately 82% to 83% in both the positive operation and negative operation. Overall, the proposed BIBBC has an efficiency improvement of up to 10 percent greater than the CCM BIBBC at heavy load, and has efficiency improvement of up to 1.5 percent greater than the TCM BIBBC at light load.

4.3. Power Supply and Extended Converter

The power supply used in the experiment is a DC voltage source. Its power characteristics are shown in Figure 14a. It can be seen that the voltage is a constant value (70 V) with small fluctuations when the output power is increasing. Figure 14b shows another new similar ZVS BIBBC by changing the magnetic coupling method of the proposed ZVS BIBBC. This ZVS BIBBC type II has similar characteristics to the proposed ZVS BIBBC. It can be used as an optional topology for practical applications.

5. Conclusions

In order to obtain the bidirectional soft-switching capability and high efficiency for the BIBBC, a new ZVS BIBBC with coupled inductors is proposed by introducing one diode into the existing soft-switching buck-boost converter. The operating principle analysis, soft-switching achieving condition, and stress analysis are presented for the proposed BIBBC. By giving the design guidelines of the new ZVS BIBBC, a 200W experimental prototype was built, and the abovementioned performance analysis verified. From the experimental switching waveforms, both transistors of the ZVS BIBBC achieve ZVS turn-on conditions. From efficiency comparing results, the proposed ZVS BIBBC has higher efficiency than the CCM BIBBC in most output power ranges, and displays an efficiency improvement of up to 10 percent at heavy load. The proposed ZVS BIBBC also has higher efficiency than the TCM BIBBC in the medium and low power range; an efficiency improvement of up to 1.5 percent at light load can be realized.