A Semi-Floating Gate Memory with Tensile Stress for Enhanced Performance
Round 1
Reviewer 1 Report
Although the concept presented in the paper of the semifloating gate memory is not novel and already presented without the strained cap, the authors demonstrated the new concept through TCAD simulations. I'm not completely familiar with modeling of strained layers on the device and how well these models can realistically demonstrate in the simulations, thus I believe the authors should provide some references of this aspect. Another aspect that is ignored by the authors is the implications of CESL on reliability and on process variations. What will the density be of induces defects and how these defects distributed. Such variations might have fatal impact on memory retention in the presence of variations, if it is not possible to simulate such effects we would need some educated guess by the authors.
Author Response
Please see the attached file for the detailed responses.
Author Response File: 
Author Response.pdf
Reviewer 2 Report
In this paper, we propose a semi-floating structure to overcome the retention weakness of 1T-1C DRAM and verify it through simulation results. Tensile stress leads to improved device performance. Although there are limitations in the results of the simulation, verification will be possible through future processes.
Author Response
We are really grateful for your appreciation on our work. Our simulation results have provided a guideline for the industrial manufacture and we are considering the taping out of the U-shaped SFGT with CESL stress engineering.
