HoneyComb ROS: A 6 × 6 Non-Blocking Optical Switch with Optimized Reconfiguration for ONoCs

Abstract

Silicon photonics has become a commonly used paradigm for on-chip interconnects to meet the requirements of higher bandwidth in computationally intensive applications for manycore processors. Design of an optical switch is a vital aspect while constructing an optical NoC topology which influences the performance of network. We present a HoneyComb optimized reconfigurable optical switch (HCROS), a 6 × 6 non-blocking optical switch where optimized reconfiguration of optical links utilizing the states of basic 2 × 2 optical switching elements (OSE) was achieved while keeping the input-output (I/O) interconnection intact. The proposed 6-port HCROS architecture was further optimized to reduce the number of OSEs to minimize overall power consumption. We proposed a generic algorithm to find the optimal switching combination of OSEs for a particular I/O link to minimize the insertion loss and power consumption. In comparison to other non-blocking architectures, a maximum of 66% reduction in OSEs was observed for the optimized HCROS, which consumes only 12 OSEs. Simulations were performed for all 720 I/O links in different configurations to evaluate the power consumption and insertion loss. We observed up to 92% power savings in the case of optimized HCROS as compared to un-optimized HCROS, and a 79% minimization in insertion loss was also reported as a result of optimization.

1. Introduction

With the advent of the manycore era, hundreds to thousands of cores are expected to be fabricated on a single die for various applications, including the internet of things (IoT), machine learning, and high performance computing where higher bandwidth requirements are highly anticipated in the near future [1,2,3]. The network-on-chip (NoC) effectively exploits the parallelism to provide higher bandwidth demands for future manycore processors [4]. However, the future requirements for the above-mentioned applications cannot be fulfilled using conventional on-chip electrical interconnects [5,6]. The International Technology Roadmap for Semiconductors (ITRS) has acknowledged ONoCs as a substitute to overcome the limitations of traditional on-chip interconnects [7]. Silicon photonics can deliver higher on-chip communication bandwidth by exploiting wavelength division multiplexing (WDM) with lower latency and power consumption, and can achieve a bandwidth of terabits per second (Tbps) [8,9,10].

Optical switches/routers are one of the important building blocks of optical NoCs (ONoC). In the past few years a lot of research has been carried out in regard to designing power and loss efficient optical switch/router architectures [11,12,13,14,15,16,17,18]. An optical switch/router can be designed using different switching fabrics, e.g., a micro-ring resonator (MR) [19] or a Mach-Zehnder switch (MZ) [20] as the basic switching element. Designing optical switch architecture with an optimum number of OSE can minimize overall insertion loss and power consumption in the network topology [21]. Numerous methodologies have been proposed to construct optical switch/router topologies with optimal arrangements of OSEs and different methods have been proposed to optimize the number of OSEs to improve overall network performance [22,23,24,25,26]. In this regard, several multi-stage blocking, strictly non-blocking (SNB), and rearrangeable non-blocking (RNB) optical switch architectures have been presented [27,28], e.g., Benes [29], Spanke-Benes [30], cross switch matrix [31] and Path Independent Loss (PILOSS) [32]. Different ONoC topologies, e.g., mesh, torus, clos and fat tree use 4-port or 5-port optical routers with one core attached to each router. A topology that has two cores attached to a single router has been proposed to form a cluster [33,34]. Cluster-based topology saves chip area and requires a 6-port optical router for the additional core connected to the same router. Different 6-port optical switch/router designs have been proposed to fulfill the requirements of cluster Mesh ONoCs [35,36,37].

The design of an optical switch/router with reduced number of OSEs delivers the advantages of low power consumption and minimized area usage [36]. Power consumption and the inherent feature of insertion loss (IL) in ONoCs require special design considerations for switch design. Reduction in the number of OSEs or MRs in the design of the optical switch can decrease overall IL and power consumption of the optical switch topology, which can improve the overall performance of NoC. In order to minimize the number of OSEs, we need to optimize the switch architecture and identify the optimal configuration in which system peak performance of NoC can be realized. This can be achieved through optimized reconfiguration (here reconfiguration is the switching states of OSE, i.e., active or inactive) of OSEs with the least number of OSEs in an active state where the effects of power consumption and IL are minimal. Designing a non-blocking optical switch with a minimal number of OSEs, and identifying the optimal switching configuration in which the optical switch consumes minimal power with optimal IL is a challenging task. Optimized reconfiguration of optimal switching combinations of OSEs in optical switch topology is the main objective of this article.

Keeping in mind the above-mentioned challenges, we propose an optimized 6-port reconfigurable non-blocking optical switch that consumes only 12 OSEs in an optimized structure with minimized IL and power consumption in an optimal arrangement of OSEs. We exploit the optimal switching combinations of OSEs to reconfigure the switching states to achieve improved performance of the optical switch. In order to achieve the optimum condition of OSEs, we propose an algorithm to find the best switching combination for a desired I/O link with minimal OSEs in an active state. Salient features of the proposed work are as follows:

• We propose a 6 × 6 reconfigurable non-blocking optical switch with a reduced number of OSE where routing combinations can be reconfigured using optimized reconfiguration to route any desired I/O link.
• We present a generic algorithm to find the optimal switching combination with the minimal number of OSE in an active, i.e., drop/bar state, which is used to complete the process of optimized reconfiguration to minimize the IL and power consumption. We identify a particular switching combination, where all OSEs are found in an inactive state that leads to minimum power consumption through optimized reconfiguration of the proposed HCROS.
• Further optimization significantly reduces the number of OSEs in comparison to other non-blocking switch architectures, which leads to minimized hardware cost and compact foot print of the HCROS topology while keeping the non-blocking feature intact.
• A comprehensive analysis for power consumption and insertion loss for all N! possible I/O links is also discussed in this article.

This paper is structured as follows: Section 2 provides a brief background about multistage optical switch design and its mathematical modeling. Section 3 presents the 6 × 6 HCROS architecture and routing details in both optimized and un-optimized form. A mathematical proof for the non-blocking property is provided in Section 4. An algorithm to find the optimal switching combination of HCROS is provided in Section 5. Comparisons, simulation results and detailed performance analysis are discussed in Section 6. Finally, Section 7 concludes the article with a discussion of intended future work. We will use the following definitions in this article for the terms optimized, optimal, and optimized reconfiguration.

• Optimized: We use the term “optimized” for the 6-port HCROS optical switch with reduced OSEs as a result of optimization where some OSEs are replaced with waveguide crossings.
• Optimal: We defined the term “optimal” as the configuration for the minimum number of OSEs in a bar/drop state or more specifically, “optimal switching combination”. Since basic 2 × 2 micro-ring (MR)-based OSE consumes more power in a bar/drop state than in a cross/through state, also the insertion loss of 2 × 2 MR-based OSE is higher in a bar/drop state.
• “Optimized reconfiguration” is defined as a process of utilizing optimal switching combination (optimal state) to reconfigure OSEs in HCROS to reduce power consumption and minimize insertion loss while ensuring the input to output interconnections are unaffected.

In addition, we use the following definitions to describe the following terms:

• I/O link: An I/O links is defined as a set of particular “routing combinations” to connect the desired input to output.
• Routing combination: A routing combination consists of six optical paths to connect each input port to every output port for mapping a particular I/O link, hence it is responsible for transmission of data in parallel.
• The switching combination is the state of OSEs for a particular routing combination to map a particular I/O link.

2. Background

In this section, we briefly review the basics of the 2 × 2 optical switching element used in the design of an optical switch/router, the transfer matrix-based mathematical model of 2 × 2 basic OSE, and the non-blocking properties of optical switch/routers. MR is widely used as a basic component in optical interconnects due to its compact size and compatibility with CMOS. The functionality of 2 × 2 MR based OSE is illustrated in Figure 1a,b, where 2 × 2 OSE consists of two crossing waveguides and two MRs [19,38]. When the resonant frequency of MR is not the same as the modulated signal, the optical signal simply passes through the waveguide intersection. However, when the wavelength, i.e., λ_i = λ_r, the optical signal gets coupled into MR and changes its direction to its respective output [39,40] where λ_i is the input wavelength while λ_r is the wavelength of the particular MR, as shown in Figure 1. It consists of two states (1) active state, i.e., drop/bar, and (2) inactive state, i.e., through/cross. In the active state, MRs are in a resonance condition with respective inputs, therefore, input signals I₁ and I₂ get coupled into upper and lower MRs, respectively, and as a result, I₁ and I₂ are propagated to O₁ and O_2, respectively, as shown in Figure 1a. During the inactive state, input signals I₁ and I₂ pass through using the same waveguide and are transmitted to O₂ and O₁ as shown in Figure 1b [19]. Detailed I/O mapping of 2 × 2 OSE is shown in

Table 1. MR based 2 × 2 OSE switching state table.

Input	Output	MR State	Wavelength λi
I1	O1	DB *	λi = λr
I2	O2	DB *	λi = λr
I1	O2	TC *	λi ≠ λr
I2	O1	TC *	λi ≠ λr

* Drop/Bar (D_B) and Through/Cross (T_C) states.

. In this article, we use a MR-based 2 × 2 OSE as the basic design unit for the proposed HCROS architecture and we use the terms drop (D_B) and through (T_C) for the active and inactive states, respectively.

Basic 2 × 2 OSEs can be used to construct non-blocking multi-stage switch topologies. Basic 2 × 2 OSE denoted by E^D_s|T_s can be modeled as transfer matrix using the following Equations (1) and (2) where E^T_s and E^D_s represent OSE in through and drop states, respectively.

$$E^{T_S}=\left[\begin{array}{cc}0& 1\\ 1& 0\end{array}\right]$$

(1)

$$E^{D_S}=\left[\begin{array}{cc}1& 0\\ 0& 1\end{array}\right]$$

(2)

$$E^{D_S|T_S}=E^{D_S}or{E}^{T_S}$$

(3)

E^D_s|T_s is expressed as particular OSE in through (E^T_s) or drop (E^D_s) states and is represented as Equation (3). Multistage architecture with N inputs-outputs is represented in the form of a transfer matrix M with S number of stages, where each stage is represented in the form of a block diagonal matrix Ω. Each stage may consist of a straight waveguide, crossing waveguide, OSE in drop (E^D_s) or through (E^T_s) states [25]. Straight waveguide is represented with the value of ‘1’ in the transfer matrix. I/O mapping is expressed as O = M.I, where I and O are the input and output column vectors of radix N switch. Transfer matrix M is represented as the product of Ω_S matrices, and the proposed HCROS architecture consists of 7 stages where S = (1, 2, … 7) and M is expressed as Equation (4) [25].

$$M={\mathrm{\Omega }}_1{\mathrm{\Omega }}_2\cdots {\mathrm{\Omega }}_{S-1}{\mathrm{\Omega }}_S={\displaystyle \prod _{i=1}^S{\mathrm{\Omega }}_i}$$

(4)

The following set of rules should be followed while designing non-blocking optical switch topology:

• Input signal from any input I_n should be routed to any output port O_n of the radix N optical switch.
• The link between any input I_n and output O_n pair should not block other input-output optical links in particular routing combinations of the radix N optical switch.
• For an N port non-blocking optical switch there exists N! switching states. For example, N = 6, it contains 6! = 720 possible switching states. For any switch to be non-blocking it should have N! routing states that remain intact, otherwise it would become blocking.

3. Switch Architecture

In this section, the proposed HCROS architecture is discussed in detail including the routing table for both the un-optimized and optimized forms.

3.1. Six-Port Non-Blocking Reconfigurable Optical Switch Architecture

Our proposed HCROS design consists of 6 input and 6 output ports with 15 2 × 2 MR based OSEs, i.e., SE₁, SE₂, … SE₁₅ and 6 waveguide crossings as shown in Figure 2. The switch can route 6! = 720 switching states. The proposed switch is divided into 7 stages shown in Figure 2 as Ω₁, Ω₂, Ω₃, Ω₄, Ω₅, Ω₆ and Ω₇ having 2 × 2 OSEs, and 2 stages with waveguide crossings shown as P_I and P_O. P_I and P_O provide the symmetry across both sides of the switch architecture. The architecture presented in Figure 2 looks like a honey comb structure, based on this we named the proposed optical switch, the HoneyComb reconfigurable optical switch (HCROS).

Using the methodology discussed in Section 2, we formulated the stage matrices of HCROS with the help of the expression shown in Equation (5).

$${\mathrm{\Omega }}_S=\left[\begin{array}{ccccc}{E}^{D_S|T_S}& 0& 0& 0& 0\\ 0& E^{D_S|T_S}& 0& 0& 0\\ 0& 0& \ddots & 0& 0\\ 0& 0& 0& E^{D_S|T_S}& 0\\ 0& 0& 0& 0& E^{D_S|T_S}\end{array}\right],\mathrm{W}\mathrm{h}\mathrm{e}\mathrm{r}\mathrm{e}(S=1,2,3,\mathrm{...7})$$

(5)

The complete transfer matrix is written in the form of the following Equation (6)

$$M={\mathrm{\Omega }}_1{\mathrm{\Omega }}_2{\mathrm{\Omega }}_3{P}_I{\mathrm{\Omega }}_4{P}_O{\mathrm{\Omega }}_5{\mathrm{\Omega }}_6{\mathrm{\Omega }}_7$$

(6)

P_I and P_O represent stages without OSEs, these two stages are a combination of straight and crossing waveguides and are represented using Equations (7) and (8), respectively. P_I is a column permutation matrix while P_O is a row permutation matrix.

$$P_I={\left[\begin{array}{cccccc}1& 3& 5& 2& 4& 6\end{array}\right]}^T$$

(7)

$$P_O=\left[\begin{array}{cccccc}1& 3& 5& 2& 4& 6\end{array}\right]$$

(8)

Six I/O ports exploit 15 OSEs that can be reconfigured according to the desired routing combination.

Table 2. Routing combinations for the 6-port optical switch.

I/O Links	Routing Combinations
SC1	I1 → O2; I2 → O3; I3 → O4; I4 → O5; I5 → O6; I6 → O1;
SC2	I1 → O3; I2 → O4; I3 → O5; I4 → O6; I5 → O1; I6 → O2;
SC3	I1 → O4; I2 → O5; I3 → O6; I4 → O1; I5 → O2; I6 → O3;
SC4	I1 → O5; I2 → O6; I3 → O1; I4 → O2; I5 → O3; I6 → O4;
SC5	I1 → O6; I2 → O1; I3 → O2; I4 → O3; I5 → O4; I6 → O5;
SC6	I1 → O1; I2 → O2; I3 → O3; I4 → O4; I5 → O5; I6 → O6;

lists six routing combinations for different I/O links denoted as SC₁, SC₂, … SC₆, where links from SC₁, SC₂, … SC₅ cover N(N-1) links. There are a total 6! = 720 distinct I/O links with different routing combinations for the 6-port optical switch, however, the selected 6 routing combinations cover all 30 optical links that can route every input to each output except loopback. We also included a loopback SC₆ as the 6th I/O link with a certain routing combination, as shown in Table 2. The remaining routing combinations are just different permutations of these 6 routing combinations [36,41]. For N = 6, I/O links can route a total of 30 links from input to output ports. Using these routing combinations, we reconfigured 15 OSEs, i.e., SE₁, SE₂, … SE₁₅ to map different I/O links, as listed in Table 2. However, our analysis is not restricted to only these six I/O links, in addition, we have provided a comprehensive performance analysis for all 720 I/O links in Section 6.

Table 3. Switching combinations of OSEs for a particular I/O link in the 6-port HCROS.

I/O Links	SE1	SE2	SE3	SE4	SE5	SE6	SE7	SE8	SE9	SE10	SE11	SE12	SE13	SE14	SE15
SC1	DB	DB	DB	DB	DB	DB	DB	DB	TC	DB	DB	TC	TC	TC	TC
SC2	DB	DB	DB	DB	DB	DB	DB	TC	TC	TC	TC	TC	TC	DB	DB
SC3	DB	DB	DB	DB	DB	DB	TC	TC	TC	DB	DB	DB	DB	DB	DB
SC4	DB	DB	DB	DB	DB	DB	TC	TC	DB	DB	DB	TC	TC	TC	TC
SC5	DB	DB	DB	DB	DB	DB	TC	DB	DB	TC	TC	TC	TC	DB	DB
SC6	DB	DB	DB	DB	DB	DB	DB	DB	DB	DB	DB	DB	DB	DB	DB

lists the 15 OSEs used for each routing combination to route an input to a particular output and shows the switching state of each OSE, i.e., drop (D_B) or through (T_C). For example, I₁ can complete its route to every output O₁, O₂, … O₆ in 6 I/O links using routing combinations_. Similarly, each input covers a route to every output in the defined 6 I/O links. Note that there are more than one switching combination for each routing combination.

As an example, the switching combination for the SC₆ I/O link is shown in Figure 3, where we can observe that I₁ → O_1, shown in green, uses 5 OSEs to reach output port O₁ and all OSEs remain in a drop state. Similarly, other routing combinations are distinguished in separate colors. For one I/O link there could be several possible paths, however for simplicity we have shown all switches in drop states that route one-to-one I/O mapping. Here, we can see that all routing combinations can route their data packets to their respective destination in parallel. The proposed HCROS is a non-blocking architecture and the optimized HCROS falls in the category of RNB (rearrangeable non-blocking) since all input-output combinations of the optical switch are rearranged in a particular manner, such that all the information is transmitted simultaneously [42,43]. A network is said to be RNB when it can incorporate the new I/O link by rearranging some of the switching combinations using the existing OSEs [43]. More details about non-blocking properties and RNB are discussed in Section 4, where a mathematical theorem is provided to proof the non-blocking property of the N×N port switch network.

In Figure 3, it can be seen that all 6 inputs are transmitted to a particular output in parallel depending on the switching states of the OSEs shown in different colors.

3.2. Optimized 6-Port Non-Blocking Reconfigurable Optical Switch Architecture

The proposed HCROS architecture was optimized and a certain number of OSEs were reduced [25]. By reducing the number of OSEs we can achieve a more compact footprint for the optical switch and a reduction in OSEs also minimizes the power consumption and IL caused due to the drop/bar state of OSEs, which consume more power in the drop/bar state than the through/cross state [38]. However, this reduction in OSEs count can lead to a decrease in some routing choices that can deteriorate the performance for some applications. As a result of optimization, we eliminated 3 OSEs in total, the 2 OSEs labeled as SE₁, SE₂ in the left half and SE₁₁ in the right half of the proposed HCROS architecture. The optimized architecture of optical switch is shown in Figure 4, where we can observe that after optimization, the total OSE count is 12 labelled as SE₁, SE₂, … SE₁₂. However, the number of waveguide crossings has increased from 6 to 9. A detailed performance analysis of both the un-optimized and optimized designs is discussed in Section 6.

The resulting transfer matrix for the optimized HCROS is expressed in Equation (9).

$$M=R_I{\mathrm{\Omega }}_1{\mathrm{\Omega }}_2{P}_I{\mathrm{\Omega }}_3{P}_O{\mathrm{\Omega }}_4{\mathrm{\Omega }}_5{\mathrm{\Omega }}_6$$

(9)

where R_I, P_I and P_O represent stages without OSEs and consist of straight and cross waveguides. The vectors P_I/P_O define the column/row permutations of the N × N identity matrix and are given by Equations (7) and (8), respectively.

One of the possible switching combinations for optimized HCROS architecture is listed in

Table 4. Switching combinations of OSEs for particular I/O links in the 6-port optimized HCROS.

I/O Links	SE1	SE2	SE3	SE4	SE5	SE6	SE7	SE8	SE9	SE10	SE11	SE12
SC1	DB	DB	DB	DB	DB	DB	TC	TC	TC	TC	TC	TC
SC2	TC	TC	DB	DB	TC	TC	DB	DB	DB	DB	DB	TC
SC3	DB	DB	DB	DB	TC	TC	TC	DB	DB	DB	TC	DB
SC4	DB	DB	DB	DB	TC	TC	DB	TC	TC	TC	TC	TC
SC5	TC	TC	DB	DB	DB	DB	TC	DB	DB	DB	DB	TC
SC6	DB	DB	DB	DB	DB	DB	DB	DB	DB	DB	TC	DB

. The switching combination of 12 OSEs for 6 I/O links including the straight/crossing waveguides are shown. Reduction in total OSEs still maps all 720 combinations including 6 I/O links SC₁, SC₂, …. SC₆ using the reconfiguration of OSEs.

As an example of optimized HCROS architecture we have shown the SC₆ I/O link’s routing combinations in Figure 5. All optical paths are highlighted in separate colors.

The number of active stages, i.e., having OSEs, in the case of the optimized HCROS are reduced from 7 to 6, which then minimizes the computational complexity, i.e., the matrix computation complexity from O(7N²) to O(6N²). Computational complexity is defined as the total number of floating point operations (multiplications and additions) in completing a particular math operation. Usually it is represented by big “O” notation. If two N × N matrices are multiplied then the multiplicative complexity is N² while the additive complexity is N. However, the overall complexity is dominated by multiplications, and is therefore represented by using O(N²).

4. Mathematical Proof for the Non-Blocking Property of HCROS

The non-blocking property of the proposed HCROS architecture is a necessary requirement. Here, we prove the non-blocking property of the proposed HCROS by using transfer matrix approach, which is used in a lot of research work to model a multi-stage optical switch [17,25]. To prove the non-blocking feature of proposed 6-port HCROS, a theorem is presented as follows:

Theorem 1.

For an N × N optical switch to be non-blocking, there exists exactly N! input-output permutations.

Proof. 

To prove that N × N optical switch is non-blocking, we need to prove there exists N! distinct transfer matrices (T.M) for N × N optical switch, which can route N! input-output combinations. Using mathematical induction, let us take N = 2,

• When I₁ → O₁ and I₂ → O₂;   $T.M_1=\left[\begin{array}{cc}1& 0\\ 0& 1\end{array}\right]$
• When I₁ → O₂ and I₂ → O₁;   $T.M_2=\left[\begin{array}{cc}0& 1\\ 1& 0\end{array}\right]$

Since, we have 2 transfer matrices, i.e., 2 = 2!, therefore, for N = 2, the switch is non-blocking. Suppose, the assertion is true for (N-2) ports. This means there exists (N−2)! distinct transfer matrices for (N-2) port optical switch. To show that the assertion is true for N ports, we divide the N × N switch into two layers, one with N-2 ports and the other with 02 ports. An example of such layering is shown in Figure 6.  □

For the upper (N-2) × (N-2) switch, there exists (N-2)! distinct transfer matrices. If only one matrix is chosen out of the (N-2)! possibilities, then there exist exactly N² − N distinct locations where the transfer matrix from the lower 2 × 2 switch can be appended in the N × N transfer matrix of the overall switch. Thus, for every matrix of the upper layer, there exist N² ‒ N distinct N × N transfer matrices when combined with the lower layer. This implies that in total, we have (N² − N)(N − 2)! distinct transfer matrices for the whole N × N switch. Since (N² − N)(N − 2)! = N(N − 1)(N − 2)! = N!, therefore, there are N! distinct transfer matrices, and hence the assertion given in the above theorem is true for N × N switch. This indicates that for an N × N optical switch to be non-blocking, there exists exactly N! input-output permutations.

The rearrangeable non-blocking network is also strictly non-blocking if all the I/O links are set up and torn down simultaneously [28]. In this manuscript, the term “rearrangeable non-blocking” is used in the context of optimized HCROS optical switch, where some of the routing states are lost as a result of optimization. An un-optimized 6x6 HCROS has 15 OSEs has a total of 2¹⁵ = 32,768 switching combinations, whereas 6! = 720 distinct routing states specify different I/O link configurations, which is much smaller than 32,768 possible switching combinations of HCROS. Therefore, there are repetitive combinations that map to the same I/O link [11]. However, if an OSE is replaced with a waveguide crossing or an OSE is constrained in a through/cross (T_C) state, the optical switch can still route all 720 routing states via rearrangement/adjustment of the switching states of the remaining OSEs exploiting the reconfiguration of 2 × 2 OSEs, hence maintaining the property of rearrangeable non-blocking (RNB) switch [11]. Un-optimized HCROS possess 2¹⁵ = 32,768 switching combinations and hold the non-blocking property, while optimized HCROS has 2¹² = 4096 switching combinations, where rearrangement of 12 OSEs leads to RNB properties of the optical switch.

5. Proposed Algorithm

In this section, we propose an algorithm to find the optimal switching combination for specific I/O links with the minimum number of OSEs in drop/bar state. Using the proposed algorithm, we identify the total number of switching combinations for a specific I/O link that can route particular inputs to desired outputs. The algorithm also finds the maximum number of routing combinations that can route the respective I/O link with the minimal number of switches in drop/bar state. The steps involved in the algorithm are detailed in

Table 5. Algorithm-1 to identify the optimal switching combination.

Inputs:N, s, ek, Ci

Outputs:Nc, Nd, Dc

Procedure:

1. Determine Ns = ${\sum }_{k=1}^K{e}_k$

2. Find St = 2Ns

3. Define ETs and EDs using Equation (3)

4. Compute Md for Ci using Equation (4) and Table 2

5. Set Nc = 0 to find total number of combinations

6. Loop i = 1 to St

7.   Choose Ci.

8.   Loop j = 1 to Ns

9.     if (Ci(j) = 0)

10.      SE(j) = ETs using Equation (1)

11.     else

12.      SE(j) = EDs using Equation (2)

13.   end

14.   Get Ω1, Ω2, … ΩS using SE(j) for every switching stage using Equation (5).

15.   Calculate M = Ω1, Ω2, … ΩS using Equation (4)

16.     If (M = Md)

17.      Nc = Nc + 1

18.      Store Ci

19.     else

20.      Ignore Ci.

21.   Determine Nd.

22.   Find Dc = Ci (min(ED)).

23. end

.

5.1. Notations and Proposed Algorithm

• N: number of input-output ports
• s: number of stages
• e_k: number of OSEs in each stage
• N_s: total number of OSEs
• S_t: possible switching states
• M_d: Desired transfer matrix
• C_i: desired I/O link for particular routing combination
• Nc: total number of switching combinations for respective I/O link
• N_d: total number of combinations with least number of OSEs in drop/bar state
• D_c: optimal number of OSEs in drop/bar state

5.2. Analysis Using Proposed Algorithm-1 for HCROS

Using the algorithm-1 described in Table 5, we calculated the total number of possible switching combinations for each I/O link, i.e., SC₁, SC₂, SC₃, SC₄, SC₅ and SC₆.

Table 6. Analysis of optimal switching combinations in un-optimized HCROS.

I/O Links	Total Possible Combinations	No. of Optimal Combinations	No. of OSEs in Drop/Bar State	No. of OSEs in Through/Cross State
SC1	34	14	6	9
SC2	34	14	5	10
SC3	144	1	0	15
SC4	34	14	5	10
SC5	34	14	6	9
SC6	144	1	3	12

shows the outcome of proposed algorithm-1 for un-optimized HCROS.

We can observe that the total number of possible combinations for each I/O link is either 34 or 144. In the case of SC₁, SC₂, SC₄ and SC_5, the number of optimal switching combinations in the drop/bar state is 14, however in the case of SC₃ and SC₆ only one optimal switching combination is found. We have also calculated the number of OSEs used in each I/O link. I/O link SC₃, in its optimal switching configuration utilizes all 15 OSEs in the through/cross state, i.e., no OSE is found in a drop/bar state, hence, we can say that SC₃ in its optimal switching configuration saves maximum power consumption. I/O link SC₆ identifies 3 OSEs in drop/bar state that can route the particular routing combination. Algorithm-1 can identify more than one switching combinations for some I/O links, therefore, if there exists more than one optimal switching combination, selection of the configuration should be adopted according to the design requirements. Due to the symmetry of HCROS architecture across both left and right sides, SC₁, SC₅ utilizes 6 OSEs while SC₂, SC₄ employs 5 OSEs in the optimal switching configuration.

In addition to 6 I/O links, we calculated the total number of possible switching combinations of un-optimized HCROS for all possible 720 I/O permutations shown in Figure 7. It can be seen that the maximum number of total switching combinations for a particular I/O link is 144 and a minimum of 32, shown in blue. The number of optimal switching combinations for all 720 I/O permutations are shown in orange. A maximum value of 36 for optimal switching combinations was observed in 720 I/O permutations for un-optimized HCROS. SC₁, SC₂, SC₄, SC₅ and SC₆ are located at the 567th, 416th, 270th, 144th, 120th and 720th permutation index, respectively, in Figure 7.

The number of OSEs in drop/bar and through/cross states in optimal switching combinations for un-optimized HCROS is shown in Figure 8, where it can be observed that at the 270th permutation index for the SC₃ I/O link, the maximum of 15 OSEs are found in through/cross state while no OSE is found in a drop/bar state.

Similarly, for optimized HCROS we calculated the optimal switching combinations. Since, 3 OSEs are replaced with waveguide crossings in HCROS as a result of optimization, therefore, the new OSE count is 12 in the optimized HCROS. We can observe in

Table 7. Analysis of optimal switching combinations in optimized HCROS.

I/O Links	Total Combinations	No. of Optimal Combinations	No. of OSEs in Drop/Bar State	No. of OSEs in Through/Cross State
SC1	3	3	6	6
SC2	9	7	5	7
SC3	18	1	0	12
SC4	3	3	5	7
SC5	9	7	6	6
SC6	18	1	3	9

, that total combinations for specified I/O links are reduced as we have minimized the redundancy of HCROS. However, optimized HCROS still route all the 720 I/O links, which can employ optimal switching combination of OSEs. Similar to un-optimized HCROS, SC₃ also routes all respective inputs and outputs in a through/cross state. We noticed that the number of optimal combinations has been reduced, however, the number of OSEs in drop/bar state still remains the same.

Similar to un-optimized HCROS, the total number of possible switching combinations of optimized HCROS for all possible 720 I/O permutations are shown in Figure 9. It can be observed that the maximum number of total switching combinations for a particular I/O link is 18 and a minimum of 2, as shown in blue. The Figure 9 also shows the number of optimal switching combinations for all 720 I/O permutations in optimized HCROS. A maximum value of 12 for optimal switching combinations was observed in 720 I/O permutations for optimized HCROS.

In optimal switching combinations, the numbers of OSEs in drop/bar and through/cross states for optimized HCROS are shown in Figure 10, where it can be observed that, similar to un-optimized HCROS, for the SC₃ I/O link, all 12 OSEs are found in the through/cross state while no OSE is found in the drop/bar state. An important point in the case of optimized HCROS is that for some I/O permutations in optimized HCROS, maximum and optimal switching combinations are the same, i.e., 6 OSEs in drop/bar states and 6 in drop/through states, which means the maximum combination is the optimal switching combination in optimized HCROS. However, optimized HCROS still performs better than un-optimized HCROS in terms of power consumption and insertion loss due to reduced number of OSEs.

6. Comparisons, Analysis and Simulation Results

In this section, we compare the proposed HCROS with different non-blocking switch architectures, i.e., Spanke-Benes [30], cross switch matrix [31], PILOSS [32] and recently proposed 6-port optical switches/routers in [24,36]. In addition, we also analyzed the performance of the proposed HCROS in terms of IL and power consumption.

6.1. Calculation of Insertion Loss and Power Consumption for HCROS

In this article, we assumed that the IL and power consumption of 2 × 2 MR based OSE are as per the specifications listed in

Table 8. Specifications and performance parameters.

Parameters	Drop/Bar State	Through/Cross State
Power Consumption of OSE	PD	PT
	200 µW [38]	0 W [38]
Insertion Loss of OSE	ILD	ILT
	1.4 dB [38]	0.2 dB [38]
IL of Waveguide Crossing	ILC
	0.16 dB [44]

. The values shown are the result of experimental measurements and incorporate the effect of process variations caused by physical parameters [38].

In the rest of this article, our results and analysis rely on the specifications provided in Table 8.

6.2. Comparisons, Results and Analysis

We compared the proposed HCROS with cross switch matrix, Spanke-Benes, PILOSS and different optical switches/routers non-blocking switches with the same port count, i.e., N = 6. We calculated the total number of OSEs used in each architecture, estimated the number of waveguide crossings and maximum per path utilization of number of OSEs in each design. Numerical values of the above-mentioned parameters are listed in

Table 9. Hardware cost comparisons and analysis for N = 6.

Switch Topology	Total OSEs	Waveguide Crossings	Max. OSEs in one Path
PILOSS [32]	36	30	6
Cross Switch Matrix [31]	36	0	11
Reference [24]	24	24	4
Spanke-Benes [30]	15	0	6
Reference [36]	12	11	4
RoR [37]	15	8	7
HCROS Un-Optimized	15	6	7
HCROS Optimized	12	9	5

. We can observe in Table 9, that the proposed HCROS in its un-optimized form consumes less OSEs than the cross switch matrix [31] and PILOSS [32] which is almost 58% lower and the same compared to Spanke-Benes [30]. However, in optimized form there is a 66%, 50% and 20% reduction in OSEs in comparison to the cross switch matrix/PILOSS, six port router [24] and Spanke-Benes switch architectures, respectively. The number of per path OSEs was also reduced from 7 to 5 with a maximum of 3 OSEs in the drop/bar state for optimized HCROS, which helps to minimize the overall power consumption of switch architecture. The stage count of optimized HCROS in terms of OSEs is also minimized as compared to un-optimized HCROS, which alleviates the impact of IL in switch network.

We undertook a performance analysis of 6-port optical switches/routers in terms of power consumption, maximum insertion loss and minimum insertion loss. For evaluation of the performance parameters, the 2 × 2 micro-ring based OSE was taken as the basic element discussed in Section 2 of the manuscript. We chose the worst-case scenario, which determines the maximum power and loss overhead of 6 × 6 routers. We assumed all OSEs are in a drop/bar state, where maximum power is consumed in switch/router architecture and the maximum effect of insertion loss can be monitored. Maximum power consumption is calculated as the sum of all the OSEs in drop/bar state. Maximum insertion loss is calculated as the sum of all OSUs in drop/bar state while minimum loss is calculated as the sum of all OSEs in through/cross state. Effect of waveguide crossings is also included in the calculation of maximum and minimum insertion loss. The performance analysis of different 6-port routers is shown in

Table 10. Performance analysis of 6-port optical switches/routers.

Switch Topology	Maximum Power (mW)	Maximum Insertion Loss (dB)	Minimum Insertion Loss (dB)
PILOSS [32]	7.2	55.2	12
Cross Switch Matrix [31]	7.2	50.4	7.2
Spanke-Benes [30]	3.0	21	3.0
RoR [37]	3.0	22.28	4.28
HCROS Un-Optimized	3.0	21.96	3.96
HCROS Optimized	2.4	18.24	3.84

. It can be observed from Table 10 that the optimized HCROS has better performance among the different 6-port optical switches/routers, with minimized power consumption and IL. HCROS has the advantage of routing all 6! = 720 I/O links as compared to the router architectures proposed in [24,36] which do not support that feature, therefore they are not included in the performance analysis shown in Table 10. We can observe a significant difference in performance parameters between HCROS and other switches/routers designs as shown in Table 10, therefore, detailed analysis for all 720 routing states is constrained to un-optimized and optimized HCROS.

6.3. Power Consumption of HCROS

We calculated the maximum and optimal power consumption for un-optimized and optimized HCROS designs. For the total power P consumption, we used the following Equation (10).

$$P={\displaystyle \sum P_D}+{\displaystyle \sum P_T}$$

(10)

where P_D is the power consumption of OSEs in a drop/bar state while P_T is the power consumption of OSEs in through/cross state. Based on the switching combinations of un-optimized and optimized HCROS for different I/O links, we present the maximum and optimal power consumption in

Table 11. Power consumption of OSEs in HCROS.

I/O Links	HCROS Un-Optimized		HCROS Optimized
	Maximum (PMax_UO_HCROS)	Optimal (POpt_UO_HCROS)	Maximum (PMax_O_HCROS)	Optimal (POpt_O_HCROS)
SC1	10*PD + 5*PT	6*PD + 9*PT	6*PD + 6*PT	6*PD + 6*PT
SC2	9*PD + 6*PT	5*PD + 10*PT	7*PD + 5*PT	5*PD + 7*PT
SC3	12*PD + 3*PT	15*PT	8*PD + 4*PT	12*PT
SC4	9*PD + 6*PT	5*PD + 10*PT	5*PD + 7*PT	5*PD + 7*PT
SC5	10*PD + 5*PT	6*PD + 9*PT	8*PD + 4*PT	6*PD + 6*PT
SC6	15*PD	3*PD + 12*PT	11*PD + 1*PT	3*PD + 9*PT

.

Based on the power calculations given in Table 11 and specification parameters assumed in Table 8, we calculated the maximum P_{Max_UO_HCROS}/P_{Max_O_HCROS} and optimal P_{Opt_UO_HCROS}/P_{Opt_O_HCROS} power consumptions in all 6 switching combinations for un-optimized and optimized HCROS architectures, respectively, and the results are shown in Figure 11. P_{Max_UO_HCROS}, P_{Max_O_HCROS}, P_{Opt_UO_HCROS} and P_{Opt_O_HCROS} are defined as follows.

• P_{Max_UO_HCROS} is the maximum power consumption in un-optimized HCROS
• P_{Max_O_HCROS} is the maximum power consumption in optimized HCROS
• P_{Opt_UO_HCROS} is the optimal power consumption in un-optimized HCROS
• P_{Opt_O_HCROS} is the optimal power consumption in optimized HCROS

Significant improvement in power consumption is noted in the case of P_{Opt_UO_HCROS}, P_{Max_O_HCROS} and P_{Opt_O_HCROS} as compared to P_{Max_UO_HCROS}. We observed P_{Max_UO_HCROS} as 3.0 mW for SC₁ I/O link, which is minimized up to 0.6 mW in the case of P_{Max_O_HCROS} and P_{Opt_O_HCROS} which is 80% lower than P_{Max_UO_HCROS}. Since some of the redundant switching states are lost as a result of optimization, therefore P_{Opt_UO_HCROS} and P_{Opt_O_HCROS} result in same power consumption for all I/O links, i.e., the number of OSEs used in drop/bar states are equal in both cases. Minimum power consumption is observed for I/O link SC₃ in the case of P_{Opt_UO_HCROS} and P_{Opt_O_HCROS}, which means that for SC₃ all OSEs are in a through/cross state and consume approximately negligible power, i.e., 0 mW in this case.

In addition to 6 I/O links, we calculated the power consumption of all 720 I/O links for un-optimized HCROS. Results are shown in Figure 12, where it can be observed that optimal reconfiguration of OSEs lead to minimum power consumption P_{Opt_UO_HCROS} in all 720 permutations. Maximum P_{Max_UO_HCROS} of 3.0 mW of power consumption is observed for the 720th permutation, i.e., SC₆. The optimal switching combination significantly reduces the power consumption of un-optimized HCROS.

Similarly, for optimized HCROS, the results of the optimal switching combination show a noteworthy improvement in power consumption P_{Opt_O_HCROS} as compared to P_{Max_O_HCROS}. The results of all 720 I/O permutations are shown in Figure 13. It can be observed that in some cases, P_{Max_O_HCROS} equals P_{Opt_O_HCROS}; this is because the fact maximum and optimal switching combinations of OSEs are equal, hence the same power is consumed in both cases. However, P_{Max_O_HCROS} never crossed the P_{Opt_O_HCROS}, out of 720 I/O permutations 106 I/O permutations have the same power consumption, i.e., P_{Max_O_HCROS} equals P_{Opt_O_HCROS}. In other words, we can conclude that 85% of the time, P_{Opt_O_HCROS} leads to minimum power consumption and 15% of the time, P_{Max_O_HCROS} equals P_{Opt_O_HCROS} in optimized HCROS.

Finally, overall power savings for all 720 I/O links are shown in Figure 14. The difference between P_{Max_UO_HCROS} and P_{Opt_UO_HCROS} is calculated and shown in blue, while the difference between P_{Max_O_HCROS} and P_{Opt_O_HCROS} is presented in orange. A maximum power saving of 2.4 mW and 1.6 mW is reported in un-optimized and optimized HCROS, respectively, as a result of optimized reconfiguration.

6.4. Insertion Loss in HCROS

We estimated IL for un-optimized and optimized HCROS architectures as worst and optimal cases. First, we calculated total IL of the whole switch by considering OSEs in drop or through states for all 720 I/O links using the following Equation (11).

$$IL={\displaystyle \sum I{L}_C}+{\displaystyle \sum I{L}_D}+{\displaystyle \sum I{L}_T}$$

(11)

Using algorithm-1, we can find more than one optimal switching combinations for one I/O link, so the appropriate combination can be selected and HCROS can be reconfigured according to the design requirements. Based on the results of Table 6, we chose one of the optimal switching combinations from each I/O links and this is shown in pictorial form for un-optimized HCROS architecture in Figure 15a–f, which is especially helpful in analyzing the effect of insertion loss of the proposed HCROS in both optimal un-optimized and optimized forms.

Similarly, one of the optimal routing combinations for each I/O link in the optimized HCROS architecture is shown in Figure 16a–f. We note that SC₁/SC₅ utilize a maximum of 6 OSEs in the drop/bar state and SC₃ requires no OSE in the drop/bar state for optimal configuration, where all OSEs are in through/cross states that alleviate the effect of IL and minimize power consumption in optimized HCROS architecture.

IL is the sum of waveguide crossing loss (IL_C) and loss induced due to switching states of OSE in drop (IL_D) or through (IL_T). Considering the switching states and waveguide crossings in switch architecture, IL_S for each I/O link was estimated and listed in

Table 12. Insertion loss of OSEs in HCROS.

I/O Links	HCROS Un-Optimized		HCROS Optimized
	Maximum (ILMax_UO_HCROS)	Optimal (ILOpt_UO_HCROS)	Maximum (ILMax_O_HCROS)	Optimal (ILOpt_O_HCROS)
SC1	6*ILC + 10*ILD + 5*ILT	6*ILC + 6*ILD + 9*ILT	9*ILC + 6*ILD + 6*ILT	9*ILC + 6*ILD + 6*ILT
SC2	6*ILC + 9*ILD + 6*ILT	6*ILC + 5*ILD + 10*ILT	9*ILC + 7*ILD + 5*ILT	9*ILC + 5*ILD + 7*ILT
SC3	6*ILC + 12*ILD + 3*ILT	6*ILC + 15*ILT	9*ILC + 8*ILD + 4*ILT	9*ILC + 12*ILT
SC4	6*ILC + 9*ILD + 6*ILT	6*ILC + 5*ILD + 10*ILT	9*ILC + 5*ILD + 7*ILT	9*ILC + 5*ILD + 7*ILT
SC5	6*ILC + 10*ILD + 5*ILT	6*ILC + 6*ILD + 9*ILT	9*ILC + 8*ILD + 4*ILT	9*ILC + 6*ILD + 6*ILT
SC6	6*ILC + 15*ILD	6*ILC + 3*ILD + 12*ILT	9*ILC + 11*ILD + 1*ILT	9*ILC + 3*ILD + 9*ILT

. We have defined certain terms for insertion loss calculation, i.e., IL_{Max_UO_HCROS}, IL_{Max_O_HCROS}, IL_{Opt_UO_HCROS}, and IL_{Opt_O_HCROS} are defined as follows:

• IL_{Max_UO_HCROS} is the maximum insertion loss in un-optimized HCROS
• IL_{Max_O_HCROS} is the maximum insertion loss in optimized HCROS
• IL_{Opt_UO_HCROS} is the optimal insertion loss in un-optimized HCROS
• IL_{Opt_O_HCROS} is the optimal insertion loss in optimized HCROS

We counted the number of OSEs in drop/bar or through/cross and included 6 waveguide crossing losses in the case of un-optimized HCROS, and computed the maximum IL_{Max_UO_HCROS} and optimal IL_{Opt_UO_HCROS} losses in HCROS. Similarly, for optimized design, we determined the maximum and optimal losses denoted as IL_{Max_O_HCROS} and IL_{Opt_O_HCROS}. Expressions for each I/O link, showing the influence of insertion loss on switch architectures are listed in Table 12. Based on the calculations provided in Table 12, we analyzed the IL_S induced in switch topologies. Detailed results are shown in Figure 17, where we observe that SC₆ I/O link has a maximum IL of 21.96 dB in IL_{Max_UO_HCROS} with 10 OSEs in drop states. IL_{Opt_UO_HCROS} shows a significant improvement using fewer number of OSEs in drop states with a minimum value of 3.96 dB. IL_{Max_O_HCROS} in comparison to IL_{Max_UO_HCROS} shows major improvements and a maximum loss of 17 dB can be observed, which is 22.5% lower than IL_{Max_UO_HCROS} for SC₆ I/O link. Optimal optimized HCROS architecture loss IL_{Opt_O_HCROS} shows the best performance of all, where the maximum value of 11.04 dB and minimum value of 3.84 dB are reported in the case of SC₁/SC₅ and SC₃ I/O links, respectively, which is almost 37% and 79% lower than IL_{Max_UO_HCROS} for the same configurations.

In addition to 6 I/O links, the analysis of insertion loss for all 720 I/O links for un-optimized HCROS is also presented. Results are shown in Figure 18, where can be seen that optimal reconfiguration of OSEs significantly minimizes insertion loss IL_{Opt_UO_HCROS} in all 720 permutations. A maximum IL_{Max_UO_HCROS} of 21.96 dB of insertion loss is observed for the 720th permutation, i.e., SC₆. Notably, a reduction in insertion loss is observed for optimal switching combinations in un-optimized HCROS. Maximum insertion loss for optimal switching combinations IL_{Opt_UO_HCROS} is observed as 12.36 dB while a minimum value of 3.96 dB was calculated.

Similarly, the results of all 720 I/O permutations for optimized HCROS are shown in Figure 19. In some cases, similar to power consumption, IL_{Max_O_HCROS} equals IL_{Opt_O_HCROS}, since the maximum and optimal switching combinations of OSEs are equal, hence, the same insertion loss value is obtained in both cases. Out of a total 720 I/O permutations, 106 I/O permutations have the same insertion loss, i.e., IL_{Max_O_HCROS} equals IL_{Opt_O_HCROS}. In other words, 85% of the time IL_{Opt_O_HCROS} remains better than IL_{Max_O_HCROS} and 15% of the time IL_{Max_O_HCROS} equals IL_{Opt_O_HCROS} in optimized HCROS. However, IL_{Max_O_HCROS} always remains lower than IL_{Max_UO_HCROS}.

In addition, the average IL for every input to output path for 6 I/O links is presented. We calculated IL_S for each input to output routing combination by counting the number of OSEs used in drop or through states and the number of waveguide crossing involved in particular I/O paths and finally, by taking the arithmetic mean of all input to output pairs for all specific I/O links using the following Equation (12).

$$I{L}_{Avg.}=({\displaystyle \sum _{i=1,j=1}^{n}I{L}_{I_i\to O_j}})/n$$

(12)

For instance, we calculated average insertion loss, Avg. IL_{Max_UO_HCROS} for SC₁ I/O link, where IL for I₁ → O₂ is 5.8 dB, I₂ → O₃ is 7.52 dB, I₃ → O₄ is 2.28 dB, I₄ → O₅ is 6.64 dB, I₅ → O₆ is 7.52 dB and I₆ → O₁ is 2.16 dB and the average IL is 5.29 dB. In similar fashion, Avg. IL_{Max_O_HCROS} for SC₁ I/O link is observed as, I₁ → O₂ is 3.64 dB, I₂ → O₃ is 4.72 dB, I₃ → O₄ is 2.32 dB, I₄ → O₅ is 3.64 dB, I₅ → O₆ is 5.36 dB and I₆ → O₁ is 2.32 dB and the average IL is 3.67 dB. All the average losses for each input to output pair for all configurations are shown in Figure 20. Results presented in Figure 20 show that Avg.IL_{Opt_O_HCROS} has a lower average IL for 6 I/O links. A minimum of 1.28 dB average loss for SC₃ is reported which is almost 80% lower than Avg.IL_{Max_UO_HCROS}.

The reduction in insertion loss for all 720 I/O links is shown in Figure 21. The difference between IL_{Max_UO_HCROS} and IL_{Opt_UO_HCROS} was calculated and is shown in blue, while the difference between IL_{Max_O_HCROS} and IL_{Opt_O_HCROS} is presented in orange in Figure 21. A maximum reduction of 14.4 dB and 9.6 dB insertion loss can be seen as a result of the optimized reconfiguration, in un-optimized and optimized HCROS, respectively.

A summary of maximum and minimum power consumption with power saving and maximum and minimum insertion loss with reduction for 720 I/O links in both un-optimized and optimized HCROS architectures is listed in

Table 13. Maximum/minimum power consumption with power saving and maximum/minimum insertion loss with reduction for 720 I/O links.

Parameter		HCROS Un-Optimized		HCROS Optimized
Power (mW)	Maximum/Minimum	Maximum (PMax_UO_HCROS)	Optimal (POpt_UO_HCROS)	Maximum (PMax_O_HCROS)	Optimal (POpt_O_HCROS)
	Max. Power	3.0	1.4	2.4	1.4
	Min. Power	1.2	0	0.6	0
Insertion Loss (dB)	Maximum/Minimum	Maximum (ILMax_UO_HCROS)	Optimal (ILOpt_UO_HCROS)	Maximum (ILMax_O_HCROS)	Optimal (ILOpt_O_HCROS)
	Max. IL	21.96	12.36	18.24	12.24
	Min. IL	11.16	3.96	7.44	3.84
Power Saving (mW)	Maximum/Minimum	Difference (PDiff_MaxtoOpt_UO_HCROS)		Difference (PDiff_MaxtoOpt_O_HCROS)
	Max. Power Saving	2.4		1.6
	Min. Power Saving	0.4		0
Insertion Loss Reduction (dB)	Maximum/Minimum	Difference (ILDiff_MaxtoOpt_UO_HCROS)		Difference (ILDiff_MaxtoOpt_O_HCROS)
	Max. IL Reduction	14.4		9.6
	Min. IL Reduction	2.4		0

. Our analysis shows that optimized HCROS with optimized reconfiguration with 12 OSEs shows significant improvements in overall power consumption and insertion loss in comparison to un-optimized HCROS. Up to 67% improvement in power consumption and 44% efficiency in insertion loss for optimized HCROS is reported. Similarly, a 33% power saving and reduction in insertion loss is also observed as in the optimized HCROS with optimal switching combinations.

7. Conclusions

In this article, we proposed an optimized reconfigurable architecture of a 6 × 6 optical switch called the HoneyComb optimized reconfigurable optical switch (HCROS) in different configurations. First, we presented an un-optimized architecture of HCROS using 15 OSEs and further optimized that design to reduce the number of OSEs to 12, which is an almost 20% reduction in overall OSEs. Furthermore, we proposed an algorithm to identify the minimum number of OSEs in an active drop/bar state to reconfigure the optical switch, which helps to alleviate the impact of insertion loss and provides power efficiency, and achieved an optimized reconfiguration. We compared the proposed HCROS with different non-blocking architectures, e.g., cross switch matrix, PILOSS, Spanke-Benes and different six-port switches/routers, where we found a maximum of 66% decrease in OSEs. Lastly, a comprehensive analysis of power consumption and insertion loss of HCROS in different configurations for 720 I/O links showed significant improvements in both parameters, i.e., power consumption and IL were reported in this article. This study could be utilized for a 6-port optical switch in the construction of cluster Mesh/3D ONoCs to meet the requirements of data transmission for future applications. In the future, we intend to extend this design in two ways (1) investigate the impact of HCROS on crosstalk noise and application mapping in ONoCs, and (2) explore the suitability of HCROS for Mach-Zehnder based OSEs.