1. Introduction
Present-day micromechanical accelerometers are widely used in different types of transport and electronic means from aerospace, water and auto transport systems to mobile phones and new generation video game consoles [
1,
2,
3,
4,
5,
6]. There are many kinds of transducers in present micromechanical accelerometers, such as capacitive, piezo-resistive, electromagnetic, optical, thermal convective, acoustic waves resonant, field emission, tunnel transducers and so on [
6]. The micromechanical accelerometers with capacitive transducers are widely used due to relatively simple transducer structure, high-sensitivity, reliability, thermal stability, excellent linearity, resolution, bandwidth, good compatibility with integrated circuits technology, and consequently low cost [
7,
8,
9,
10,
11,
12,
13,
14].
Together with the transducers, the important functional blocks of micromechanical accelerometers are primary signal processing devices, which vastly determine characteristics of the sensory microsystems for motion parameters registration [
14,
15,
16,
17,
18,
19]. In capacitive accelerometers, the relative simplicity of a transducer’s construction and technology requires relatively complex signal processing devices for accurate measuring the nanoscopic changes of the proof mass position in capacitive transducers. As a result, capacitive accelerometers are more complex in comparison to many other sensors, e.g., resistive strain gauges [
16].
In the capacitive transducers, the nanoscopic displacement of the proof mass and corresponding capacity change induced by acceleration can be measured by detecting a change of charge, voltage, electric current, or frequency of an oscillator with the capacitive transducer in its frequency control circuit [
19].
Figure 1 shows corresponding types of signal processing devices (SPD) for micromechanical capacitive accelerometers. Every type of SPD can be performed in both open-loop or closed-loop applications. Additionally, there are two variants of closed-loop SPD with frequency output: force balance loop and phase-locked loop [
19]. Capacitive accelerometers with voltage control closed-loop signal processing devices are characterized by higher linearity and wider dynamic range in comparison with open-loop analogs. Moreover, the switching-capacitor charge-based technique is conventionally used in closed-loop SPD to effectively suppress flicker noise [
19]. Therefore, voltage control closed-loop SPD are frequently used today especially for high-sensitivity and high accuracy MEMS accelerometers [
8,
9,
10,
11,
12,
13].
However, there are the following disadvantages of voltage control closed-loop signal processing devices:
This work is devoted to a comprehensive solution of aforementioned problems by means of development and comparative analysis of three IP-core projects of highly sensitive open-loop signal processing devices with frequency output for capacitive MEMS accelerometers. The first is an analog scheme SPD project based on harmonic LC or RC oscillators considered in
Section 3. The second one is a well scalable fully digital scheme SPD project discussed in
Section 4. The third project is a mixed-signal SPD investigated in
Section 5. The common principles of the open-loop frequency control signal processing devices for the capacitive MEMS accelerometers are considered in
Section 2.
Section 6 presents the results of comparative analysis of the proposed SPD projects.
3. Analog Scheme of SPD Project
The first open-loop frequency-based SPD IP-core project used harmonic LC oscillators and CMOS analog scheme of the mixer. A scheme of this SPD project without oscillators is presented in
Figure 4. The names and assignments of the SPD’s external signals are given in
Table 1.
According to
Figure 4, the proposed scheme contained the following functional blocks:
Nonlinear differential cascade on the transistors VT1–5, which combine the functions of a mixer, rectifier and amplifier;
Detector on the transistors VT6–8 and the capacitor C1;
First comparator in the form of CMOS-inverter on the transistors VT9 and VT10;
First low-pass filter on the capacitor C2;
Second comparator in the form of CMOS-inverter on the transistors VT11 and VT12;
Output low-pass filter on the capacitor C3.
A layout of IC implementation of the analog frequency-based SPD scheme is presented in
Figure 5. This project was implemented for CMOS 0.12 μm technology in layout editor of CAD Microwind [
24].
Results of electrical modeling of the analog frequency-based SPD project for initial conditions Δ
f = 0 and correspondent differential frequency
fD =
fD0 = 100 MHz are shown in
Figure 6.
Basic parameters of the transistors and external signals of SPD are given in
Table 2.
Distinctive features of the CMOS scheme proposed in
Figure 4 are:
According to the scheme of SPD in
Figure 4, harmonic signals
Sin1 and
Sin2 of the oscillators were fed to the inputs of the differential cascade on the transistors
VT1–5. Frequency of the signal
Sin1 was dependent on the measured acceleration
f1 ± Δ
f(
ax). Frequency of the signal
Sin2 was independent on the acceleration. The cascade operating point was calculated to provide a nonlinear mode of operation. In this mode, the differential cascade combined the functions of a mixer, a rectifier and an amplifier with a gain of 10 for the parameters of input signals (
Sin1,
Sin2) and offset voltages (
S3,
S4) given in
Table 2.
As a result, according to transients in
Figure 6, output signals of differential cascade
S1 and
S2 were amplified, rectified and modulated in amplitude with a frequency equal to the frequency difference
fD of the input signals
Sin1 and
Sin2.
Next, the signals
S1 and
S2 were fed to the detector inputs on transistors
VT6–8 and capacitor
C1. Detector transistors provided a superposition, inversion and amplification of half-phases of the signals
S1 and
S2 in signal
S5 in accordance to
Figure 7. Transients of the detector in
Figure 7 were simulated without capacitor
C1, which suppressed the pulsation amplitude and selected a signal enveloping
S5 with difference frequency
fD shown in
Figure 6.
One of the key design tasks of proposed signal processing device was a definition of the initial values of frequencies
f0 and
f1 in
Table 2.
The minimum value of the frequency
f0, independent of acceleration
ax, was determined by the maximum allowable design area
SLmax of the inductance
L2 for the Oscillator 2 on the chip:
The maximum value
f1max of the frequency
f1 of the Oscillator 1, corresponding to maximum positive acceleration
axmax, was determined as follows:
where
ftech is a maximum oscillator frequency defined by the CMOS technology used. We define
ftech as the frequency at which the amplitude of the oscillator signal decreases by 3 dB relative to the maximum value.
The minimum value
f1min of the frequency
f1 of the Oscillator 1, corresponding to maximum negative acceleration −
axmax, is determined by expression:
where
Kpull < 1 is an empirical coefficient defining the minimum ratio
fDmin/
f0 (where
fDmin =
f1min −
f0) at which the pulling effect for oscillators is guaranteed to be impossible for the entire working temperature range. The value of
Kpull should be experimentally measured for the CMOS technology used.
The initial value
f1, corresponding to
ax = 0, is determined as follows:
Basic parameters of the transducer used for SPD modeling and for calculation of the frequencies
f0 and
f1 are given in
Table 3.
Next, the signal
S5 was fed to the input of series-connected comparators on transistors
VT9–12 and low-pass filters on capacitors
C2 and
C3. CMOS-inverters were used as the comparators. This functional block transformed harmonic-like signal
S5 in the rectangular output digital signal
Sout with the same frequency
fD. The capacitors
C2 and
C3 deleted undesirable pulsations in the output. Corresponding transients are shown in
Figure 6.
Figure 8 shows the transients of the considered SPD project for the negative and positive accelerations, which induced output frequency changes Δ
f = −50 MHz (
fD = 50 MHz in
Figure 8a for negative direction of the acceleration) and Δ
f = 50 MHz (
fD = 150 MHz in
Figure 8b for positive direction of the acceleration).
To illustrate a noise immunity of the considered SPD, transients for noised signals of the oscillators
Sin1 and
Sin2 with an RMS noise
NRMS = 0.5 V are shown in
Figure 9.
According to
Figure 9, an excellent functionality of the considered frequency-based SPD was saved even for RMS noise of input signals
S1 and
S2 (
NRMS = 0.5 V) higher than amplitude of these signals (0.1 V). However, noise of input signals increased a jitter
Jout of output signal
Sout in comparison with the transients of
Sout without input noise in
Figure 6. Considering a jitter
Jout of digital output signal as a maximum time interval between corresponding rising fronts of
Sout taking into account input noise (in
Figure 9) and ideal condition (without input noise in
Figure 6) we got a value
Jout = 0.41 ns, which was 4.1% of the period of ideal
Sout (
Tout = 10 ns in
Figure 6). It should be noted, that real RMS of input signals noise may be considerably lower than an amplitude of these signals (in the considered project, 0.1 V). In this case, output jitter will be considerably lower too.
An important advantage of the considered SPD project is a possibility of increasing the frequency of the oscillators to maximum values determined by the CMOS-technology used and the permissible level of phase noise. According to Equations (11) and (13), higher frequency of the SPD oscillators provides an increase in sensitivity and dynamic range of the accelerometer.
However, a drawback of the developed SPD project is a bad scalability when the changing of CMOS-technology is needed. In this case, a full complex of project calculations and modeling is needed to provide a good functionality and necessary values of the parameters.
4. Fully Digital Scheme of SPD Project
The second IP-core project of open-loop frequency-based SPD used oscillators of digital rectangular pulses and a fully digital CMOS-scheme of the mixer. A scheme of this SPD project without oscillators is presented in
Figure 10. The names and assignments of SPD’s external signals are given in
Table 4.
According to
Figure 10, the proposed scheme contains the following functional blocks:
Digital mixer of rectangular input signals Clk1 and Clk2 on the XOR logic element DD1;
Functional block for determination of the duration of the mixer’s output pulses on the logic elements AND (DD3) and NOT (DD4), and on the digital counter DD6;
Functional block for determination of the intervals between mixer output pulses on the logic elements OR (DD2) and the digital counter DD5;
RS-trigger on the logic elements NOR (DD7, DD8) for differential-frequency output signal Sout synthesis.
A layout of IC implementation of the fully digital frequency-based SPD scheme for CMOS 0.12 μm technology is presented in
Figure 11. The project was implemented in layout editor of CAD Microwind [
24].
Results of electrical modeling of the digital frequency-based SPD project for the period of output pulses
TD = 36 ns (differential frequency
fD = 27.78 MHz) are shown in
Figure 12.
Basic parameters of CMOS 0.12 μm technology for digital frequency-based SPD are presented in
Table 5.
According to the scheme of the considered SPD in
Figure 10 and transients in
Figure 12, rectangular digital signals
Clk1 and
Clk2 of the oscillators were fed to the inputs of the mixer (XOR element
DD1), which formed the signal
CR1. Frequency of the signal
Clk2 was dependent on the measured acceleration
f1 ± Δ
f(
ax). The frequency of the signal
Clk1 was independent of the acceleration. Pulse duration of
CR1 was modulated by phase difference of input signals
Clk1 and
Clk2.
Next, the signal
CR1 was fed to the inputs of two functional blocks for determining the duration of the output pulses of the mixer and the intervals between these pulses. The block for determining the duration of the mixer pulses included the elements AND (
DD3), NOT (
DD4), and counter
DD6. Correspondently, the block for determining the intervals between mixer pulses included the element OR (
DD2) and counter
DD5. Element
DD3 filled the pulses of the
CR1 with pulses of the clock-generator (signal
Clock). Correspondently, element
DD2 was filled by pulses of the signal clock at the intervals between pulses of the
CR1 (
Figure 12). Output signal
CT1 of the OR element
DD2 was fed to the counting input
C of the counter
DD5. Output signal
CT2 of the AND element
DD3 was fed to the counting input
C of the counter
DD6. On the reset-inputs
R of the counters
DD5 and
DD6 a direct (on the
R input of
DD5) and an inversed by inverter
DD4 (on the
R input of
DD6) mixer’s signal
CR1 were fed.
The outputs
Q of counters
DD5 (signal
Q3) and
DD6 (signal
QQ3) were the high bits of the output buses of the counters. A high logic level on these outputs was formed when maximum pulse duration of
CR1 (for
QQ3) or maximum interval between pulses of
CR1 (for
Q3) occurred (
Figure 12). For this purpose, the following ratio between frequency
f0 of
Clk1 and Clock-frequency
fClock is necessary:
where
B is a number of bits of the counter’s output bus.
Next, the counter output signals
Q3 and
QQ3 were fed to the inputs of the RS-trigger on the NOR elements
DD7 and
DD8. The RS-trigger formed an output signal
Sout with differential-frequency
fD (
Figure 12).
In the considered digital SPD layout presented in
Figure 10, the number of bits of the counter’s output bus (
B) was equal to four. According to Equation (20) and taking into account the parameters of CMOS 0.12 μm technology, following frequencies for transients in
Figure 12 were selected:
fClock = 2.5 GHz and
f0 = 250 MHz.
The frequency
f0 of digital SPD was lower than in the analog SPD project considered in
Section 3 due to Equation (20). Therefore, in accordance with Equations (11) and (13), the sensitivity and a dynamic range of the digital SPD were lower too. In contrast to the analog SPD project, the digital SPD project is fully scalable for various CMOS technologies. For example, and to illustrate the noise immunity of the considered SPD,
Figure 13 shows the transients of the digital SPD project in the same manner as the
Figure 10 layout for the CMOS 50 nm technology, of which basic parameters are presented in
Table 6. The transients in
Figure 13 were modeled for
fClock = 5 GHz,
f0 = 500 MHz and for input signals
Clk1,
Clk2 and
Clock with an RMS noise
NRMS = 0.5 V (
Figure 13b).
As the transients in
Figure 12 and
Figure 13 show, the functionality of the digital frequency-based SPD was independent of the CMOS technology parameters. Comparative analysis of the ideal and noised transients in
Figure 13a,b shows that even for comparatively high RMS noise of input signals
Clk1,
Clk2 and
Clock (
NRMS = 0.5 V) the jitter of the output signal
Sout was not increased in contrast to the analog SPD project transients considered in
Section 3. This is because the noise of the input signals can change mainly the shape of the output signal, while the informative parameter of the output signal is its frequency.
5. Mixed-Signal Scheme of SPD Project
The third open-loop frequency-based SPD IP-core project was a mixed-signal project. A scheme of this SPD without oscillators is presented in
Figure 14. This project combined the advantages of the analog and fully digital SPDs considered in
Section 3 and
Section 4. Like the fully digital SPD, this mixed-signal project uses LC oscillators of digital rectangular pulses (input signals
Clk1 and
Clk2 in
Figure 14) and a mixer on the bases of XOR CMOS-element on the transistors
VT1–6. In contrast to the digital SPD, in this case, like the analog SPD project, the synthesis of the output rectangular differential-frequency signal
Sout used two series-connected CMOS-inverters on the transistors
VT7–10 and low-pass filters based on the capacitors
C1,
C2 and
C3. The first low-pass filter
C1 was included in the XOR scheme in accordance with
Figure 14.
A layout of IC implementation of the mixed-signal frequency-based SPD scheme for CMOS 50 nm technology, of which basic parameters are presented in
Table 6, is shown in
Figure 15. The project was implemented in layout editor of CAD Microwind [
24].
The parameters of the capacitors
C1–3 are presented in
Table 7.
Results of electrical modeling of the mixed-signal frequency-based SPD project for a frequency of the signal
Clk1 are as follows:
f0 = 50 GHz, initial frequency of the signal
Clk2 f1 = 48.08 GHz, period of output pulses
TD = 520 ps, initial differential frequency
fD0 = 1.92 GHz are shown in (
Figure 16).
According to the scheme in
Figure 14 and transients in
Figure 16, rectangular digital signals
Clk1 and
Clk2 of the oscillators were fed to the inputs of a XOR-mixer (
VT1–6) with low-pass filter (
C1), which formed a signal
S1 with differential frequency
fD. Frequency of the signal
Clk2 was dependent on the measured acceleration
f1 ± Δ
f(
ax). Frequency
f0 of the signal
Clk1 was independent of the acceleration. Next, two series-connected inverters on transistors
VT7–10 and low-pass filters on capacitors
C2 and
C3 deleted pulsations of the signal
S1 and formed the output digital signal
Sout.
Figure 17 presents the transients for positive (Δ
f = 0.46 GHz and
fD = 2.38 GHz,
Figure 17a) and negative (Δ
f = −1.42 GHz and
fD = 0.5 GHz,
Figure 17b) directions of measured acceleration.
To study a noise immunity of the mixed-signal frequency-based SPD, an analysis of the transients for noised input signals
Clk1 and
Clk2 with a band of RMS noise 0.1–0.7 V was executed.
Figure 18 shows the noised transients for initial conditions (Δ
f = 0,
f0 = 50 GHz and
fD0 = 1.92 GHz) with RMS noise
NRMS = 0.1 V (
Figure 18a) and
NRMS = 0.5 V (
Figure 18b).
Figure 19 presents the dependence of an output signal jitter on RMS noise of the input signals. This dependence was obtained by statistical averaging over a sample of 25 transients for each RMS noise value.
In accordance with the dependence in
Figure 19, jitter
Jout of output differential-frequency signal
Sout monotonously increased with increasing RMS of input noise. Even for high RMS of input noise 0.1–0.7 V, the output jitter
Jout was less than 2–16 ps, which corresponds to 0.4–3% of the period of output signal. Moreover, as it was shown in
Section 2.4, output frequency measuring during post-processing significantly decreased the influence of output jitter on the post-processing results due to averaging of the output signal period
TD on the period of high-stability clock oscillator
TCLK.
6. Results of Comparative Analysis and Discussion
Comparative analysis of three developed IP-core projects of highly sensitive open-loop signal processing devices with frequency output for capacitive MEMS accelerometers allows the following conclusions to be made.
The analog project of frequency-based SPD considered in
Section 3 has a comparatively simple CMOS scheme (12 transistors and three capacitors in
Figure 4). It uses high-frequency harmonic oscillators, the frequencies of which are limited only by the parameters of the CMOS-technology used and power dissipation requirements. In accordance with Equations (11) and (13), high frequency of the oscillators increases sensitivity and expands dynamic range of MEMS-accelerometers with the considered SPD. According to
Figure 9, functionality of this frequency-based SPD is saved even for RMS noise of input signals (
NRMS = 0.5 V) higher than amplitude of these signals (0.1 V). However, noise of input signals increases a jitter of output signal
Sout to 0.41 ns, which is 4.1% of the period of
Sout.
Compatibility with CMOS-technologies is an important feature of all three SPD projects considered in this study. The drawback of the analog SPD project is a bad scalability. When the CMOS-technology used is changed, a full range of project calculations and modeling is needed to provide a good functionality and necessary values of the parameters.
The fully digital project of frequency-based SPD considered in
Section 4 has a more complex CMOS scheme (
Figure 10) than the analog one. In contrast to the analog SPD scheme, oscillators of digital rectangular pulses are used. The frequency of sensing oscillators in digital SPD is considerably lower than in the analog one due to the necessity of a clock-generator, the frequency of which is connected with the frequency of sensing oscillators by Equation (20). Therefore, in accordance with Equations (11) and (13), the sensitivity and dynamic range of digital SPD are lower too. In contrast to the analog SPD project, the digital SPD project is fully scalable for various CMOS technologies. This is confirmed by transients of digital SPD projects for both 120 nm (
Figure 12) and 50 nm (
Figure 13) CMOS-technologies.
The mixed-signal project of frequency-based SPD considered in
Section 5 combines the advantages of the analog and fully digital SPD considered in
Section 3 and
Section 4. Like the digital SPD, this mixed-signal project uses oscillators of digital rectangular pulses and a mixer on the bases of XOR CMOS-element. In contrast to the digital SPD and like to the analog SPD project, two series-connected CMOS-inverters and low-pass filters are used to synthesize the output rectangular differential-frequency signal. This approach the scheme of SPD to be simplified, excluding a clock-generator, increasing the frequency of the oscillators to maximum values (which are determined by the CMOS-technology and by permissible level of a phase noise), increasing sensitivity and widening dynamic range. It should be noted, that like the digital SPD, the mixed-signal project is well scalable for various CMOS technologies.
In accordance to the dependence in
Figure 19, jitter of output SPD signal is monotonously increased with an increasing RMS of input noise. But even for high RMS of input noise 0.1–0.7 V, the output jitter in mixed-signal SPD is less than 0.4–3% of the period of output signal. Moreover, as it was shown in
Section 2.4, the influence of the considered output jitter on the accuracy of acceleration measuring will be significantly decreased due to averaging of the output signal period during post-processing.
Results of comparative analysis of the proposed frequency-based SPD projects are briefly presented in
Table 8.
7. Conclusions
This paper focuses on open-loop frequency-based signal processing devices (SPD) for capacitive MEMS accelerometers. The considered frequency-based readout circuits have some advantages to compare with widely used voltage-based SPD, such as a high sensitivity, noise immunity, wide dynamic range and resistance to temperature changes.
In this paper, the differential frequency principle of the open-loop frequency-based SPD is used to develop three CMOS IP-core projects of highly sensitive readout circuits with frequency output: analog, digital and mixed-signal. These signal processing devices form the output rectangular pulses, the frequency of which equals a difference of signal frequencies of two oscillators, one of which contains a micromechanical accelerometer capacitive transducer in the frequency control circuit.
According to the results of the comparative analysis, the analog circuit of the project is characterized by high sensitivity and dynamic range due to the high frequency of oscillators. At the same time, the layout of the analog SPD project is not scalable for various CMOS technologies.
In contrast to this, the digital project is fully scalable for various CMOS-technologies due to the digital rectangular pulses of oscillators and digital mixer. However, the frequency of sensing oscillators in digital SPD is considerably lower than in the analog one due to the necessity of a clock-generator. Correspondently, sensitivity and dynamic range of digital SPD are lower too.
The mixed-signal project combines the advantages of the analog and digital projects. Therefore, the mixed-signal project is a most promising candidate to comprehensively increase the basic parameters of considered frequency-based signal processing devices.
According to the results of modeling, all considered SPD projects demonstrate a high immunity to noise fluctuations of input voltages because not voltage, but frequency is an informative parameter of readout circuit’s output signal and due to the lack of high-gain operational amplifiers. Even for high RMS of input noise 0.1–0.7 V, the output jitter in mixed-signal SPD is less than 0.4–3% of the period of the output signal. Accordingly, only the phase noise of the LC oscillators is the main contribution to the jitter of the output signal, which can be significantly reduced during the post-processing.
It is important to note, that open-loop frequency-based signal processing devices proposed in this study can be successfully used for various capacitive sensors, such as accelerometers, gyroscopes, pressure sensors, inclinometers, etc.