A Fast Transient Response Digital LDO with a TDC-Based Signal Converter

Abstract

The digital low drop-out regulator (LDO) has been used widely in digital circuits for its low supply voltage characteristics. However, as the traditional digital LDOs regulate the output voltage code at a rate of 1 bit per clock cycle, the transient response speed is limited. This paper presents a digital LDO to improve transient response speed with a multi-bit conversion technique. The proposed technology uses a voltage sensor and a time-to-digital converter to convert the output voltage to digital codes. Based on a 65-nm CMOS process, the proposed DLDO reduces the settling time from 147.8 ns to 25.2 ns on average and the response speed is improved by about six times.

1. Introduction

Process scaling causes the continuous reduction in supply voltage. In particular, the application of the Internet of things (IoT) makes the low operating supply voltage more important than ever. In such conditions, dynamic range and bandwidth of integrated circuits are reduced, thus the stability is harder to control. The fine-grained supply voltage management faces a real challenge. In contrast to analog low drop-out regulator (LDO), digital LDOs (DLDO) exhibiting ultra-low operating voltage [1,2,3,4,5,6]. Hence, the DLDO has been widely used in the low source supply voltage conditions and digital load circuits.

The traditional DLDO employs a barrel shifter, whose output code switches 1 bit in a clock cycle [7]. When there is a large transient, it takes a long time to regulate the output voltage to the target value. Some studies have attempted to enhance the transient performance using adaptive regulation technology [8,9,10,11,12,13], but the circuit complexity increases obviously and the multiple times regulation is still required. In [14,15,16], DLDO with a flash analog-to-digital converter (ADC) is proposed. The ADC converts the output voltage to the digital domain and a digital controller provides a multi-bit regulation. Since the comparator offset increases the error of ADC, there may be a deviation in the regulation. In [17,18,19], a time-to-digital converter (TDC) is employed to replace ADC. To convert the output voltage to digital codes, the TDC alters the buffer-gate’s propagation delay by changing the power supply of the buffer-gate. However, the relationship between the power supply and the propagation delay of buffer-gate is nonlinear, and the resolution of TDC is degraded. In this paper, a voltage sensor based on capacitor charging is introduced. Since the proposed TDC operates by changing the time intervals rather than buffer-gate’s propagation delay, the linearity is improved. With a digital controller behind TDC, a multi-bit regulation is achieved and the transient response speed is increased.

This paper is organized as follows. Inl Section 2, the fast response DLDO is proposed with circuit architecture and system dynamic model. Section 3 discusses the circuit implementation of the proposed DLDO. In Section 4, the circuit performance is simulated and the simulation results are shown. Finally, conclusions are drawn in Section 5.

2. System Overview

2.1. The Architecture of the Proposed DLDO

Figure 1 shows circuit diagrams for the baseline DLDO and the proposed DLDO. The proposed DLDO consists of three components. The first component is the TDC-based signal converter, which provides a digital code of the output voltage $V_{\mathrm{OUT}}$ to a digital controller. As the second component, the digital controller outputs a regulation code to drive a PMOS array according to the different inputs. Finally, the PMOS array M provides appropriate current to regulate the $V_{\mathrm{OUT}}$.

Figure 1. The circuit architecture of (a) baseline DLDO and (b) proposed DLDO.

In the TDC-based signal converter, a voltage sensor generates a time signal related to $V_{\mathrm{OUT}}$ by capturing the charging time of a capacitor. The TDC behind the voltage sensor converts the time signal to a digital code $V_{\mathrm{OUT},\mathrm{D}}$. Subtracting $V_{\mathrm{OUT},\mathrm{D}}$ from the reference voltage code $V_{\mathrm{REF},\mathrm{D}}$, the digital subtractor produces an error value e and drives the digital PI controller to vary the number of turned-on transistors in M. When the error value e is 0, $V_{\mathrm{OUT},\mathrm{D}}$ is equal to $V_{\mathrm{REF},\mathrm{D}}$ and output voltage $V_{\mathrm{OUT}}$ is regulated to the target value.

In contrast to the conventional DLDO, the proposed circuit regulates its output voltage using a digital PI controller rather than a shift register. Hence, the number of turned-on transistors can be switched multi-bits in a clock cycle. A faster response is achieved in the proposed circuit.

2.2. System Hybrid Model

To understand the overall system behavior, a system hybrid model for the proposed DLDO is shown in Figure 2. The relationship between input and output of the TDC-based signal converter is rounding linearly and the TDC-based signal converter is modeled as a cascade between gain $K_{\mathrm{TDC}}$ and a rounding function. TDC-based signal converter operates periodically, and the rounding function is followed by a zero-order holder (ZOH). Since the digital PI controller accumulates the previous output of the digital subtractor, it acts as the superposition of a gain $K_{\mathrm{p}}$ and an ideal integrator in discrete-time. The power MOSFETs are driven by a digital circuit, and their parasitic gate capacitances affect the settling time. The effect is modeled as a time delay ${\mathrm{e}}^{-s{T}_{\mathrm{DEL}}}$, where $T_{\mathrm{DEL}}$ is the delay caused by the parasitic gate capacitances. The corresponding transfer function in the z-domain is $z^{-T_{\mathrm{DEL}}}$. The load and power MOSFETs can be approximated as an $RC$ load with gain $K_{\mathrm{DC}}$. The s-domain model of the load and power MOSFETs is

$$P\left(s\right)=\frac{K_{\mathrm{DC}}}{1+\frac{s}{F_{\mathrm{LOAD}}}}$$

(1)

where $F_{\mathrm{LOAD}}$ is the output pole frequency and can be written as $F_{\mathrm{LOAD}}=1/(2\pi ·R_{\mathrm{LOAD}}·C_{\mathrm{LOAD}})$. The corresponding $P\left(z\right)$ in z-domain can be represented as

$$P\left(z\right)=\frac{K_{\mathrm{DC}}{F}_{\mathrm{LOAD}}z}{z-{\mathrm{e}}^{-F_{\mathrm{LOAD}}/F_{\mathrm{S}}}}$$

(2)

where $F_{\mathrm{S}}$ is the sampling frequency and $F_{\mathrm{S}}=1/T$. Thus, the open-loop transfer function between $V_{\mathrm{REF},}\mathrm{D}$ and $V_{\mathrm{OUT}}$ can be written as

$$G\left(z\right)=K·\frac{z^{1-T_{\mathrm{DEL}}}\left(z-\frac{K_{\mathrm{p}}-K_{\mathrm{I}}/F_{\mathrm{S}}}{K_{\mathrm{P}}}\right)}{\left(z-1\right)\left(z-{\mathrm{e}}^{-F_{\mathrm{LOAD}}/F_{\mathrm{S}}}\right)}$$

(3)

where the open-loop gain $K=K_{\mathrm{DC}}{K}_{\mathrm{P}}{F}_{\mathrm{LOAD}}$. Taking the TDC-based signal converter and the zero-order holder into account, the entire closed-loop transfer function of the proposed DLDO in z-domain is

$$Q\left(z\right)=\frac{K·z^{1-T_{DEL}}\left(z-\frac{K_{\mathrm{P}}-K_{\mathrm{I}}/F_{\mathrm{S}}}{K_{\mathrm{P}}}\right)}{z^2+K_{\mathrm{TDC}}K{z}^{2-T_{\mathrm{DEL}}}-\left(1+{\mathrm{e}}^{-F_{\mathrm{LOAD}}/F_{\mathrm{S}}}\right)z-\left(K_{\mathrm{TDC}}K\frac{K_{\mathrm{P}}-K_{\mathrm{I}}/F_{\mathrm{S}}}{K_{\mathrm{P}}}\right)z^{1-T_{\mathrm{DEL}}}+{\mathrm{e}}^{-F_{\mathrm{LOAD}}/F_{\mathrm{S}}}}$$

(4)

Figure 2. The system hybrid model for the proposed DLDO.

Because $T_{\mathrm{DEL}}$ is much smaller than 1, Equation (4) can be approximated to

$$Q\left(z\right)=\frac{K·z\left(z-\frac{K_{\mathrm{P}}-K_{\mathrm{I}}/F_{\mathrm{S}}}{K_{\mathrm{P}}}\right)}{\left(1+K_{\mathrm{TDC}}K\right)z^2-\left(1+{\mathrm{e}}^{-F_{\mathrm{LOAD}}/F_{\mathrm{S}}}+K_{\mathrm{TDC}}K\frac{K_{\mathrm{P}}-K_{\mathrm{I}}/F_{\mathrm{S}}}{K_{\mathrm{P}}}\right)z+{\mathrm{e}}^{-F_{\mathrm{LOAD}}/F_{\mathrm{S}}}}$$

(5)

Equation (5) provides insights into the stability of the proposed DLDO. Compared with the transfer function of the traditional DLDO in [20], the PI controller produces an extra zero at $z=\left(K_{\mathrm{P}}-K_{\mathrm{I}}/F_{\mathrm{S}}\right)/K_{\mathrm{P}}$. The bandwidth and transient response speed of the proposed system are increased.

Figure 3 shows the pole plots of the proposed system under different sampling frequency and integration gain conditions. The simulation parameters are listed in Table 1. As illustrated in the plots, a large sampling frequency damages the system stability. In addition, the higher integration gain of the digital PI controller leads to decreasing stability. Hence, large $F_{\mathrm{S}}$ and $K_{\mathrm{I}}$ should be avoided in the selection of parameters. In Figure 4, the pole plots of the proposed system under variable load are shown and the simulation parameters in Table 1 are used. As illustrated in the plots, the increasing load resistance, which results in a lower load current, reduces the stability of the proposed system. Meanwhile, the decreasing load capacitance degrades the system stability as well. When the load capacitance is decreased to 13 pF, the pole is close to the unit circle, and the system is in critical stability.

Figure 3. The pole plot of the proposed system under: (a) variable sampling frequency; and (b) variable integration gain.

Table 1. The simulation parameters of the system hybrid model.

${\mathit{K}}_{\mathbf{P}}$	${\mathit{K}}_{\mathbf{TDC}}$	${\mathit{K}}_{\mathbf{DC}}$	${\mathit{R}}_{\mathbf{LOAD}}$	${\mathit{C}}_{\mathbf{LOAD}}$	${\mathit{F}}_{\mathbf{LOAD}}$	${\mathit{T}}_{\mathbf{DEL}}$
1	38	0.02	10 $\Omega$	500 pF	32 MHz	10 ps

Figure 4. The pole plot of the proposed system under: (a) variable load resistance; and (b) variable load capacitance.

3. Circuit Implementation

3.1. Voltage Sensor

The transformation of the output voltage from analog to digital is achieved by a TDC-based signal converter, which contains a voltage sensor and a time-to-digital converter. Figure 5 illustrates the circuit scheme of the voltage sensor. During phase ${\varphi }_1$, two plates of the charge capacitor $C_{\mathrm{C}}$ are pre-charge to $V_{\mathrm{OUT}}$ and $V_{\mathrm{IL}}$, respectively, where $V_{\mathrm{IL}}$ is the acceptable high level of the buffer-gate in TDC. After the capacitor is pre-charged, the voltage difference between node A and node B is ($V_{\mathrm{OUT}}-V_{\mathrm{IL}}$). At the moment the phase is switched, node A is connected to ground. Because the voltage difference between the two plates of a capacitor does not change suddenly, the voltage of node B is ($V_{\mathrm{IL}}-V_{\mathrm{OUT}}$). During phase ${\varphi }_2$, node B is charged by a constant current source I, which is supplied by a PMOS of a current mirror. Since $V_{\mathrm{IL}}$ is usually lower than half the supply voltage, the source-drain voltage of the PMOS is large enough and the PMOS operates in the saturation region. Under such a condition, the drain current is slightly affected by the source-drain voltage. Hence, the linearity of the voltage sensor is not greatly affected by the change of the voltage of node B. The charging current I is stable in the range of concern.

Figure 5. The circuit scheme of the voltage sensor.

When the voltage of node B rises to $V_{\mathrm{IL}}$, the voltage level turns to logic “1” and the TDC is triggered. During the process, the charge variation in $C_{\mathrm{C}}$ can be expressed as

$$\Delta Q_{\mathrm{C}}=I·\Delta t$$

(6)

where $\Delta t$ is the time interval of node B is charged from ($V_{\mathrm{IL}}-V_{\mathrm{OUT}}$) to $V_{\mathrm{IL}}$. Meanwhile, the voltage variation of node B is [$V_{\mathrm{IL}}$−($V_{\mathrm{IL}}$−$V_{\mathrm{OUT}}$)]. The relationship between $\Delta Q_{\mathrm{C}}$ and the voltage change during $\Delta t$ is

$$\Delta Q_{\mathrm{C}}=C_{\mathrm{C}}·\left[V_{\mathrm{IL}}-\left(V_{\mathrm{IL}}-V_{\mathrm{OUT}}\right)\right]$$

(7)

Combining Equations (6) and (7), $\Delta t$ can be expressed as

$$\Delta t=\frac{C_{\mathrm{C}}}{I}{V}_{\mathrm{OUT}}$$

(8)

Hence, the output voltage is converted to a time interval by varying the initial voltage of $C_{\mathrm{C}}$.

In the voltage sensor, a parasitic capacitance exists in the capacitor $C_{\mathrm{C}}$, which causes a slight change of about 20–30 fF in $C_{\mathrm{C}}$. In the proposed circuit, the charging capacitance is 250 fF, which is much larger than the parasitic capacitance. Because the resolution of the proposed 6-bit TDC-based voltage converter is about 25 mV, the circuit response is not modified by the slight fluctuation of $C_{\mathrm{C}}$.

3.2. Time-to-Digital Converter

The circuit scheme of the time-to-digital converter is shown in Figure 6. As an all digital circuits, TDC is implemented by logical synthesis. The input ports of the TDC are connected to the clock $\varphi$ and the output of the voltage sensor. In the delay line, the propagated time of each buffer is $t_{\mathrm{d}}$. Figure 7 shows the timing diagram of the TDC-based signal converter. At the beginning of phase ${\varphi }_2$, signal “1” is transmitted in the delay line. When the voltage sensor generates a positive edge, the D flip-flops are triggered, and ports ${\mathrm{D}}_{\mathrm{i}}$ (i = 1, 2, ⋯, n) output the voltage level of node ${\mathrm{P}}_{\mathrm{i}}$ (i = 1, 2, ⋯, n). The number of buffers transmitted by signal “1” is $N=\left[\Delta t/t_{\mathrm{d}}\right]$. According to Equation (8),

$$N=\left[\frac{C_{\mathrm{C}}}{I·t_{\mathrm{d}}}{V}_{\mathrm{OUT}}\right]$$

(9)

Figure 6. The circuit scheme of the time-to-digital converter.

Figure 7. The timing diagram of the TDC-based signal converter.

Using the voltage sensor and TDC, the transformation of $V_{\mathrm{OUT}}$ from analog to digital can be achieved.

3.3. Digital Controller

The delay line in TDC outputs a 64-bit thermometer-coded digital signal $V_{\mathrm{OUT},\mathrm{D}}$. The digital subtractor subtracts the temperature code from the reference voltage $V_{\mathrm{REF},\mathrm{D}}$ and outputs an error value e. Driven by the error value, the output of the digital PI controller at kth clock cycle can be expressed as

$$u\left(k\right)=K_{\mathrm{P}}e\left(k\right)+K_{\mathrm{I}}\sum _{j=0}^{k}e\left(j\right)$$

(10)

When there is a steady-state error, $V_{\mathrm{OUT},\mathrm{D}}$ is not equal to the $V_{\mathrm{REF},\mathrm{D}}$ and the output of digital subtractor is non-zero. Under such a condition, the accumulative component of Equation (10) causes the PI to output a variable value. The digital code $V_{\mathrm{OUT},\mathrm{D}}$ is forced to approach the $V_{\mathrm{REF},\mathrm{D}}$ until steady-state error is eliminated. When the circuit is stable, $V_{\mathrm{OUT},\mathrm{D}}$ is equal to the $V_{\mathrm{REF},\mathrm{D}}$ and the output of the digital subtractor is 0. Since the accumulative component of the digital PI controller no longer changes, a stable voltage is outputted continuously.

4. Simulation and Results

4.1. TDC-Based Signal Converter

The proposed fast response DLDO was realized in a 65-nm TSMC technology. It occupies an active area of 0.017 mm${}^2$ and the layout is shown in Figure 8. The current injection of the switches in the TDC-based voltage converter introduces the voltage errors to the output voltage of switches. To describe the effect, the voltage errors were measured and the results are shown in Figure 9. In the circuit, the charging capacitor is 250 fF and the charging current I is 120 $\mathsf{\mu }$A. According to the results, the current injection causes the positive errors at node A and node B under different $V_{\mathrm{OUT}}$ conditions. The resolution of the proposed TDC-based voltage converter is about 25 mV, which is larger than the maximum voltage error. Hence, the current injection will not affect the accuracy of the proposed circuit. Figure 10 shows the comparison of linearity between the conventional TDC and the proposed TDC. The test points are fitted into a quadratic function. According to the fitting results, the coefficients of the quadratic term of the conventional TDC and the proposed TDC are −47.1 and $-2.8\times {10}^{-14}$, respectively. Relative to the conventional TDC, the performance of linearity is improved in the proposed design.

Figure 8. The layout of the proposed fast response DLDO.

Figure 9. The voltage error caused by the current inject of switches.

Figure 10. The comparison of linearity for: (a) conventional TDC; and (b) proposed TDC.

4.2. Proposed DLDO

To describe the transient response speed of the proposed circuit, the settling time $T_{\mathrm{S}}$ with variable load was simulated. The settling time is defined as the time of the output voltage recovers to 90% of the droop voltage. As shown in Figure 11, the proposed DLDO reduces the settling time under each condition. The settling time is decreased to only 17.1% of the baseline design of DLDO (from 147.8 ns to 25.2 ns) on average. In other words, the proposed circuit improves the response speed by about six times. Under the variations of sampling frequency and load current, the settling time was evaluated as well. In Figure 12, the increasing sampling frequency results in a shorter $T_{\mathrm{S}}$. The settling time when $f_{\mathrm{S}}$ = 100 MHz is about half that of $f_{\mathrm{S}}$ = 50 MHz. Compared with the heavy load condition, settling time is shorter in the light load condition under each frequency.

Figure 11. The settling time when: (a) load resistance is 11 $\Omega$; and (b) load capacitance is 500 pF.

Figure 12. The settling time under the variations of sampling frequency and load current.

Figure 13 shows the measured transient responses of the baseline DLDO and the proposed DLDO with a load step of 80 mA. With $V_{\mathrm{IN}}$ = 1 V, $V_{\mathrm{OUT}}$ = 0.85 V (step up) or $V_{\mathrm{OUT}}$ = 0.65 V (step down), $f_{\mathrm{S}}$ = 100 MHz and $C_{\mathrm{L}}$ = 500 pF, we measured a 25 ns (step up) or 64 ns (step down) settling time. Compared with the baseline case, the proposed DLDO shows a significantly faster settling time. The output voltage is measured for a target voltage of from 0.95 to 0.65 V with $V_{\mathrm{IN}}$ ranging from 0.7 to 1.1 V. As shown in Figure 14, the effect of the line voltage on the output voltage is slight. A line regulation of 15 mV/V is achieved. The output voltage with a load current range from 55 to 85 mA is measured. As shown in Figure 15, the circuit regulates the output voltage from 0.95 to 0.65 V, and a load regulation of <0.8 mV/mA is achieved. A performance comparison with published DLDO is given in Table 2, which includes both the ALDO and DLDO. In comparison to those prior designs in Table 2, this paper achieves the shortest response time, the best figure of merit (FOM) of speed [21], and competitive current efficiency.

Figure 13. The measured transient responses of the baseline DLDO and the proposed DLDO for a load: step up (a,b); and step down (c,d).

Figure 14. The output voltage under the variations of line voltage.

Figure 15. The output voltage under the variations of load current.

Table 2. Comparison with published LDO designs.

Paper	2015 [22]	2018 [23]	2019 [24]	2018 [25]	This Work
Type	Analog	Digital	Analog	Digital	Digital
Process	180 nm	65 nm	55 nm	65 nm	65 nm
Active area [mm${}^2$]	0.021	NA	0.042	0.012	0.017
$V_{\mathrm{IN}}$ [V]	1.3–1.8	0.8–1	<0.8	0.5–1	0.7–1.1
$V_{\mathrm{OUT}}$ [V]	1.2	0.75–0.95	0.6	0.35–0.95	0.65–1.05
Quiescent $I_{\mathrm{Q}}$ [$\mathsf{\mu }$A]	10	24	0.016	45.2	495
$I_{\mathrm{MAX}}$ [mA]	25	13	10	2.8	120
Peak current efficiency $\eta$ [%]	99.9	99.8	99.8	98.4	99.6
Line regulation [mV/V]	0.5	NA	0.5	NA	15
Load regulation [mV/mA]	0.14	NA	1.05	NA	0.6
Load capacitor $C_{\mathrm{L}}$ [nF]	4700	0.2	1000	0.1	0.5
Max voltage droop [mV] @ Load step	2 @ 25 mA	100 @ 6 mA	70 @ 10 mA	46 @ 1.76 mA	371 @ 80 mA
Response time $T_{\mathrm{R}}$ * [ns]	376	3.3	7000	2.63	2.1
FOM ** [ps]	150	13.3	11.4	67.1	8.7

* $T_{\mathrm{R}}={\mathrm{C}}_{\mathrm{L}}\ast {\mathrm{V}}_{\mathrm{droop}}/{\mathrm{I}}_{\mathrm{MAX}}$; ** FOM = $T_{\mathrm{R}}\ast {\mathrm{I}}_{\mathrm{Q}}$/$I_{\mathrm{MAX}}$.

5. Conclusions

This paper presents a fast response DLDO with a TDC-based signal converter for decreasing the settling time. The voltage sensor and TDC convert the output voltage from analog to digital. The digital controller provides a multi-bit regulation and improves transient response performance. The simulation results show that the proposed fast response DLDO can decrease the settling time to 17.1% of the baseline design of DLDO on average, and a FOM of 8.7 ps is achieved.