Bulk Bias as an Analog Single-Event Transient Mitigation Technique with Negligible Penalty

Round 1

Reviewer 1 Report

My review comments are adequately addressed. 

Reviewer 2 Report

After the first revision the manuscript looks appropriate for publication. I would like to thank all the authors for addressing all my concerns. 

The introduction section improved significantly after first revision. Also, I liked the fact the author compared their results with other authors work. 

Overall, I am recommending this manuscript for acceptance in present form.

Reviewer 3 Report

Thank you for taking into account all my remarks.

This manuscript is a resubmission of an earlier submission. The following is a list of the peer review reports and author responses from that submission.

Round 1

Reviewer 1 Report

Very interesting paper and well written. A few comments below:

1. From the proposed paper: “Single-event hardened analog and mixed-signal systems design are more challenging compared with digital systems because of the continuous characteristic of analog signals rather than “0” or “1” values of digital signals.”

However, analog circuits can recover (assuming non-destructive damage) after a SET with a certain time constant. In contrast, in many digital circuits (i.e. flash memories), if the bits are flipped the information is lost except if there redundancy which is common in such circuits.

 

2. In space environment we have both SET effects and TID effects. For paper completeness, could you commend if this technique will influence the TID performance and why?

In general I believe that the paper is presenting a useful work and results for the community of radiation hardened IC circuits.

Reviewer 2 Report

The abstract and introduction section is well written.

However, the quality of the manuscript submitted is not appropriate for a journal paper. If I was one of the authors, then I would have relevant works as my second section. Later, I would have compared the results obtained by the proposed technique with other published articles.

Also, I feel after going through the article it feels to me that authors just ran some simulation using TCAD and presented the plots obtained from them. I wish they have included some theoretical concepts and equations with this article.

All the circuit pictures are poorly made. It is not shown in the pictures, which transistors are BTS and others who are not. Also, I didn't find the reason why only the BTS technique applied to PMOS and not to NMOS also.

Reviewer 3 Report

General, major concerns:
1. None of the references you're citing as "novel" techniques use this statement in the paper's title. It is not justified to call your studies this way. Please change the title to:
"PMOS bulk bias as a single-event transient mitigation technique with negligible penalty"
or similar. It suits the paper's content better.

2. In my opinion, It's not fully fair to simulate such circuit partially. Why not simulate the full stack of these 3 transistors? People anyway very often use shorting the bulk bias of PMOS to their sources (as stated in line 69) so it's not a new technique. It's rather a qualitative study of its impact on radiation immunity.

3. Please elaborate more on how bulk bias modification affects the pulse length of the SET event. This is crucial for understanding the content and I think it needs to be explained briefly.

Other remarks:

Ref. 2 is relatively old compared to the current CMOS processes and simulation techniques.
Ref. 4 is related to SET is digital CMOS while it is reference when talking about analog circuits.
27 - 28 - rephrase. Statement "0 or 1" values is too basic.
Refs 5-7 are relatively old: 2005, 2008, 2013 and 2 of them refer to switched capacitor circuits. Please do a thorough state of the art study referred to the topic and circuit type you're presenting.

73: rephrase.
86-87 - this was partially stated before, please move these information to the previous paragraphs.
90 - why track length is 10um only? Is it a depth of a well?
106 - redundant information, again 30 (...).
Fig. 3 - again 30 (...)
112 - again 30 (...)
166 - I disagree, the effect is clearly visible so it cannot be called as effective SET mitigation.
Fig. 3, Fig. 4 - please change Y label to something more meaningful like "DUT output voltage" or "output voltage".
122 - "great SET mitigation effect" => please quantify, as in the next sentence, not use 'great', which is meaningless
125-127 - elaborate more of 100mV threshold selection, it is not clear why such an arbitrary value is used and taken from ref. 1 which is dated down to 2001.
131-132 - It's not the amplitude which is constant, it is the high level. I think that this paragraph should be earlier, just after Fig. 3, or close to.
133 - and this is probably the key point of these studies.
Table 2 - what about AC performance? Supply voltage - pointless to state it here. What DC (20dB) means? I think you could remove the table and state the important parameters in text.
172-174 - I think that miller compensation is well known and it is not necessary to mention it here since it's not within the scope of the paper. The same with statements in 175-180. Just state the GBW and phase margin values.
197 - again 30 (...). The test methodology was stated in the beginning.
199 - you haven't introduced the shortcut RHBD which might not be familiar to some of the journal's readers
203 - it's not "extremely effective", sorry. Avoid using such statements.