A 24-GHz RF Transmitter in 65-nm CMOS for In-Cabin Radar Applications
, Hyunwon Moon 2,* and Ilku Nam 1,*
Round 1
Reviewer 1 Report
This paper presents a 24GHz RF Tx IC implemented in 65nm CMOS process. The reviewer would like to suggest a few revision points for this paper.
- Use the different notations for R, C and parasitic line inductance of the poly-phase filter. The same notations such as R1, C1 and L1 have already been used for the LO I/O buffers in Figure 5. Revise the equations of (6) and (7) also correspondingly.
- The authors have commented in line 166 that the lengths of the connecting lines should be as similar as possible ~. Show the layout drawing plan of the poly-phase filter as an additional figure to help the understanding of the readers.
- In table 1, this work shows better LO leakage performance than others. Explain how you could achieve this good performance in detail within this paper.
Author Response
1. The same notations such as R1, C1 and L1 have already been used for the LO I/O buffers in Figure 5. Revise the equations of (6) and (7) also correspondingly.
Answer) Thank you for your comment.
We modified Fig. 5, Fig.6 and the equations.
2. The authors have commented in line 166 that the lengths of the connecting lines should be as similar as possible ~. Show the layout drawing plan of the poly-phase filter as an additional figure to help the understanding of the readers.
Answer) Thank you for your comment.
We added the layout drawing plan of the poly-phase filter.
Please refer to Fig. 7.
3. In table 1, this work shows better LO leakage performance than others. Explain how you could achieve this good performance in detail within this paper.
Answer) Thank you for your comment.
The LO leakage performance was achieved by symmetric mixer layout and good balanced differential LO signals, which were verified by post-layout simulations and full EM(electro-magnetic) simulations including all passive components and line connections.
We added it to this manuscript. Please refer to page 8.
Reviewer 2 Report
The paper is well written, it presents clearly the aim of work done. However I have some remarks which would improve the paper:
pg.5 line 137 – can you add some simulations of conventional and proposed transconductor to prove 4 dB OIP3 improvement?
pg.5 line 140 – can you comment biases, are they central or distributed? Is there some additional circuit for crosstalk minimization?
pg.5 line 142 – can you comment the parasitic Lg1, Ls1 and Ls2 – were they estimated, calculated? Does they influence somehow the performance?
pg.5 line 152 – there are L due to connections. Is there some crosstalk between the channels?
pg6. line 169 – you estimate the L1-L4 to be around 20pH – how much they vary in fact, is there some optical length depending on central frequency? It seems L2 has greater influence or it doesn’t matter? Is equal L only solution or is there some other guide?
pg6. line 182 – can you comment more the operation of PA, maybe some simulations? Expected amplification?
pg.7 line 187 – can you comment the power consumption of each block?
Some general remarks:
Figures of schematic are a bit blurry. Also the layout is not clear and it doesn’t have proper lighting. You have two supply voltages. Is there a reason why not using only one supply voltage (core and power elements?). Some spectral diagrams (LO and RF) will nice to have.
Author Response
pg.5 line 137 – can you add some simulations of conventional and proposed transconductor to prove 4 dB OIP3 improvement?
Answer) Thank you for your comment.
As shown in Fig. 4, when the width of PMOS Mp1 with a channel length of 65nm is 0 um ((i.e., the PMOS is not used), the simulated OIP3 performance of the up-conversion mixer with a conventional NMOS transconductor is 15.8 dBm. When the width of PMOS Mp1 with a channel length of 65nm is 72 um, the simulated OIP3 performance of the up-conversion mixer with proposed transconductor is 19.6 dBm.
pg.5 line 140 – can you comment biases, are they central or distributed? Is there some additional circuit for crosstalk minimization?
Answer) There is a current generation circuit using PTAT and bandgap circuits. The bias currents from the current generation circuit are distributed for transistors’ biasing. Current mirrors are placed near core transistors. The capacitors are used in the current mirrors to reduce crosstalk and noise.
pg.5 line 142 – can you comment the parasitic Lg1, Ls1 and Ls2 – were they estimated, calculated? Does they influence somehow the performance?
Answer) Lg1, Ls1, and Ls2 are not parasitic components but lumped elements, which were used for impedance matching.
pg.5 line 152 – there are L due to connections. Is there some crosstalk between the channels?
Answer) Through EM(electromagnetic) simulation and post-layout simulation, it was confirmed that there was almost no crosstalk between the channels.
pg6. line 169 – you estimate the L1-L4 to be around 20pH – how much they vary in fact, is there some optical length depending on central frequency? It seems L2 has greater influence or it doesn’t matter? Is equal L only solution or is there some other guide?
Answer) The inductances (L1~L4) by routing lines were extracted through EM simulation. It seems that the parasitic inductance L2 does not have much effect in the simulation. There may be other design guidelines, but since the length of the routing line of the poly-phase filter is not long, the parasitic inductance is dominant than other parasitic components, so we presented the design guideline from the parasitic line inductance analysis by the length of the line.
pg6. line 182 – can you comment more the operation of PA, maybe some simulations? Expected amplification?
Answer) The simulated OP1dB and OIP3 are 9.7 dBm and 17 dBm, respectively. The simulated peak PAE is 15 %.
pg.7 line 187 – can you comment the power consumption of each block?
Answer) The current consumption of an I/Q up-conversion mixer and an I/Q LO generator is 8.6 mA and 11.4 mA at a 1.2-V supply voltage, respectively. The current consumption of the power amplifier is 60 mA at a 2.1-V supply voltage.
Some general remarks:
Figures of schematic are a bit blurry. Also the layout is not clear and it doesn’t have proper lighting. You have two supply voltages. Is there a reason why not using only one supply voltage (core and power elements?). Some spectral diagrams (LO and RF) will nice to have.
Answer) Thank you for your comment. We improved the resolution of figures. We improved the resolution of the picture. 2.1V was used to obtain high linearity of the power-stage amplifier.
Reviewer 3 Report
Overall, a polyphase filter for differential to IQ four phase conversion, an I/Q mixer and a PA is presented. Below are some comments and questions to the author:
- For PA part, can author explain about C3, C4, C7 and C8 in their PA schematic? What is the function of those capacitors and how those are optimized? Also the linearity and PAE is never discussed for PA. Is the compression due to PA or mixer?
- For mixer part, only PMOS profile is provided. Can author provide the NMOS profile also and plot composite curve of gm''? Is the linearity really improved by gm'' or simply by matching of NMOS gm and PMOS gm? Please show the DC current also since DC current can also be traded for linearity.
- For LO part, is the magnitude mismatch in Fig. 7 correct? If it is as high as 0.25 dB, the image signal, by hand calculation, is already - 37 dBc. Or is it because the mixer is normalizing the signal and reduces the final magnitude imbalance? If so, a gain curve for the mixer should be provided and corresponding explanation should be added.
- Although the LO leakage and image rejection performance achieved in this design is good, the bandwidth is too narrow. Can author discuss the cause of the limited bandwidth and propose some ways to improve the bandwidth? e.g. tunable polyphase filter？
Author Response
1. For PA part, can author explain about C3, C4, C7 and C8 in their PA schematic? What is the function of those capacitors and how those are optimized? Also the linearity and PAE is never discussed for PA. Is the compression due to PA or mixer?
Answer) Thank you for your comment.
C3, C4, C7, C8 are used for the cascode transistors’ gate to be ac grounded.
The simulated OP1dB and OIP3 are 9.7 dBm and 17 dBm, respectively. The simulated peak PAE is 15 %. The compression of the transmitter is due to PA in the simulation. The measured OP1dB decreased by 1dB.
2. For mixer part, only PMOS profile is provided. Can author provide the NMOS profile also and plot composite curve of gm''? Is the linearity really improved by gm'' or simply by matching of NMOS gm and PMOS gm? Please show the DC current also since DC current can also be traded for linearity.
Answer)
Fig. 3 shows the composite curve of gm’’ of the inverter transconductor composed of nmos and pmos. The gm’’ of nmos is the value when the width of pmos is 0 um (i.e., the PMOS is not used). If the value of the composite gm’’ is minimized, the linearity can be improved.
We added the dc current consumption of the I/Q up-conversion mixer in Fig. 4 versus the width of PMOS.
3. For LO part, is the magnitude mismatch in Fig. 7 correct? If it is as high as 0.25 dB, the image signal, by hand calculation, is already - 37 dBc. Or is it because the mixer is normalizing the signal and reduces the final magnitude imbalance? If so, a gain curve for the mixer should be provided and corresponding explanation should be added.
Answer) Thank you for your valuable comment. In general, a mixer circuit is designed to operate in a region which is insensitive to the amplitude variations of the LO signals. Therefore, although the magnitude mismatch between the I- and Q-paths of the proposed poly-phase filter-based I/Q LO generation circuits is less than 0.25 dB, the simulated gain of the designed I- and Q-paths of the up-conversion mixer is the same.
4. Although the LO leakage and image rejection performance achieved in this design is good, the bandwidth is too narrow. Can author discuss the cause of the limited bandwidth and propose some ways to improve the bandwidth? e.g. tunable polyphase filter？
Answer) Thank you for your valuable comment. Because the bandwidth of our target system is narrow from 24 GHz to 24.5 GHz, we had not considered the ways to improve the bandwidth. As you mentioned, the tunable poly-phase filter or more than three-stage poly-phase filter could be candidate to expand the bandwidth.
Round 2
Reviewer 1 Report
My comments were addressed appropriately.
Reviewer 3 Report
The questions have been answered. No further comments.
