Design and Development of BTI Model and 3D InGaAs HEMT-Based SRAM for Reliable and Secure Internet of Things Application

Abstract

It is broadly accepted that the silicon-based CMOS has touched its scaling limits and alternative substrate materials are needed for future technology nodes. An Indium-Gallium-Arsenide ($InGaAs$)-based device is well situated for further technology nodes. This material also has better mobility of the electrons and holes for the high performance and real-time system design. The improved mobility helps to increase the operating frequency of the device which is useful for Internet of Things (IoT) applications. However, $InGaAs$-based High Electron Mobility Transistors (HEMT) limits the reliability of the device due to the presence of dangling bonds at the channel–gate insulator interfaces. Weak dangling-bonds get broken under electric stress, and positive hydrogen atoms are trapped into the oxide. This charge trapping depends on the material parameters and device geometry. In this paper, the existing Bias-Temperature-Instability (BTI) model is modified based on the material parameters and device geometry. Charge trapping and annealing constants are the most critical BTI model parameters that are modeled and evaluated based on different HEMT material parameters. The proposed model was compared to experimental and TCAD simulation results. The proposed model has been used for lifetime prediction of the InGaAs HEMT-based Static Random-Access Memory (SRAM) cell because it is used to store and process the information in the IoT applications.

1. Introduction

Wireless sensor networks (WSNs) have been extensively used as devices for information collection and decision making. These capabilities have expanded the scope of applications of WSNs in many fields including Internet of Things (IoT), healthcare, search and rescue where sensor nodes are deployed at remote locations and under extreme conditions [1]. Power-consumption is one of the important challenges that restrict the efficiency of WSN since sensor nodes are battery operated. Hence, life time prediction of the VLSI chips used for WSN circuits has become a necessity. Speed is another design requirement for WSN circuits which are required to operate at high frequencies. Since MOSFET no longer supports high-frequency operation, High Electron Mobility Transistors (HEMT) provide an alternative solution to achieve high-performance circuit design for WSNs [2]. HEMT has been used to design satellite receivers and sensor nodes [3,4]. Some compound semiconductor materials are used to increase the operating frequency of HEMT such as Gallium-Nitride ($GaN$) and Indium-Gallium-Arsenide ($InGaAs$). In $InGaAs$-based HEMT, the indium material provides extra strain to increase the mobility of electrons and holes. These semiconductor devices use high-k dielectric materials in order to establish strong insulation of the gate terminal. This helps to reduce the gate leakage current for the low power circuit design. Unlike the conventional bulk-based MOSFET, the high-k dielectric materials in HEMT establish a weak interafce with the bulk material. Therefore, more dangling bonds are generated in HEMT than MOSFET in order to strengthen the contact at the bulk dielectric interface. ($Si{O}_2/Si$) [5].

When HEMT devices are operated under electrical stress, the dangling-bonds get broken, and positive hydrogen atoms get trapped inside the gate-insulator, which increases the threshold voltage of the HEMT. Consequently, the HEMT threshold voltage increases which causes a decrease in the operating frequency. Such effects are further escalated at higher temperatures due to the Bias-Temperature-Instability (BTI) which is one of the main reliability degradation sources in HEMT. Other reliability degradation sources include Time-Dependent Dielectric Breakdown (TDDB) and Hot Carrier Injection (HCI) [6]. Therefore, an efficient HEMT-based circuit design should carefully consider the effects of those sources. Due to the complexity of developing a physical VLSI chip, CAD tools are used to model and simulate the behavior of VLSI circuits. Models should incorporate all the reliability degradation sources in order to obtain an accurate simulation of the VLSI circuit under their effects. The Reaction–Diffusion (RD) model [7] can be used to model the increase in the threshold voltage of the HEMT. The RD model is based on using electrochemical reactions and activation energies to represent the interface state [7]. Reliability models should also account for the various device parameters and geometrical properties and therefore they should be modified accordingly based on the device under test.

The primary components of an IoT system are a data converter, a transmitter, and a receiver [1]. These components can be designed using logic circuits and storing elements such as Static Random-Access Memory (SRAM) [8]. Hence, the proposed reliability model for HEMT can be tested on SRAM. SRAM is considered to be the fundamental storing element occupying more than 80% of the on-chip area of the processor. Since HEMT is used for high-frequency SRAM design, the prediction of its lifetime becomes necessary [9]. In this paper, an $InGaAs$-based SRAM is designed and analyzed to evaluate its stability under BTI stress. Based on this analysis, a BTI model for SRAM lifetime prediction has been proposed, and further, it is used for an SRAM circuit simulation using SystemVerilog-based modeling and the HSPICE EDA tool. The highlights of the proposed works are as follows:

• Design and simulation of the $InGaAs$-based HEMT;
• Calibration of simulation models and HEMT with experimental data;
• Proposed a PBTI/NBTI model for HEMT;
• Proposed model is modified according to the material parameters;
• Use of proposed model for 6T SRAM cell design.

The rest of the paper is organized as follows: In Section 2, the state-of-the-art BTI models are discussed. In Section 3, the proposed $InGaAs$-based HEMT design is discussed. In Section 4, simulation setup, model calibration with experimental results, and design are proposed. In Section 5, the 6T SRAM cell is briefly described and simulation results are discussed. In Section 6, a spice equivalent BTI model for the $InGaAs$-based HEMT is discussed. In Section 7, the simulation results of the proposed model are discussed. Section 8 concludes the work.

2. State-Of-The-Art BTI Models

It was already mentioned in a previous study, that the trapping of the charge carrier in the gate insulator due to the NBTI/PBTI can be defined by the RD-model [7]. Due to the unclear nature of NBTI/PBTI, more realistic RD-models that better incorporate the effects of those sources have been proposed. Kufluoglu et al. [10] has proposed a model where the transistor structure and scaling-based compact NBTI model were included. It shows similar characteristics with the numerical simulation results despite the superiority of this model to all other kinds of transistor structures, the model parameters were not experimentally determined. Furthermore, the electron/hole generation and annealing parameters were used but the model did not include the device structure and experimental data. Another RD-based model has been proposed by Islam et al. [11,12], which showed the passivation/depassivation effects of the Si-H bond by using the initial charge density, electron/hole generation constant, and annealing constant. This model, however, did not show the geometrical effect on NBTI/PBTI. For circuit simulation purposes, this model was modified and applied for 65 nm CMOS technology [13]. When BTI is induced, the trap charge density was found to be dependent on the diffusion constant. Therefore, the RD model is further modified to include the diffusion length. This model used the default values for the hole/electron generation and annealing constant [14]. The same model was further modified for silicon body tied FinFET [15].

Some statistical reliability models were proposed for FinFET and SRAM cells and used to investigate the NBTI effects [16]. An NBTI framework for 20 nm node devices was presented by Mishra et al. [17]. The stress generated by BTI is found to be more significant than PBTI stress. NBTI reduces the inversion charges and degrades the electron and hole mobility. It is due to the Coulomb scattering and depends on the applied gate voltage, temperature, and stress time [16,17]. In these works, they also assumed that the generated interface state is designing a substrate gate interface bond with their energy distribution.

In this work, we have modified the existing model given by Kufluoglu et al. [10] and proposed a new geometry-based BTI model device for N-type $InGaAs$ HEMT (FinFET). The electron–hole generation constant and different parameter values are calculated for the $InGaAs-A{l}_2{O}_3$ interface. Due to the model dependency on the hydrogen diffusion consistent, this constant has been calculated for the $InGaAs-A{l}_2{O}_3$ interface. Further, the effectiveness of the proposed model has been tested with the TCAD simulator, and results are verified with state-of-the-art experimental results.

3. Proposed InGaAs HEMT

Figure 1 shows the architecture of the $InGaAs$-based HEMT [18]. The real physical device operation was simulated using a process equivalent TCAD simulation [19]. To design $I{n}_{0.53}G{a}_{0.47}As-A{l}_2{O}_3$ interface, $InP$ was deposited over the insulator, and over it, an $InGaAs$ layer was deposited for device formation. Then, a $A{l}_2{O}_3$ gate insulator layer was deposited at the top. Tin material was deposited over the $InGaAs$ layer which formed the gate layer. After the device design, a simulation-based device characterization was done using the $Sdevice$ TCAD simulator [19]. The values used for $R_{ON}$ and $I_{OFF}$ are 180 Ω/μm and 100 nA/μm, respectively, are obtained at $V_{DS}$ = 0.5 V and calibrated as per the experimental data [20]. Other important parameters are shown in

Table 1. Device parameters for Indium-Gallium-Arsenide ($InGaAs$)-based High Electron Mobility Transistors (HEMT) as per the experimental results [20].

Operating voltage $V_{DD}$ [V]	0.5
Operating overdrive =2/3 * $V_{DD}$ [V]	0.33
EOT [nm]	1.8
Operating $E_{ox}$ [mV/cm]	2
$H_{fin}$ [nm]	35
$W_{fin}$ [nm]	10
$L_{Gate}$ [nm]	30
PBTI time exponent (n)	0.1
$\mathsf{\Delta }{V}_{th}(t=10Y)$$@Op.E_{ox}$ [mV]	118
$\mathsf{\Delta }{N}_{eff}(t=1s)$$@Op.E_{ox}$ [cm−2]	2 × 1011

. Figure 2 shows the current–voltage characteristics of a device with $W_{fin}$ = 22 nm, and $L_g$ = 30 nm. Figure 2 and Table 1 both show the calibration results with experimental data [20].

To understand the BTI effect in the proposed device, we need to understand the bulk–oxide and oxide–metal interface properties. The properties of this interface depend on the gate oxide materials such as $Si{O}_2$, $Hf{O}_2$, $L{a}_2{O}_3$, $A{l}_2{O}_3$, and $TaSi{O}_x$. The unbounded states, the band-decomposed charge density corresponding to the bandgap pinning energy interval are shown in a 3D plot by Kim et al. [21]. This 3D plot can be used to determine the exact location and the number of dangling bonds at the $InGaAs$ and $A{l}_2{O}_3$ insulator interface. The unbounded states are localized at the existing coordinated Aluminum ($Al$) atoms which have bonded with two Oxygen ($O^{\prime }s$) atoms and one Hydrogen (H) atom. In amorphous bulk, $A{l}_2{O}_3$ and $Al$ primarily have four bonds with O, as shown in Figure 3. These dangling bonds change the electrical properties of a device and increase the density of the existing interface trapped charges ($N_{it}$).

Active depletion charge density is used to understand the interface properties which gives the device reliability information. The active interface charge in the depletion region can be measured using a quasi-static and high-frequency capacitance–voltage model. Figure 4 shows bi-directional capacitance–voltage (CV) curves for different gate insulator interfaces for $InGaAs$-based HEMT [22]. These data are taken from published experimental work [22]. Figure 4 shows the initial charge density for $L{a}_2{O}_3$-based gate insulator is lower because the trivalent oxides $A{l}_2{O}_3$ and $L{a}_2{O}_3$ have fewer dangling bonds. Having fewer dangling bonds reduces the interracial state. However, $L{a}_2{O}_3$ is very unstable material [22], hence we are using $A{l}_2{O}_3$ as a gate insulator material in the proposed $InGaAs$-based HEMT. The next element of the proposed work is an SRAM cell for the IoT applications, which is explained in the next section.

4. BTI Effects on 6T SRAM Cell

Figure 5 shows a 6T SRAM cell, which is designed by the $InGaAs$-based HEMT. It can also be called FinFET for circuit applications. The design parameters (Fin Number (NF)) of the proposed SRAM transistors are as follows; driver(PD) NF = 4, Access(A) NF = 2, and Pull-Up (PU) NF = 4. Data retention stability under standby condition is analyzed by Static Noise Margin (SNM), and read stability is analyzed by Read Noise Margin (RNM). Synopsys TCAD-mixed-mode simulator has been used for the $InGaAS$ device-based circuit simulation. The 6T SRAM cell was analyzed in both standby and read mode operations using the two-stage NBTI and degradation models in [19]. The trap charge density under three-year stress in standby mode operation is shown in Figure 6. The figure shows a single driver transistor for the two-stage NBTI model because symmetric inverters design the 6T SRAM cell and NBTI affects the PMOS transistors only. In the degradation model, the effect of BTI is plotted for both NMOS and PMOS [19,23]. TCAD simulation results show a significant change in the trap charge density.

The SNM butterfly curves of the proposed SRAM cell is shown in Figure 7a. We take a standard Gaussian doping and initial $N_{IT}$ = $con=4\times {10}^{12}$. The $N_{IT}$ increases with three-year stress. A similar result is also shown for the RNM (as shown in Figure 7b). These variations can not be considered under the most of the available spice–circuit simulators. Hence, most of the circuit simulators can not predict the reliability of the chip (in terms of the lifetime). The MOSERA model bases reliability simulation can be performed in the H-SPICE simulator, but it uses a fundamental power–law model. Hence, the proposed BTI model, which is developed especially for $InGaAs$-based FinFET, can be used in circuit simulation.

5. Proposed BTI Model for HEMT

HEMT is a three-dimensional (3D) device with three trapping regions; two of them are from side walls and one from the top. Top and side walls show one-dimensional (1D) trap-induced BTI, whereas the corners show two-dimensional (2D) trap-induced BTI, as shown in Figure 8.

We have already discussed that the RD model is used for the electric’s stress-induced trapping. The RD model follows the time-dependent power–law model [10]. In the RD model, the shift in NMOS parameters induced by PBTI is represented by the breaking of the hydrogen passivated substrate material bonds in the $InGaAs--A{l}_2{O}_3$ interface. The total charge trap density at $InGaAs--A{l}_2{O}_3$ interface due to BTI (PBTI and NBTI) is given by [10]:

$$\begin{array}{c}\hfill \frac{d{N}_{IT}}{dt}=k_f\left[N_0-N_{IT}\right]-k_r{N}_{IT}{N}_H(x=0,t)\end{array}$$

(1)

$$\begin{array}{c}\hfill \frac{d{N}_{IT}}{dt}=D\frac{d{N}_H(x,t)}{dx}{|}_{x=0}+\frac{\delta }{2}\frac{N_H(x,t)}{dt}\end{array}$$

(2)

where $N_0$ is the initial trap charge density and $N_{IT}$ shows the total interface charge due to the BTI in the $InGaAs--A{l}_2{O}_3$ interface. $N_{IT}$ depends on the rate at which H atoms are generated. Therefore, $k_f$ is the H generation rate and $k_r$ is the annealing rate. This parameter is used in the recovery phase. Some time $N_{IT}$ may approach $N_0$ because the diffusion process is slower than ionization and annealing [13]. Annealing is responsible for the removal of hydrogen from the $InGaAs-A{l}_2{O}_3$ interface. The diffusion process can also be considered to be taking place in the quasi-steady-state condition of this reaction. Therefore, $d{N}_{IT}/dt\sim 0$ Equation (1) may be simplified as:

$$\begin{array}{c}\hfill \frac{k_f(N_0-N_{IT})}{k_r}=N_H^0{N}_{IT}\end{array}$$

(3)

Using this relation in Equation (2), the total trap charge density can be modeled by:

$$\begin{array}{c}\hfill \frac{d{N}_{IT}}{dt}=D_H\frac{N_H^0}{\sqrt{D_{H}t}}=\sqrt{\frac{D_H}{t}}\frac{k_f}{k_r}\left(\frac{N_0-N_H}{N_{IT}}\right)\end{array}$$

(4)

Equation (1) shows that the trap charge density increases with the net reaction. Diffusion in FinFET is a process that happens in 2D at the corners and in 1D at the top and sidewalls. Hence, Equation (1) cannot be used to describe this process. For a more realistic representation, diffusion in the 1D and 2D are explained first. Assuming that H is one interface yields to the equation $N_{IT}\left(t\right)=\int N_H(r,t)d^{3}r$. It is previously mentioned that the rate at which H atoms are released is much greater than the diffusion rate. The hydrogen profile represented by ${\left(D_{H}t\right)}^{0.5}$ is shown on the left side of Figure 8b. Therefore, the 1D diffusion of hydrogen on a plane surface in the x direction is derived as:

$$\begin{array}{c}\hfill N_{IT}^{1D}\left(t\right)={\int }_0^{\sqrt{D_H}t}{N}_H^0\left(1-\frac{x}{\sqrt{D_{H}t}}\right)dx\end{array}$$

(5)

by putting values from Equation (3) into Equation (5), we obtain the solution:

$$\begin{array}{c}\hfill N_{IT}^{1D}\left(t\right)=\sqrt{\frac{k_f{N}_0}{2k_r}}{\left(D_{H}t\right)}^{0.25}\end{array}$$

(6)

Further, The hydrogen diffusion at the corners is a 2D process, as shown in Figure 8. There, the corresponding hydrogen diffusion profile is shown on the right in Figure 8b, which is circular and makes only a 1/4 circles at each corner, which is obtained by the circumference of the circle [10].

$$\begin{array}{c}\hfill N_{IT}^{2D}\left(t\right)=\frac{1}{4}{\int }_0^{\sqrt{D_H}t}{N}_H^0\left(1-\frac{r}{\sqrt{D_{H}t}}\right)2\pi rdr\end{array}$$

(7)

where r is the radius of the circle which is equivalent to the thickness of the oxide. Now putting the values from Equation (3) into Equation (7)

$$\begin{array}{c}\hfill N_{IT}^{2D}\left(t\right)=\sqrt{\frac{\pi k_f{N}_0}{12r{k}_r}}{\left(D_{H}t\right)}^{0.5}\end{array}$$

(8)

Similarly, the above explanation can be used to estimate the diffusion of hydrogen on a 2D surface. In the prescribed structure, the side and top walls show 1D diffusion, whereas the two corners show the 2D diffusion interface, as shown in Figure 8a,b. Hence, the interface state density generated by BTI is given by:

$$\begin{array}{cc}\hfill N_{I{T}_{stress}}& =\left[2{\int }_0^{\sqrt{D_{H}t}}{N}_H^0(1-\frac{x}{\sqrt{D_{H}t}})\right]dx\hfill \\ \hfill & +{\int }_0^{\sqrt{D_{H}t}}{N}_H^0(1-\frac{y}{\sqrt{D_{H}t}})dy\hfill \\ \hfill & +\frac{2}{4}{\int }_0^{\sqrt{D_{H}t}}{N}_H^0(1-\frac{r}{\sqrt{D_{H}t}})2\pi rdr\hfill \end{array}$$

(9)

By substituting $r=t_{ox}\sim EOT$ and W into Equation (1), we can write:

$$\begin{array}{c}\hfill N_{I{T}_{stress}}\left(t\right)=\sqrt{\frac{k_f{N}_0}{2k_r}}{\left[{\left(D_{H}t\right)}^{\frac{1}{2}}+\frac{\pi \left(D_{H}t\right)}{9W{t}_{ox}}\right]}^{\frac{1}{6}}\end{array}$$

(10)

where, $k_f$ and $k_r$ are the rates of generation of $H_2$ i.e., electron/hole and $k_r$ is the annealing rate. The shift of the trap threshold is described by:

$$\begin{array}{c}\hfill V_{th}=\alpha \frac{q}{C_{ox}}{N}_{I{T}_{stress}}\end{array}$$

(11)

where $\alpha$ is a multiplication factor that depends on the type of device structure, temporal parameter degradation caused by BTI depends on the physical properties of the channel and type of gate oxide.

We did not work on the recovery model and we have used the recovery model as given by Reis et al. [24]. The recovery process happens in two stages: The first stage involves a fast recovery caused by $H_2$ atoms inside the gate oxide. The second stage involves a slow recovery caused by $H_2$ due to the back diffusion from gate oxide to $InGaAs$ (bulk or channel). The number of annealed traps consists of two parts represented by the recombination of $H_2$ in $A{l}_2{O}_3$ and the back diffusion of $H_2$ in the gate. At the end of the stress (time $t_0$), the number of generated trap charges is given by the following equation and it becomes zero if $k_f=0$:

$$\begin{array}{c}\hfill \frac{N_{I{T}_{rec}}}{dt}=-k_r(N_H^0-N_H^{\ast })(N_{IT}^0-N_{IT}^{\ast })\end{array}$$

(12)

where, $N_H^0$ is the hydrogen concentration generated after stress at time $t_0$ and C is a constant [7]. Therefore, the change in threshold voltage after recovery is given by:

$$\begin{array}{c}\hfill V_{th}=\alpha \frac{q}{C_{ox}}{N}_{I{T}_{rec}}\end{array}$$

(13)

where $\alpha$ is a multiplication factor that depends on the type of device structure, Equations (11) and (13) describe the stress and recovery process of the trap charges caused by NBTI/PBTI for $InGaAs$-based HEMT, respectively.

6. Modeling of Charge Generation Constant

In this section, a mathematical model of the electron/hole generation constant ($K_f$) for $InGaAs$–FinFET (HEMT) is derived. The following expression conventionally gives the $K_f$ constant:

$$\begin{array}{c}\hfill K_f=\sigma E_{eff}{P}_{eff}\end{array}$$

(14)

where $\sigma$ is the electron/hole capture cross-section, $E_{eff}$ is the effective oxide field across the gate oxide, and $P_{eff}$ is the effective potential. Such factors were all investigated in previous material level studies [25,26]. $\sigma$ depends on the activation energy, temperature, doping concentration, and the layer thickness [25]. The electron capture cross-section area is an important parameter for $K_f$. If the capture cross-section is more than $K_f$, is also more. The electron capture cross-section areas are greater, by 3× of magnitude, than the hole capture cross-section. The electron capture cross-sectional area is very large and has a value that ranges from ${10}^{-15}$ to ${10}^{-14}$. It depends on the recombination center [25,26]. The value of $\sigma$ for $InGaAs$-based HEMT can be given by:

$$\sigma ={\sigma }_{\infty }exp\left(\frac{-E_B}{KT}\right)$$

(15)

where $E_B$ is the activation energy, ${\sigma }_{\infty }$ is the pre-exponential factor, K is the Boltzmann constant, and T is the temperature in Kelvins. The values of the pre-exponential factor ${\sigma }_{\infty }$ and the activation energy $E_B$ for an $InGaAs$ substrate and insulator $A{l}_2{O}_3$-based HEMT are derived in this work. The default value of ${\sigma }_{\infty }$ used in the literature is in the range of $6\times {10}^{-15}$ to $1\times {10}^{-17}$ [25], and the values of ${\sigma }_{\infty }$ for $GaAs$ and $InGaAs$ are $6\times {10}^{-15}$ and $1\times {10}^{-20}$, respectively [25]. Hence, these values have been employed in different simulation experiments to find the optimal value for the $InGaAs--A{l}_2{O}_3$ interface. The change of the electron capture cross-section with respect to temperature variation is depicted in Figure 9 which shows that $K_f$ is directly proportional to the temperature and that $K_f$ increases as $V_{gs}$ increases. The effective oxide field ($E_{eff}$) and the effective potential $P_{eff}$ depends on the gate voltage ($V_{gs}$), the threshold voltage ($V_{th}$), and the oxide capacitance ($C_{ox}$). Hence, $k_f$ can be modeled as:

$$\begin{array}{c}\hfill k_f={\sigma }_{\infty }exp\left(\frac{-E_B}{KT}\right)\left[exp\left(\frac{E_{ox}}{E_0}\right)C_{ox}(V_{gs}-V_{th})\right]\end{array}$$

(16)

$$\begin{array}{c}\hfill k_r={\sigma }_{\infty }exp\left(\frac{-E_B}{KT}\right)\left[C_{ox}(V_{gs}-V_{th})\right]\end{array}$$

(17)

The annealing constant $K_r$ also depends on the oxide electric field, the gate voltage, and the threshold voltage of the device. For $K_r$, $V_{gs}$ is either zero or has a positive value for apposite stress. The values of $E_{ox}$ and $E_0$ are always zero. The parameter values extracted from the simulation results and are listed in

Table 2. Extracted BTI model parameters for $InGaAs--A{l}_2{O}_3$ interface.

${\sigma }_{\infty }$	$1\times {10}^{-16}$
K	$1.38\times {10}^{-23}$
$EOT$	1.8 nm
$K_{A{l}_2{O}_3}$	9
${ϵ}_0$	$8.85\times {10}^{-14}$
$K_r=K_{r0}{e}^{\frac{E_A{K}_r}{kT}}$	$K_{r0}=9.9\times {10}^{-7}$
$D_{H0}$	9.56 × 10−11 cm2/s
$E_a$	0.2 eV
$E_{ox}$	2 eV
$E_0$	0.5 eV
$N_0$	$2\times {10}^{11}$
$\xi$	0.58
$E_B$	0.054 eV

.

Modeling of Hydrogen Diffusion Constant

Another important factor for BTI-induced trapping is Hydrogen diffusion constant ($D_H$). As per experimental data, the value of $E_B$ for the $InGaAs$–$A{l}_2{O}_3$ interface is in the range of 0.05 to 0.066 eV [5,25]. Temperature is important parameter for the diffusion constant. These parameters were extracted for the BTI model using different experimental data in these papers [5,25]. The Hydrogen diffusion constant $D_0$ is given by:

$$\begin{array}{c}\hfill D_H=D_{0}exp\left(\frac{-E_a}{KT}\right)\end{array}$$

(18)

where $E_a$ is the activation energy, K is the Boltzmann constant, and T is the temperature. The value of $D_0$ for $H_2$ diffusion in $A{l}_2{O}_3$ ranges from $1.5\times {10}^{-5}$ to $1\times {10}^{-6}$ as per the state-of-the-art experimental results [5,25]. The diffusion constant values for varying temperatures are shown in Figure 10 which shows that the diffusion constant is highly dependent on the temperature. Therefore, the temperature is an important parameter required to estimate $K_f$, $K_r$, and $D_H$. All the related parameters for the $InGaAs$-based HEMT are shown in Table 2.

7. Model Verification and Circuit Simulation

To verify the proposed model, modeling results are compared with the experimental result. The first model is verified for silicon-based MOSFET (Figure 11) and further, it is verified for 3D InGaAs HEMT. It is also used to predict the lifetime prediction of the SRAM. The required parameters are calculated from the model file for the model. The flat band voltage and the vertical gate oxide ($E_{ox}$) are calculated from the BSIM model then the change in the threshold voltage ($V_{th}$) due to PBTI is calculated. All calculated and optimized parameters are shown in Table 2. The comparative results for the model with the experimental results for the change in the threshold voltage are shown in

Table 3. Comparison of the modeling results with the experiment results.

S.No.	$\mathsf{\Delta }{\mathit{V}}_{\mathit{th}}$	Stress Time(s)	${\mathit{t}}_{\mathit{ox}}$	Ref.
1	0.15	1000	2.0	[27]
2	0.125	1000	4.2	[28]
3	0.15	1000	3.5	[29]
4	0.15	1000	1.8 nm	[30]
4	0.15	1000	1.8 nm	Calculated in this work

[27,28,29,30]. All results are calculated for different device dimensions, but one of the available studies is very similar to the proposed work, hence, we made a detailed comparison with the similar study. Hence, the proposed model has been further verified using the experimental results for 10-year stress and different temperatures values obtained from data given by Franco et al. [30]. The stress voltage from −1 V to maximum $V_{gs}$ has been applied for the P-FinFET. The initial trap density ($N_0$) from −1 V to maximum $V_{gs}$ was extracted from [30]. The hole capture constant ($K_f$) is calculated using the proposed model and calibrated as per the literature. The simulation results for 10-year stress are shown in Figure 12 [30] which clearly shows that PBTI is strongly affected by the vertical electric field has a linear relationship with $V_{gs}$. A similar plot at a $log$ scale is shown in Figure 13 [30].

Circuit simulation was conducted using the 6T SRAM cell for testing purposes. The total change in the trap charge density for three-year stress and the corresponding shift in the threshold voltage was calculated. The simulation flow and strategy are shown in Figure 14. The initial charge density and the other parameters are calculated from the device model file. In HSPICE, the parameters given by the $.param$ command in the spice net-list are used to calculate the change in the threshold voltage due to BTI i.e., $v_{th}=v_{th0}+\mathsf{\Delta }{V}_{th}$. The $.alter$ command used to simulate the second stage gives the final simulation output. Figure 15 shows the comparative results of the proposed model and TCAD simulation for a 6T SRAM cell. The SNM and RNM results of the 6T SRAM cell are calibrated according to the TCAD simulation results.

8. Conclusions

Static Random-Access Memory (SRAM) is used as a data storing and processing element in Wireless Sensor Networks and the Internet of Things (IoT) applications. Hence, SRAM should be a high-performance, reliable element. In this work, We have analyzed the stability of the 6T using the two-stage NBTI and degradation models under the deference electric stress. It is revealed from the results that NBTI affects almost 20% of the stability compared to the conventional target design only in the three-year stress. Also, the RD-based BTI model was modified for the 3D $InGaAs$-based HEMT and presented as a proposed BTI model for circuit simulation. This model has been used for lifetime prediction of the 6T SRAM cell. The BTI model parameters have been calculated, extracted, and optimized using material parameters and device geometrical dimensions. The modified model contains all the main characteristics of the reaction–diffusion model. The proposed model can be used to predict DC stress for electrical stresses. Consequently, this model can be utilized to predict BTI under real device and circuit working conditions.