A Performance Analysis Framework of Time-Triggered Ethernet Using Real-Time Calculus
Abstract
:1. Introduction
- This paper proposes a performance analysis framework of TTEthernet. The abstract model of TTEthernet consists of the data model, resource model and component model, and RTC is applied to analyze the feasibility of abstract model.
- We discuss the impacts of clock synchronization and different traffic integration strategies on delay bounds of TT traffic, backlog bounds of processing nodes and resource utilization of the network.
- Finally, the paper concludes the feasibility of the performance analysis framework through discussing a specific case that mainly focuses on different traffic integration strategies.
2. Related Work
3. Preliminaries
3.1. Time-Triggered Ethernet
3.2. Real-Time Calculus
4. Performance Analysis Framework
4.1. Data Model
4.2. Resource Model
4.3. Abstract Model
5. Performance Analysis
6. Case Study
7. Conclusions
Author Contributions
Funding
Conflicts of Interest
Abbreviations
TTEthernet | time-triggered Ethernet |
RTC | real-time calculus |
TT | time-triggered |
ET | event-triggered |
RC | rate-constrained |
BE | best-effort |
AFDX | Avionics Full-Duplex Switched Ethernet |
BAG | bandwidth allocation gap |
PCF | protocol control frames |
CS | cold-start |
CA | cold-start acknowledge |
IN | integration |
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Flow | Route | Period (ms) | Size (B) |
---|---|---|---|
--- | 2 | 880 | |
-- | 1 | 730 | |
--- | 2 | 340 | |
--- | 2 | 560 | |
-- | 2 | 1300 | |
-- | 2 | 900 | |
Flow | Route | BAG (ms) | Size (B) |
--- | 2 | 1320 | |
--- | 2 | 890 | |
-- | 4 | 1250 | |
-- | 2 | 760 | |
--- | 8 | 900 | |
--- | 2 | 1050 | |
--- | 2 | 1200 | |
-- | 2 | 980 |
Link | VL ID | Time Slot (ms) |
---|---|---|
[, ] | 1 | [0.65, 0.90] |
2 | [0.35, 0.60] | |
3 | [1.05, 1.30] | |
[, ] | 4 | [1.70, 1.95] |
5 | [1.05, 1.30] | |
[, ] | 1 | [1.40, 1.65] |
3 | [0.10, 0.35] | |
4 | [0.75, 1.00] | |
[, ] | 2 | [0.45, 0.70] |
5 | [0.80, 1.05] | |
[, ] | 6 | [1.35, 1.60] |
[, ] | 1 | [0.65, 0.90] |
6 | [1.00, 1.25] | |
[, ] | 3 | [0.80, 1.05] |
4 | [1.70, 1.95] |
Node | WCB (bits) |
---|---|
24,160 | |
14,880 | |
78,080 | |
65,280 | |
7200 |
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Yang, X.; Huang, Y.; Shi, J.; Cao, Z. A Performance Analysis Framework of Time-Triggered Ethernet Using Real-Time Calculus. Electronics 2020, 9, 1090. https://doi.org/10.3390/electronics9071090
Yang X, Huang Y, Shi J, Cao Z. A Performance Analysis Framework of Time-Triggered Ethernet Using Real-Time Calculus. Electronics. 2020; 9(7):1090. https://doi.org/10.3390/electronics9071090
Chicago/Turabian StyleYang, Xiuli, Yanhong Huang, Jianqi Shi, and Zongyu Cao. 2020. "A Performance Analysis Framework of Time-Triggered Ethernet Using Real-Time Calculus" Electronics 9, no. 7: 1090. https://doi.org/10.3390/electronics9071090
APA StyleYang, X., Huang, Y., Shi, J., & Cao, Z. (2020). A Performance Analysis Framework of Time-Triggered Ethernet Using Real-Time Calculus. Electronics, 9(7), 1090. https://doi.org/10.3390/electronics9071090