A Modified Criss-Cross-Based T-Type MLI with Reduced Power Components

Abstract

Significant advancements in the field of power electronics have created an ideal opportunity to introduce various topologies of multilevel inverters. These multilevel inverter topologies comprise different notable characteristics, such as staircase sinusoidal output voltage with high quality, a lowered number of power switches, no filter requirement, etc. In this literature, a new asymmetrical MLI topology is proposed to reduce the number of components of the inverter with admirable voltage-step creation. The proposed topology provides a 17-level, staircase-type, nearly sinusoidal output voltage waveform. The number of switches required for the proposed multilevel inverter topology is fewer compared to the existing topology for the same level. A carrier-based sinusoidal pulse-width modulation technique is used for the proposed topology at a switching frequency of 3 kHz. The functioning of the proposed inverter topology is thoroughly examined. A 17-level asymmetrical inverter is executed; both the MATLAB/SIMULINK as well as the experimental results using dSPACE-1103 controller. The simulation results are verified using the experimental results for the proposed 17-level multilevel inverter for modulation indexes of 1 and 0.6.

1. Introduction

Currently, researchers are directing their attention towards multilevel inverters (MLIs) within the realm of power electronics for a number of reasons. MLIs hold significant sway in power electronics converters due to their numerous applications and associated advantages [1]. Conventional inverters encounter challenges related to waveform quality, switching frequency, and electromagnetic interference (EMI). However, these issues are mitigated in MLIs, as MLIs offer enhanced features for instance superior quality staircase sinusoidal output voltage with reduced total harmonic distortion (THD), a reduced requirement for power switches, and the elimination of the necessity for extra filters [2,3]. MLIs offer improved solutions in diverse applications like high-voltage DC power transmission, electric vehicles, and variable-frequency devices due to their superior features [4,5,6]. Given the numerous constraints, the world is increasingly turning to renewable energy resources. MLIs also prove beneficial in renewable energy power conversion systems, such as those utilizing solar energy and wind energy. MLIs are highly suitable for applications requiring high power and medium voltage. Multilevel inverters (MLIs) have a wide range of applications across various industries due to their ability to generate high-quality AC waveforms with reduced harmonic distortion. Some common applications of MLIs include the following:

(I).

Renewable energy systems: MLIs are widely used in renewable energy systems such as solar photovoltaic (PV) inverters and wind turbine generators for grid integration. They help convert the DC power generated by renewable sources into grid-compatible AC power with improved efficiency and power quality [7,8].

(II).

Motor drives: MLIs are employed in adjustable speed motor drives for controlling the speed and torque of electric motors used in industrial and commercial applications. They provide smoother operation and higher efficiency compared to traditional two-level inverters [9]

(III).

Grid-tied inverters: MLIs are utilized in grid-tied inverters for feeding power from distributed energy resources (DERs) such as solar panels or batteries into the electrical grid. They enable precise control of power flow and support functions like reactive power compensation and voltage regulation [10,11].

(IV).

High-voltage direct current (HVDC) transmission: MLIs are used in HVDC transmission systems for converting AC power to DC power at the sending end and vice versa at the receiving end. They help improve the efficiency and stability of long-distance power transmission [12].

(V).

Electric vehicles (EVs): MLIs play a crucial role in the power electronics systems of electric and hybrid vehicles, converting DC power from batteries or fuel cells into AC power for driving motors. They enable efficient energy conversion and regenerative braking [13,14].

Utilizing multiple DC inputs, MLIs produce a staircase-like output voltage, which closely resembles a sinusoidal waveform, thus minimizing total harmonic distortion [15]. As a result, the need for filters is significantly diminished. Furthermore, the staircase voltage output reduces the dv/dt ratio.

The flying capacitor-based MLI (FC-MLI) was introduced by Dickerson and Ottaway [16] in the US patent filed in December 1969 and granted in 1971. For developing a high-power converter like an FC-MLI, Meynard and Foch [17] introduced a new versatile commutation cell in 1992, with an objective to enable voltage sharing and zero harmonics at switching frequency. The switching circuit and bridge converter circuit [18] for the NPC-MLI (also known as the diode clamped MLI) were filed as a US patent by Baker et al. in 1978 and 1980, being granted in July 1980 and May 1981, respectively. In [19], Nabae et al. developed a three-level neutral point clamped (3L-NPC) inverter. In July 1969, McMurray filed a US (United States) patent [20], granted in 1971, with the objective of providing a new and improved switching power converter circuit (now popularly known as a cascaded H-bridge inverter) that could generate a stepped-wave output voltage. Moreover, another US patent [21] was filed by Baker and Bannister in 1974 for a cascaded H-bridge inverter, granted in 1975.

Although traditional MLIs provide numerous benefits compared to two-level inverters, they also have drawbacks such as the need for a large quantity of power switches. In certain cases, multiple DC voltage sources and capacitors are required. Due to the lower total standing voltage in the recent MLI presented by researchers utilizing lower-rated semiconductor switches, resulting in cost savings to overcome these challenges, numerous new MLI topologies have been proposed with the aim of reducing components and enhancing efficiency. These topologies can be categorized into symmetrical and asymmetrical groups on the basis of the magnitude of the input voltage sources used in the MLI [22,23,24]. Symmetrical MLIs have uniform input voltage magnitudes, whereas asymmetrical MLIs show variations in input voltage magnitudes.

The MLI topology proposed was simulated using sinusoidal pulse-width modulation (SPWM) on the MATLAB/Simulink platform. Following this, an experimental prototype of the multilevel inverter was built in a laboratory, utilizing a dSPACE-1103 controller to validate the simulation result and illustrate its performance at a switching frequency of 3 kHz. This paper is organized into four sections, covering the modulation and control of the MLI in Section 2 and the operation of the proposed topology in all modes in Section 3. Section 4 compares the proposed topology with other existing MLI topologies. Section 5 discusses the simulation parameters and desired outputs, followed by a conclusion provided in Section 6.

2. Proposed Circuit Topology

The proposed 17-level inverter topology, depicted in Figure 1, comprises thirteen switches labelled from S₁ to S₈, including two bidirectional switches (S₂ and S₇) and six unidirectional switches (S₁, S₃, S₄, S₅, S₆, and S₈). The unidirectional switches operate across two quadrants whereas the bidirectional switches operate across four quadrants. This configuration utilizes four isolated DC sources, 3V_dc, 3V_dc, V_dc, and V_dc, operating in an asymmetrical mode. Without utilizing an H-bridge at the output, these asymmetric sources and switch configurations provide distinct pathways for producing positive and negative 17-level bipolar output voltage. The specified magnitude for the isolated DC sources is V_dc = 39 V and 3V_dc = 117 V.

Three distinct configurations of bidirectional switches are well presented in [25] and can be explained as follows:

(I).

Common emitter configuration: This configuration utilizes an insulated gate bipolar transistor in a common emitter configuration. The common emitter setup involves the emitter terminal being common between the input and output circuits. In this arrangement, the IGBT serves as the main switching element, controlling the flow of current bidirectionally, as depicted in Figure 2a.

(II).

Power switch with four-diode configuration: This configuration incorporates a diode bridge switch. A diode bridge consists of four diodes arranged in a bridge configuration, allowing for current to flow bidirectionally. However, this setup typically involves more diodes compared to other configurations, potentially leading to higher conduction losses, as depicted in Figure 2b.

(III).

Common collector configuration: This configuration employs an IGBT in a common collector setup. In a common collector arrangement, the collector terminal serves as the common connection point between the input and output circuits. Here, the IGBT controls the current flow bidirectionally while providing a different configuration compared to the common emitter setup as depicted in Figure 2c.

Figure 2. Different types of configurations for bidirectional switches: (a) common emitter configuration; (b) power switch with four-diode configuration; (c) common collector configuration.

Figure 2. Different types of configurations for bidirectional switches: (a) common emitter configuration; (b) power switch with four-diode configuration; (c) common collector configuration.

Modulation and Control of MLI

Many control modulation strategies have been presented by the researchers, including carrier-based pulse-width modulation, selective harmonic elimination (SHE), nearest level control, and space vector pulse-width modulation (SVPWM) [26,27,28]. Modulation techniques are essential for improving the efficiency of MLIs by minimizing switching losses, optimizing voltage and current waveforms [29]. In this study, the SPWM control modulation technique was used to produce the switching signal for a 17-level inverter, as depicted in Figure 3a. A carrier-based PWM modulator consists of both modulation signals and a carrier signal. The reference signal is represented by the red line which is typically a sine wave. The carrier signals are represented by different colors as triangular waves or sawtooth waves. Multiple carriers are shown, each in a different color. These carriers are compared with the reference signal to generate the PWM signals. To generate a switching signal for the 17-level inverter, 16 triangular carrier waveforms are utilized. The digital output is produced by continually comparing the carrier signals with the reference signal using sixteen comparators. As shown in Figure 3b, the sixteen output signals of the comparator were aggregated to create the inverter switching signal. The generated switching signal for a single-phase, 17-level inverter is depicted in Figure 3b along with the accompanying real-time simulation result. Further decoding of the switching signals yields the gate pulses for the relevant switching devices of the proposed MLI.

3. Modes of Operation

The different modes of voltage generation for the 17-level inverter are illustrated in Figure 4. The positive half-cycle voltage generation path of the proposed topology is represented by the red line while the negative half-cycle is represented by the blue one.

The working of the 17-level inverter is elucidated below:

• Switches S₁, S₅, and S₈ are activated to produce +8V_dc, as illustrated in Figure 4a, while S₃, S₄, and S₆ are turned ON to generate −8V_dc.
• The power switches S₁, S₅, and S₇ are turned ON to generate +7V_dc, as illustrated in Figure 3b, whereas S₃, S₄, and S₇ are activated to generate −7V_dc.
• Switches S₁, S₅, and S₆ are activated to achieve +6V_dc, as illustrated in Figure 4c, whereas S₃, S₄, and S₈ are turned ON to generate −6V_dc.
• Switches S₂, S₅, and S₈ are turned ON to achieve +5V_dc, as illustrated in Figure 4d, whereas S₂, S₄, and S₆ are turned ON to generate −5V_dc.
• Switches S₂, S₅, and S₇ are turned ON to achieve +4V_dc, as illustrated in Figure 4e, whereas S₂, S₄, and S₇ are turned ON to generate −4V_dc.
• Switches S₂, S₅, and S₆ are turned ON to achieve +3V_dc, as illustrated in Figure 4f, whereas S₂, S₄, and S₈ are activated to generate −3V_dc.
• Switches S₃, S₈, and S₅ are turned ON to achieve +2V_dc, as illustrated in Figure 4g, whereas S₁, S₄, and S₆ are activated to generate −2V_dc.
• Switches S₂, S₅, and S₇ are activated to generate +V_dc, as illustrated in Figure 4h, whereas S₁, S₄, and S₇ are activated to produce −V_dc.
• Switches S₃, S₅, and S₆ are activated to produce 0V_dc.

The switching mode of the proposed 17-level inverter have been shown in

Table 1. Switching status of switches for 17-level inverter topology.

	S1	S2	S3	S4	S5	S6	S7	S8
+8Vdc	√	×	×	√	×	×	×	√
+7Vdc	√	×	×	×	√	×	√	×
+6Vdc	√	×	×	×	√	√	×	×
+5Vdc	×	√	×	×	√	×	×	√
+4Vdc	×	√	×	×	√	×	√	×
+3Vdc	×	√	×	×	√	√	×	×
+2Vdc	×	×	√	×	√	×	×	√
+1Vdc	×	√	×	×	√	×	√	×
0Vdc	×	×	√	×	√	√	×	×
−1Vdc	√	×	×	√	×	×	√	×
−2Vdc	√	×	×	√	×	√	×	×
−3Vdc	×	√	×	√	×	×	×	√
−4Vdc	×	√	×	√	×	×	√	×
−5Vdc	×	√	×	√	×	√	×	×
−6Vdc	×	×	√	√	×	×	×	√
−7Vdc	×	×	√	√	×	×	×	×
−8Vdc	×	×	√	√	×	√	×	×

. The use of green (√) and red (×) symbols signifies the states of switches within the inverter circuit. When a switch position is marked with a green check mark (√), it indicates that the corresponding switch is in the “on” state. Conversely, when a switch position is marked with a red cross (×), it indicates that the switch is in the “off” state.

4. Comparative Study

In recent years, several newly developed MLI configurations have been introduced and analyzed in the various literature [30,31,32,33,34,35,36]. These analyses typically focus on different performance metrics, including the total number of power switches, input DC sources, and capacitors, as well as main diodes.

Table 2. Comparative study illustrating generalized formulations for Z number of output voltage levels.

Cited Papers	Total Number of Switches	Isolated DC Sources	Capacitors	Main Diodes
[30]	$Z+1$	$\left(Z-1\right)/2$	0	$Z+1$
[31]	3$\left(Z-1\right)/2$	$\left(Z-1\right)/2$	0	$3\left(Z-1\right)/2$
[32]	$7\left(Z-1\right)/8$	2	$\left(Z-3\right)/2$	$\left(Z-1\right)/8$
[33]	$2\left(Z-1\right)$	1	$\left(Z-1\right)/2$	2$\left(Z-1\right)$
[34]	$\left(Z+3\right)$	1	$\left(Z-1\right)/2$	$(Z+3)$
[35]	$\left(Z+5\right)/2$	1	$\left(Z-1\right)/2$	4
[36]	$\left(Z+3\right)$	$\left(Z-1\right)/2$	0	$\left(Z+3\right)$
Proposed MLI	$\left(Z-9\right)$	$\left(Z-9\right)/2$	0	$\left(Z-7\right)$

presents generalized formulas for these different MLI topologies proposed in the literature, where $Z$ represents the number of output voltage levels of proposed topologies. For a specific example, such as a 17-level inverter, the relevant references are compiled in

Table 3. Comparative study for 17-level inverter.

Cited Papers	Voltage Level $\left(\mathit{Z}\right)$	Total Number of Switches	Isolated DC Sources	Capacitors	Main Diodes
[30]	17	18	8	0	18
[31]	17	24	8	0	24
[32]	17	14	2	6	2
[33]	17	36	1	8	32
[34]	17	20	1	8	20
[35]	17	11	1	8	4
[36]	17	20	8	0	20
Proposed MLI	17	8	4	0	10

. The quantity of required gate driver circuits is equivalent to the quantity of switches utilized, as each switch necessitates one gate pulse for operation. Main diodes are those connected with the switches; a unidirectional switch typically involves one anti-parallel diode, while a bidirectional switch may have two or four associated diodes.

A comprehensive analysis and comparison was carried out with recently introduced topologies [30,31,32,33,34,35,36]. The circuits of the compared manuscript is depicted in Figure 5. In Table 3, a comparative study is shown for the 17-level output. From the comparative study, it can be concluded that the required total number of switches for the proposed MLI is the least compared to the other cited topologies. This reduction in the number of power switches not only simplifies construction but also enhances the control and reliability of the system, making it cost-effective. This can be considered as the advantage of the proposed topology.

5. Simulation and Experimental Result

The proposed MLI topology was simulated, employing level-shifted SPWM on the MATLAB/Simulink platform. Subsequently, a prototype model of the MLI was constructed in a laboratory, employing a dSPACE-1103 controller. The components utilized in this prototype model include power switches (IGBT-CT60AM), gate driver circuits (TLP250), isolated DC sources, a DSO-X 2024A oscilloscope, and an RL load, as illustrated in Figure 6.

The blocking voltage in an MLI is critical for ensuring the reliability and safety of the circuit. It refers to the voltage rating that each switching device must withstand when in the off state. Overvoltage leads to semiconductor device failure and potentially damages the entire inverter circuit. Therefore, selecting switching devices with appropriate voltage ratings is crucial in MLI design to ensure dependable and safe operation. The blocking voltages across the switches S₁, S₂, S₃, S₄, S₅, S₆, S₇, and S₈ are as follows: 250 V, 120 V, 225 V, 78 V, 40 V, 78 V, 305 V, and 305 V, respectively, as depicted in Figure 7.

The simulation and experimentation were performed for the proposed 17-level inverter with two distinct loads: one with R = 180 Ω, L = 150 mH, and the other with R = 180 Ω, L = 25 mH at modulation index (MI) 0.6 and 1. The input volage values were V₁ = V₂ = 39 V and V₃ = V₄ = 117 V, as detailed in

Table 4. Circuit parameters in simulation and experimentation for proposed 17-level inverter.

Parameters	Specification
Switching parameters IGBT	CT-60AM-18F: 900 V, 60 A Von, IGBT = 1.3 V, Von, Dio= 1.5 V, RDio = 0.01 Ω, RIGBT = 0.11Ω, β = 3
Types of switching devices and their controlling elements	Driver Controller	TLP250: 10–35 V, ±1.5 A DS1103
Parameters of simulation and experiment	(V1 = V2 = 39 V, V3 = V4 = 117 V) R = 180 Ω, L = 150 mH, Vpk = 196 V, Ipk = 0.78 A, MI = 0.6
	(V1 = V2 = 39 V, V3 = V4 = 117 V) R = 180 Ω, L = 150 mH, Vpk = 320 V, Ipk= 1.17 A, MI = 1
	(V1 = V2 = 39 V, V3 = V4 = 117 V) R = 90 Ω, L = 25 mH, Vpk = 196 V, Ipk = 2.2 A, MI = 0.6
	(V1 = V2 = 39 V, V3 = V4 = 117 V) R = 90 Ω, L = 25 mH, Vpk = 320 V, Ipk = 3.2 A, MI = 1

, with the output voltage and load current.

The simulation results for the proposed 17-level inverter at MI = 0.6 are illustrated in Figure 8. The simulation was conducted with an RL load, where R = 180 Ω and L = 150 mH. The input voltage parameters were set to V_dc = 39 V and 3V_dc = 117 V, as per the proposed topology. In Figure 8a, the simulation output voltage (Vo/p max) is shown to be 196 V. Similarly, in Figure 8b, the load current (Io/p max) is measured at 0.78 A for the same input DC voltage. The experimental result validates the simulation results of output voltage and load current, as shown in Figure 8c.

The performance analysis of the proposed 17-level inverter is conducted with the same set of loads where (R = 180 Ω and L = 150 mH) and input voltage (V_dc = 39 V and 3V_dc = 117 V) at MI = 1. Results from both simulations and experiments are depicted in Figure 9. In Figure 9a, the simulation result shows an output voltage of 320 V. Correspondingly, in Figure 9b, the load current is measured at 1.4 A. Furthermore, the simulation results for the output voltage and load current at MI = 1 were validated by the experimental data, as depicted in Figure 9c.

The simulation and experimentation were performed for the proposed 17-level inverter with the loads R = 90 Ω, L = 25 mH at MI = 0.6. The input volage values were V₁ = V₂ = 39 V and V₃ = V₄ = 117 V. The simulation output voltage (Vo/p max) was 196 V, as depicted in Figure 10a, and the load current was 1.8 A, as depicted in Figure 10b. The experimental result for the output voltage and the load current is shown in Figure 10c, which validates the simulation result.

The simulation and experimentation were performed with the loads R = 90 Ω, L = 25 mH at MI = 1 for the input volage values V₁ = V₂ = 39 V and V₃ = V₄ = 117 V. The simulation output voltage (Vo/p max) was 320 V, as depicted in Figure 11a, and the load current was 2.4 A, as depicted in Figure 11b. The output voltage and load current observed experimentally as depicted in Figure 11c aligned closely with the simulation results, further validating the effectiveness and accuracy of the proposed 17-level inverter.

6. Conclusions

This paper introduced a new criss-cross-based T-type MLI topology for 17-level output voltage. A comparative study was conducted with the proposed MLI topology. The number of switches required to generate 17-level voltage output is fewer compared to the other compared topologies. The reduction in the number of components makes the proposed topology cost-effective. All the simulation results were validated with a hardware result designed in the laboratory. The future scope of the proposed topology is broad and promising, driven by ongoing advancements in power electronics and renewable energy systems. Some potential avenues for development include investigating its fault-tolerance capabilities, reliability improvement, efficiency enhancement, and its application in motor vehicle and renewable energy systems as an efficient power converter. The limitation of the proposed topology is that it has to be modified on the basis of its application. It is complex in terms of its control strategies and circuit design.