Shallow Trench Isolation Patterning to Improve Photon Detection Probability of Single-Photon Avalanche Diodes Integrated in FD-SOI CMOS Technology
, Thibauld Cazimajou 2, Patrick Pittet 2, Martine Le Berre 1, Mohammadreza Dolatpoor Lakeh 3, Fabien Mandorlo 1, Régis Orobtchouk 1, Jean-Baptiste Schell 3, Jean-Baptiste Kammerer 3, Andreia Cathelin 4, Dominique Golanski 4, Wilfried Uhring 3 and Francis Calmon 1,*Round 1
Reviewer 1 Report
Comments and Suggestions for AuthorsThe paper discusses photon distribution control in a SPAD by a photonic crystal structure using surface and BOX patterning. The idea is of great interest to many readers. Considering practical applications, some important information seems missing. I suggest the following revision and addition of information.
(1) Definition and evaluation of PDP
According to Eq. (3), definition of PDP is separated from the quantum efficiency of photogeneration (let’s call it QEP for now). However, unfortunately, many people use PDP which includes QEP, so that it means photon detection probability with respect to total number of photons incident on a entire pixel structure. Please explain the difference in more detail.
Related to this point, in experiments, please give explanation on how the presented PDP was separated from QEP.
(2) Photon distribution in CMOS area
From the manuscript, I could not read the information on photons “leaking into” or “residing in” the CMOS circuit area. I guess there are some photons in the circuit area. Or is there “zero” photon in this area ? Please give the number and explanation on why the photogenerated carriers in the CMOS circuit area are insignificant. Also, please give more magnified figure of the right most of Figure 4.
(3) Related to (2), if there remain some photons in the circuit area, please specify the acceptable maximum incident photon ratio (intensity) when this SPAD is used in a high illumination condition.
(4) Practically, this structure seems to require light shielding for the CMOS circuit from both sides, i.e., front and back sides. What is a possible device structure to realize such shielding ? Or is such shielding unnecessary concern ? Please explain.
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Reviewer 2 Report
Comments and Suggestions for AuthorsIt is suggested that light gets trapped by making a 2D-diffractive grating through STI patterning the oxide layer that is present in SOI.
The presented grating, however, only changes the direction of the photons when passing it. Due to the achieved angle in the semiconductor, an increased absorption can thus be achieved. For example, in case photons get a 45 degrees direction, the effective interaction length with the SPAD-sensitive layer, increases by the square root of 2 (so an additional 41%).
It could be desirable to “trap” photons, in this SPAD-sensitive layer. For this, the photons should encounter an additional reflection of some sort (through a metallic mirror, or through a Bragg-mirror) for achieving confinement.
However, in the presented structure, once the photons have passed the grating, (if not having been absorbed the first time by the SPAD sensitive layer with the increased absorption length), they will just continue their way into the silicon substrate and be lost. There is thus no trapping of light, only redirection.
That the DCR rate is negatively impacted due to the grating is interesting, but already described in literature.
Further, the magic of Figure 11, achieving a multiplication factor that is highly dependent on small variations of the excess bias has no acceptable explanation. The improvement by a factor of 3 is also excessive considering that the light is not trapped, but only deflected as stated above. If the improvement due to the grating is due to altering the photon directions, it would also not be so dependent on the excess bias. Simulations, explanations, and understanding are not present for backing the factor 3 improvement in any way.
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Reviewer 3 Report
Comments and Suggestions for AuthorsComments:
The paper presents a method to increase the Photon Detection Probability of the FD-SOI SPAD, which use patterned STIs to increase the light trapping to achieve this goal. The author provided the simulation method and measurement results to prove this concept and concluded that the patterned STI nanostructuring can help to improve the PDP while maintaining a comparable level of Dark Count Rate. The paper is well organized and easy to read. However, there are still have some room for improvement. I provided my detailed comments as follows.
1. The authors should pay attention to the abbreviations in the paper. For example, Photon Detection Probability (PDP) appeared two times in Line 42 and Line 61. Same case for “front-side illumination (FSI)”.
2. In the introduction section, you may also check the work from Prof. Jamal Deen and Prof. Robert K. Henderson.
https://scholar.google.ca/citations?user=c8qsopcAAAAJ&hl=en&authuser=2
https://scholar.google.ca/citations?hl=en&authuser=2&user=Veu9OAQAAAAJ
3. Figure 1 is very blur. The word “silicon” is not readable. Please provide a clear version.
4. From Figure 2, it seems that there is no guard ring at the edge of SCR. Do you have any simulation results and light emission test to prove that there is no edge breakdown when SPAD is reversely biased above the breakdown voltage?
5. How do you get the value of “t2” for your simulation, which is the depth of STI?
6. Figure 4 is very blur. Please provide a clear version. You may consider putting the three figures vertically.
7. Same for Figure, it is blur.
8. Line 234, could you please provide more detailed explanations for the reasons of abrupt change of DCR for the SPAD with patterned STIs? Please also describe more for the term “afterpulsing runaway”.
9. In Figure 10, the excess voltages are different for two figures. For fair comparison, it is better to have the same vex.
10. Same comments on Vex for Figure 12.
Comments on the Quality of English LanguageNo comment.
Author Response
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Reviewer 4 Report
Comments and Suggestions for AuthorsIn this paper, a nanostructurated layer generates light trapping and consequently light sensitivity increase in front side illumination. The content is enough, and the manuscript needs a major revision before considering its acceptance in this journal. Some suggestions are described as following:
1. Many abbreviations are adopted in this paper including title and main text. Particularly, it is not suitable to use abbreviations in title, such as STI, FSI, PDP, SPAD, FD, SOI, CMOS. Of course, CMOS is familiar for us, however, most abbreviations are unconversant. Please revise this part.
2. Some expressions are not suitable such as PDP relative gains thanks to the STI patterning. Here, the thanks to should be reconsidered. Please check whole contents and revise such expressions.
3. The authors demonstrate a patterning nanostructure to enhance the device performance, however, there lacks the details of this nanostructured layer, including the size, density and area. The pattern size is important to influence the light capture. Please provide more details and discussions.
4. Some recent progress towards photodetectors are suggested to be included in the introduction part, such as Small, 2023, 19, 2206310, Adv. Funct. Mater. 33 (2023) 2213334, Adv. Sci. 10 (2023) 2206417. https://doi.org/10.1007/s12598-021-01909-8, https://doi.org/10.1007/s12598-022-02012-2, https://doi.org/10.1007/s12598-022-02113-y
Comments on the Quality of English LanguageNo
Author Response
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Round 2
Reviewer 1 Report
Comments and Suggestions for AuthorsPlease see attached file.
Comments for author File: Comments.pdf
Author Response
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Author Response File: Author Response.pdf
Reviewer 2 Report
Comments and Suggestions for Authors1) Although there is no light trapping, as admitted, it is still mentioned on many places (9 times). Even in the abstract.
2) The 3X improvement figure 11 c is explained by the authors as follows:
“Considering Figure 11, here are a few comments that are also mentioned in section 4:
This higher relative gain increase with excess voltage for patterned SPAD compared to reference structure can be explained by:
i) higher avalanche triggering probability __, due to STI patterning (according to previous TCAD study [13]),
ii) higher number of photogenerated carriers due to constructive light interference in the multiplication region.
iii) extension of the depleted zone (multiplication region) with Vex.”
This is not convincing:
i) reference 13 doesn’t mention a single time STI, nor an improvement based there-on.
ii) The horizontal SCR layer mentioned by the authors will see indeed area’s of increased amplitude, however, these are alternated by area’s with much less amplitude (as can be expected and confirmed by their own simulation in Figure 4, Cartography).
iii) Going from Vex=0.5 to Vex=0.7 is an increase of 1.43% of the excess bias compared to Vbd. (it has been added in the text that 0.7V excess voltage is 5% of Vbd, so 200mV is an increase of 1.41%). The increase of depletion width goes with the square root of the voltage change, so the increase of SCR width can then be estimated to be only 0.715%. This is a very small change and will barely change the PDP!
3) Reference 17 : “3D Electro-optical Simulations for Improving the Photon Detection Probability of SPAD Implemented in FD-SOI CMOS Technology”:
They consider STI layer patterning mentioning the following: “Simulation shows an increase of PDP spectrum of over 50% at wavelengths of 400-550nm and 750-1000nm and of 10-15% at the wavelengths of 550-750nm, compared to a reference SPAD without any nanostructuration” . This is what I mentioned in my initial reply as a to-be-expected improvement level (I mentioned 40% improvement).
Conclusion: A three times increased PDP (+200%) is totally not understood, neither explained with new insights on why, it is contradictory to what can be expected, and by what has been simulated earlier [17]. Also from the authors' simulation in this paper itself, there is no understanding or insight added for this fantastic (unrealistic) improvement.
Author Response
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Reviewer 3 Report
Comments and Suggestions for AuthorsThank you for addressing all my comments.
Author Response
The authors would like to thank the reviewer for analysing the manuscript and agreeing to its publication.
Reviewer 4 Report
Comments and Suggestions for AuthorsAn acceptance is suggested.
Author Response
The authors would like to thank the reviewer for analysing the manuscript and agreeing to its publication.
Round 3
Reviewer 2 Report
Comments and Suggestions for AuthorsI keep rejecting
Author Response
Despite our best efforts, we regret that reviewer #2 has maintained his rejection decision.
No new questions were raised by reviewer #2, so we are attaching a revised version in response to comments of reviewer #5.
Yours sincerely
Francis Calmon
Author Response File: 
Author Response.docx
