Power-Efficient Electronically Tunable Fractional-Order Filter

Abstract

This article describes a low-voltage, low-power fractional-order low-pass filter (FO-LPF) of order 1 + α, which is implemented using a voltage differencing differential difference amplifier (VDDDA). The VDDDA structure is implemented using the bulk-driven metal oxide semiconductor transistor technique. The transistors operate in the subthreshold region to maintain low-supply voltage and low-power consumption. The FO-LPF structure implemented using this VDDDA structure is compact. It includes three VDDDAs and three grounded capacitors along with two active resistors implemented using MOS transistors. In addition, this filter structure provides electronic tuning of its order and cut-off frequency through the bias current of the active component used. The effects of tracking error and parasitics on the functionality of the proposed FO-LPF were investigated. The VDDDA and filter operate at ±300 mV and dissipate only 207 nW and 663 nW of power, respectively. Thus, the VDDDA structure and filter are suitable for low-voltage and low-power operation. Layouts of the proposed VDDDA as well as the FO-LPF were designed in the Cadence Virtuoso environment. Post-layout simulation results of the designed circuits imply that they are suitable for fabrication. Noise, total harmonic distortion, Monte-Carlo, and PVT analyses were also performed.

1. Introduction

The utilization of fractional calculus (FC) is being observed increasingly within the engineering domain due to its ability to provide a more precise representation of natural phenomena and physical entities compared to integer-order (IO) models, making their study and control easier. Fractional-order (FO) systems offer greater design flexibility compared to IO systems. FO systems provide more design adaptability than IO systems. Although the mathematical basics of FC evolved around 200 years ago, this topic remained restricted only to mathematicians until it found its importance in diverse engineering fields, such as material theory, diffusion theory, control theory, bioengineering, circuit theory and design, electromagnetics, and robotics. In the case of circuit theory, fractional-order systems find applications in transmission media, power electronics, multivibrator circuits, integrator–differentiator circuits, chaotic systems, oscillators, resonators, filters, memristive elements, and many more [1,2,3,4]. The demand for active filters in diverse fields, including analog signal processing, is experiencing a significant surge. The order of a filter is a significant attribute, which is determined by its slope in the transition band. Order is generally a real number, but while designing a filter using traditional methods, it is rounded off to the nearest integer. Therefore, accurate requirements for frequency response are not achieved. Nevertheless, the FO design methodology enables researchers to have precise control over the various parameters of the filter. IO filters have a slope of −20 × n dB/decade, where n is a positive integer. Fractional order filters (FOFs), a generalized case of IO filters, have a slope of −20 × (n + α) dB/decade for an FOF of order (n + α), where n is a positive integer and α is a real number between 0 and 1 [4,5].

The successful implementation of FOFs necessitates the use of fractional-order passive elements (FOEs). These FOEs can be fractional-order capacitors (FOCs) or fractional-order inductors (FOIs). The commercial viability of FOEs has yet to be achieved, despite numerous attempts to manufacture them [3,4]. Because of the above-stated reason, for designing FOFs, integer-order approximations are used. There are two design techniques [3,6]. One approach involves approximation of integer-order capacitors and integer-order inductors by FOCs and FOIs, and thus, a generalized form of conventional filters in the fractional domain is obtained. The approximation mentioned above can be achieved by approximating FOEs by building RL or RC networks [3,4,7]. Using this approach, several structures are present in the literature where operational amplifier (OPAMP) [8,9], second-generation current conveyor (CCII) [10], operational transconductance amplifier (OTA) [11], and differential voltage current conveyor (DVCC) [12,13] are used as active elements. Nevertheless, the utilization of this approximation to create FOFs is accompanied by the disadvantage of incorporating floating resistors and capacitors during the implementation of FOEs [4,7]. Additionally, the obtained filter does not provide tuning of its order. The second approach is to approximate properly the transfer function (TF) of FOFs through a suitable integer-order approximation. To implement this technique, the Laplacian variable (τs)^α, is approximated using continued fraction expansion (CFE), a commonly used approximation technique. Several filter structures that use this approach are available in the literature. These implementations are achieved by utilizing OPAMP [14], current feedback operational amplifier (CFOA) [15,16], OTA, current follower (CF), and adjustable current amplifier (ACA) [17,18], differential difference current conveyor (DDCC) [19], current differencing buffered amplifier (CDBA) [20], and universal voltage conveyor (UVC) [21] as their active building blocks.

The voltage differencing differential difference amplifier (VDDDA) block, first described in [22], is a truly versatile analog building block that has a combined feature of OTA and differential difference amplifier (DDA). Therefore, the VDDDA block proves to be advantageous in situations where the tuning of filter parameters and summing of voltages are required simultaneously, as it makes the design compact. A literature survey of VDDDA-based filters reveals several available structures, such as multifunction filters [23], universal filters [24,25], or all-pass filters [22]. Out of all these filters, only [25] presents VDDDA based on the LV-LP technique, and it is also observed that until now, VDDDA has not been employed for the implementation of FOF.

Among the existing works, only [19] provides a filter structure that is capable of operating at low-voltage supply (LV) and low-power consumption (LP), because the DDCC structure is implemented using the bulk-driven quasi-floating gate (BD-QFG) technique. Generally, fractional-order filters are meant to be utilized in the processing of biological signals. Therefore, the utilization of the LV-LP technique would yield significant advantages in the implementation of such filters. The bulk-driven (BD) technique is considered a viable strategy for operating analog circuit designs in LV-LP conditions. This technique eliminates the barrier posed by the threshold voltage in the signal path. However, BD MOSFET offers bulk transconductance, which is three to five times lower than that of gate-driven MOSFET. This low transconductance value of the BD MOSFET leads to a lower intrinsic voltage gain and a reduced bandwidth for the resulting circuit. However, these limitations can be leveraged as a desirable characteristic for applications such as biomedical, as biological signals typically exhibit a frequency range of 0.05 to 10 kHz and amplitude levels ranging from 0.015 to 5 mV, and also because their prime requirements are low-voltage operation and lower power consumption. Operating BD MOSFET in the subthreshold region seems to be a great option to attain low power and low-frequency operation in electronic gadgets.

A fractional-order low-pass filter (FO-LPF) is often used in the detection of sleep apnea syndrome [26]. Due to sleep apnea, there is a prolongation of cardiac inter-beat intervals. These prolongations are detected by applying the energy signal obtained from an electrocardiogram (ECG) to an FO-LPF. In the realm of wearable biomedical systems, the utilization of low-power systems becomes imperative due to the critical significance of minimizing dissipation power. For instance, in an electrocardiogram (ECG) acquisition system, a low-pass filter (LPF) is employed to eliminate noise [27,28].

The aforementioned studies show that only a few structures of FOF are available for its operation in the LV-LP domain and that the mentioned benefits of VDDDA have not been explored in designing FOF. Therefore, this study presents the implementation of the proposed VDDDA using bulk-driven MOSFETs and operated in the subthreshold region. The CMOS structure has a power supply range of ±300 mV and power dissipation of 207 nW, rendering it well-suited for applications that require low voltage and low-power consumption. Subsequently, the FOF structure is implemented using the proposed VDDDA. The CFE method is employed as an approximation technique for the fractional operator, and the resulting circuit is realized using IFLF topology. The proposed FOF structure utilizes a minimal configuration consisting of three VDDDAs, six MOS transistors, and three grounded capacitors. The filter circuit operates with a power supply of only ±300 mV and has a power consumption of 663 nW. These values are the least among the compared literature studies. Additionally, the filter also offers electronic and independent tuning of its order and pole frequency. The remainder of the article is organized as follows. Section 2 analyzes VDDDA behavior, its proposed structure using the LV-LP technique, and simulation results. Section 3 presents the proposed VDDDA-based fractional order low-pass filter, its non-ideality analysis, and simulation results. A comparison of the proposed filter with the FOFs available in the literature is given in Section 4, followed by conclusions in Section 5.

2. Voltage Differencing Differential Difference Amplifier: VDDDA

2.1. Proposed VDDDA

A VDDDA is the active building block (ABB) that provides the advantages of both OTA as well as the differential difference amplifier (DDA). Figure 1a,b, shows the circuit symbol and behavioral model of VDDDA, respectively. VDDDA is a six-terminal block. Out of six terminals, there are four high-impedance voltage input terminals, V₊, V₋, n, and p, a high-impedance auxiliary current output terminal z, and a low-impedance voltage output terminal w. The terminal relationships for an ideal VDDDA are characterized as follows [22]:

$${\mathit{I}}_{\mathit{z}}={\mathit{g}}_{\mathit{m}}({\mathit{V}}_{\mathit{V}+}-{\mathit{V}}_{\mathit{V}-}),{\mathit{V}}_{\mathit{w}}={\mathit{V}}_{\mathit{z}}-{\mathit{V}}_{\mathit{n}}+{\mathit{V}}_{\mathit{p}},$$

(1)

In (1), g_m represents transconductance, and its relationship with bias current (I_b) is given as $g_m=I_b/{(\eta V}_t).$ Here, V_t = KT/q is the thermal voltage and η is the subthreshold slope parameter which is a technology-dependent constant.

The CMOS structure for the proposed BD-VDDDA capable of operating at low voltage is shown in Figure 2. The first stage is the OTA stage, composed of MOSFETs M₁–M_10, where MOSFETs M₁ and M₂ are the bulk-driven PMOS input transistors, and MOSFETs M₇ and M₈ act as an active load. MOSFETs M₅, M_10, and M₄, M₉ act as a current mirror to obtain the output current and its copy at the z_c terminal, respectively. For MOSFETs M₁ and M₂, input is applied at the bulk terminal, and the gate terminal is biased using a constant voltage source, V_G. The second stage is the differential-difference stage comprising MOSFETs M₁₁–M₁₉. The two differential stages at the output are implemented using bulk-driven PMOS transistors M₁₅–M₁₆ and M₁₇–M₁₈. The output terminal, i.e., the drain of MOSFET M₁₉, is shorted to the bulk terminals of MOSFETs M₁₉ and M₁₈ to create a negative feedback loop to improve the accuracy of the gain of the resulting voltage follower. The optimal aspect ratio of the MOSFETs used for the CMOS implementation of VDDDA is mentioned in

Table 1. Aspect ratio of transistors of VDDDA.

Transistor	W (μm)/L (μm)
M1, M2	12/0.6
M3–M5, Mb1, Mb2, Mdc1, Mdc2	10/0.6
M6, M9, M10	7/0.6
M7, M8	4/0.6
M11–M14	4/0.3
M15–M18	10/0.3
M19	20/0.3

. A detailed analysis of structure presented in Figure 2 is available in Appendix A.

2.2. Simulation Results of VDDDA

The bulk-driven CMOS circuit of LV-LP VDDDA operating in the subthreshold region, as shown in Figure 2, is simulated in the Cadence Virtuoso design tool using a 0.18 μm TSMC process parameter with supply voltages, V_DD = −V_SS = 300 mV and V_G = −300 mV. The bias currents I_b and I_dc are set to 14 nA and 55 nA, respectively. All the MOS transistors are operated in the subthreshold region, to derive the complete circuit at the lowest possible supply voltage for obtaining low power consumption. The proposed layout of the BD VDDDA circuit covers an overall area of 1208 μm² (43.8 μm × 27.6 μm) and is shown in Figure 3.

DC and AC analyses were carried out to verify the performance of VDDDA, and the corresponding simulation results are plotted in Figure 4 and Figure 5. From the DC analysis, shown in Figure 4a,b, it can be concluded that the maximum values of terminal voltages without producing significant distortion are up to ±200 mV for the OTA and −240 mV to +200 mV for the DDA, respectively. From the AC analysis shown in Figure 5a, showing pre-layout and post-layout results, it can be observed that the value of g_m at a bias current (I_b) of 14 nA is approximately 200 nA/V. It can be seen that the pre-layout and post-layout results differ slightly from each other due to the impact of parasitic. Figure 5b shows the frequency response of the DDA. The value of gains at low frequency and −3 dB frequency for V_w/V_z, V_w/V_n, and V_w/V_p are found to be −9.1 mdB, 30 mdB, −718 mdB and 158 kHz, 141 kHz, 158 kHz, respectively. The power consumption of the BD-VDDDA circuit is observed to be 207 nW. Hence, a low power consumption value makes this circuit appropriate for low-power applications. The output noise of VDDDA is shown in Figure 6. It is 202 nV/$\surd \mathrm{H}\mathrm{z}$ and 282 nV/$\surd \mathrm{H}\mathrm{z}$ at 10 Hz for pre-layout and post-layout and after that, it follows an exponential decay and decreases to a value of 21.5 nV/$\surd \mathrm{H}\mathrm{z}$ and 30.9 nV/$\surd \mathrm{H}\mathrm{z}$ at 1 kHz for pre-layout and post-layout.

Another compact structure of VDDDA suitable for low-voltage applications was presented in [25]. When the proposed VDDDA was compared with the existing structure, we found that in the existing structure, 17 multiple-input gate-driven MOSFETs are being used in contrast to 19 bulk-driven MOSFETs in the proposed structure. Although the transistor count is low in the existing structure, multiple-input gate-driven MOSFETs are being used which will automatically increase the chip area and thus power dissipation as the multiple-input gate-driven MOSFETs require capacitors at their inputs. Also, the existing circuit uses a power supply of ±900 mV and the power dissipation is 0.99 mW in contrast to ±300 mV and 207 nW for the power supply and power dissipation, respectively, of the proposed circuit. So, in the context of the CMOS structure, the proposed VDDDA is a novel solution and is suitable for low-voltage and low-power applications.

3. Fractional-Order Low-Pass Filter (FO-LPF)

3.1. Basics of FO-LPF of Order 1 + α

The Laplacian operator, s^α, is used to design fractional-order filters. An easy way to use s^α is to use a fractance element, but despite various efforts, most of them are now still in their development stage [29,30]. Because fractance devices are commercially unavailable, physical realizations of these filters are not possible. Neverthless, using continued fraction expansions (CFEs), the obtained second-order approximation for the Laplacian operator is given below:

$$\left(\mathit{\tau }\mathit{s}\right){}^{\mathit{\alpha }}=\frac{\left({\mathit{\alpha }}^2+3\mathit{\alpha }+2\right){\mathit{\tau }}^2{\mathit{s}}^2+\left(8-2{\mathit{\alpha }}^2\right)\mathit{\tau }\mathit{s}+\left({\mathit{\alpha }}^2-3\mathit{\alpha }+2\right)}{\left({\mathit{\alpha }}^2-3\mathit{\alpha }+2\right){\mathit{\tau }}^2{\mathit{s}}^2+\left(8-2{\mathit{\alpha }}^2\right)\mathit{\tau }\mathit{s}+\left({\mathit{\alpha }}^2+3\mathit{\alpha }+2\right)}.$$

(2)

The TF of a FO-LPF of order 1 + α, where (0 < α < 1), with Butterworth characteristics and cut-off frequency ω₀ = 1/τ, is given below:

$${\mathit{H}}_{1+\mathit{\alpha }}^{\mathit{L}\mathit{P}}\left(\mathit{s}\right)=\frac{{\mathit{K}}_1}{{\left(\mathit{\tau }\mathit{s}\right)}^{1+\mathit{\alpha }}+{{\mathit{K}}_3\left(\mathit{\tau }\mathit{s}\right)}^{\mathit{\alpha }}+{\mathit{K}}_2}\mathrm{.}$$

(3)

Here, K₁, K₂, and K₃ are constants whose values are obtained through an algorithm to achieve the required filter characteristics. Using (2), the TF of the IO low-pass filter is given by the following:

$${\mathit{H}}_{1+\mathit{\alpha }}^{\mathit{L}\mathit{P}}\left(\mathit{s}\right)\cong \frac{{{\mathit{a}}_2\mathit{s}}^2+{\mathit{a}}_1\mathit{s}+{\mathit{a}}_0}{{\mathit{s}}^3+{{\mathit{b}}_2\mathit{s}}^2+{\mathit{b}}_1\mathit{s}+{\mathit{b}}_0}\mathrm{.}$$

(4)

The values of coefficients a_i (i = 0, 1, 2) and b_i (i = 0, 1, 2) in (4) are given as follows:

$${\mathit{a}}_2=\frac{1}{\mathit{\tau }}\left(\frac{{\mathit{\alpha }}^2-3\mathit{\alpha }+2}{{\mathit{\alpha }}^2+3\mathit{\alpha }+2}\right){\mathit{K}}_1,$$

(5)

$${\mathit{a}}_1=\frac{1}{{\mathit{\tau }}^2}\left(\frac{{8-2\mathit{\alpha }}^2}{{\mathit{\alpha }}^2+3\mathit{\alpha }+2}\right){\mathit{K}}_1,$$

(6)

$${\mathit{a}}_0=\frac{1}{{\mathit{\tau }}^3}{\mathit{K}}_1\mathrm{.}$$

(7)

$${\mathit{b}}_2=\frac{1}{\mathit{\tau }}\left(\frac{{({\mathit{K}}_2+{\mathit{K}}_3-2)\mathit{\alpha }}^2-3({\mathit{K}}_2-{\mathit{K}}_3)\mathit{\alpha }+(8+2{\mathit{K}}_2+{2\mathit{K}}_3)}{{\mathit{\alpha }}^2+3\mathit{\alpha }+2}\right),$$

(8)

$${\mathit{b}}_1=\frac{1}{{\mathit{\tau }}^2}\left(\frac{{({1-2\mathit{K}}_2-2{\mathit{K}}_3)\mathit{\alpha }}^2-3\mathit{\alpha }+(2+8{\mathit{K}}_2+{8\mathit{K}}_3)}{{\mathit{\alpha }}^2+3\mathit{\alpha }+2}\right),$$

(9)

$${\mathit{b}}_0=\frac{1}{{\mathit{\tau }}^3}\left(\frac{{({\mathit{K}}_2+{\mathit{K}}_3)\mathit{\alpha }}^2-3({\mathit{K}}_2-{\mathit{K}}_3)\mathit{\alpha }+2({\mathit{K}}_2+{\mathit{K}}_3)}{{\mathit{\alpha }}^2+3\mathit{\alpha }+2}\right)\mathrm{.}$$

(10)

For the filter to have Butterworth characteristics, constants K₁, K₂, and K₃ were derived by the computation of the cumulative error, and particularly, the values that resulted in the smallest cumulative band-pass error were utilized in [31]. K₁, K₂, and K₃ are given by the following expressions:

$$K_1=1,$$

(11)

$$K_2=0.2937\mathit{\alpha }+0.71216,$$

(12)

$${\mathit{K}}_3=1.068{\mathit{\alpha }}^2+0.161\mathit{\alpha }+\mathrm{0.3324.}$$

(13)

The functional block diagram (FBD) of inverse follow-the-leader feedback (IFLF) is depicted in Figure 7. It is used to realize the IO TF of (4) [3]. Analysis of this block diagram yields the following TF:

$$\frac{{\mathit{V}}_{\mathit{o}\mathit{u}\mathit{t}}}{{\mathit{V}}_{\mathit{i}\mathit{n}}}=\frac{{\mathit{s}}^2\frac{{\mathit{A}}_2}{{\mathit{\tau }}_2}+\mathit{s}\frac{{\mathit{A}}_1}{{\mathit{\tau }}_2{\mathit{\tau }}_1}+\frac{1}{{\mathit{\tau }}_2{\mathit{\tau }}_1{\mathit{\tau }}_0}}{{{\mathit{s}}^3+\mathit{s}}^2\frac{1}{{\mathit{\tau }}_2}+\mathit{s}\frac{1}{{\mathit{\tau }}_2{\mathit{\tau }}_1}+\frac{1}{{\mathit{\tau }}_2{\mathit{\tau }}_1{\mathit{\tau }}_0}}.$$

(14)

The values of forward gain (A₁, A₂), and time constants (τ₀, τ₁, and τ₂) could be computed by equating the respective coefficients in (4) and (14) while using the expressions in (5)–(13).

3.2. Proposed FO-LPF Using LV-LP VDDDA

In this sub-section, the FO-LPF of order (1 + α) is implemented using the proposed BD-VDDDA. The FBD shown in Figure 7 is implemented using VDDDA as ABB. The filter implementation is shown in Figure 8. At the z-terminal of VDDDA₁, an input voltage V_in is applied, while a scaled version of V_in is applied to the z-terminal of VDDDA₂ and VDDDA₃. These connections allow for the implementation of the forward path with gain. The output node is connected to the n-terminal of each VDDDA, implementing the feedback path. The p-terminal of VDDDA₁ is connected to the ground, while the remaining p-terminals receive the signals that have been integrated by the preceding block. The integrators used in the FBD are implemented using VDDDA₁–VDDDA₃ along with capacitors C₁ to C₃. The forward paths with gains A₁ and A₂ are implemented using PMOS common gate amplifiers M_a1 and M_b1, where A₁ = g_maR_A and A₂ = g_mbR_B. Here g_ma and g_mb are the transconductances of transistors M_a1 and M_b1, respectively, and R_A and R_B are the resistances connected at the output node of M_a and M_b, respectively. In Figure 8, the implementation using transistors M_R1–M_R2 and M_R3–M_R4 represents an active resistor R_A and R_B, which provides a resistance value controllable through external voltages V_g2 and V_g3, respectively. Thus, this implementation provides a variable resistor whose value can be adjusted according to the required forward gain by changing the external voltages. The benefit of using active resistors in place of the physical resistor is that it reduces the chip area. Transistors M_R1–M_R4 are operated in the triode region, therefore the obtained grounded resistance value can be expressed as $R_A=\frac{1}{k_n(V_{g2}-{2V}_{tn})}$ and $R_B=\frac{1}{k_n(V_{g3}-{2V}_{tn})}$ where $k_n={\mathit{\mu }}_n{C}_{ox}\left(\raisebox{1ex}{$W$}\!\left/ \!\raisebox{-1ex}{$L$}\right.\right)$, V_g2 and V_g3 are the externally applied voltages, and V_tn is the threshold voltage of the NMOS transistor. The TF of the FO-LPF depicted in Figure 8 is given by (9). Various parameters, such as the capacitances and transconductances values of the filter, can be calculated by equating respective coefficients in (4) and (15) along with using (5)–(13).

$$\frac{{\mathit{V}}_{\mathit{O}\mathit{U}\mathit{T}}}{{\mathit{V}}_{\mathit{I}\mathit{N}}}=\frac{\frac{{\mathit{s}}^2{\mathit{g}}_{\mathit{m}3}{\mathit{A}}_2}{{\mathit{C}}_3}+\frac{\mathit{s}{\mathit{g}}_{\mathit{m}2}{\mathit{g}}_{\mathit{m}3}{\mathit{A}}_1}{{\mathit{C}}_2{\mathit{C}}_3}+\frac{{\mathit{g}}_{\mathit{m}1}{\mathit{g}}_{\mathit{m}2}{\mathit{g}}_{\mathit{m}3}}{{{\mathit{C}}_1\mathit{C}}_2{\mathit{C}}_3}}{{\mathit{s}}^3+\frac{{\mathit{s}}^2{\mathit{g}}_{\mathit{m}3}}{{\mathit{C}}_3}+\frac{\mathit{s}{\mathit{g}}_{\mathit{m}2}{\mathit{g}}_{\mathit{m}3}}{{\mathit{C}}_2{\mathit{C}}_3}+\frac{{\mathit{g}}_{\mathit{m}1}{\mathit{g}}_{\mathit{m}2}{\mathit{g}}_{\mathit{m}3}}{{{\mathit{C}}_1\mathit{C}}_2{\mathit{C}}_3}}\mathrm{.}$$

(15)

3.3. Effect of Non-Idealities on FO-LPF

In this subsection, the non-ideality effect of VDDDA on the presented FO-LPF is studied. Here, two types of non-idealities are covered, i.e., non-ideality due to tracking error and parasitic. Terminal relationships in (1) are valid for the ideal VDDDA. While considering non-idealities in VDDDA, its characteristics are as follows:

$${\mathit{I}}_{\mathit{Z}}={\mathit{g}}_{\mathit{m}}\left({\mathit{\alpha }}_{\mathit{p}}{\mathit{V}}_{\mathit{V}+}-{\mathit{\alpha }}_{\mathit{n}}{\mathit{V}}_{\mathit{V}-}\right),{\mathit{V}}_{\mathit{w}}={\mathit{\beta }}_{\mathit{z}}{\mathit{V}}_{\mathit{z}}-{\mathit{\beta }}_{\mathit{n}}{\mathit{V}}_{\mathit{n}}+{\mathit{\beta }}_{\mathit{p}}{\mathit{V}}_{\mathit{p}}\mathrm{.}$$

(16)

where α_p and α_n are tracking errors in transconductance from V₊ and V₋ terminals to z terminal, respectively, β_z, β_n, and β_p, are the errors in the respective voltage gain from z, n, and p terminals, respectively to the w terminal of VDDDA. Ideally, tracking errors α_i and β_i are considered to be unity. Taking into account the above-mentioned errors, the voltage at the zc terminal of 1st VDDDA will be as follows:

$$V_{ZC1}=\frac{{{\alpha }_{p1}g}_{m1}\left({{\beta }_{Z1}V}_{in}-{{\beta }_{n1}V}_{out}\right)}{s{C}_1}$$

(17)

Similarly, the voltage at the zc terminal of 2nd VDDDA is found to be as below:

$$V_{ZC2}=\frac{{{\alpha }_{p2}g}_{m2}}{s{C}_2}\left[V_{in}\left(\frac{{{\alpha }_{p1}{\beta }_{Z1}{\beta }_{p2}g}_{m1}}{s{C}_1}+{{\beta }_{Z2}\mathrm{A}}_1\right)-V_{out}\left(\frac{{{\alpha }_{p1}{\beta }_{n1}{\beta }_{p2}g}_{m1}}{s{C}_1}+{\beta }_{n2}\right)\right]$$

(18)

The voltage at the w terminal of 3rd VDDDA is realized as the following:

$$V_{w3}=\left[V_{in}\left(\frac{{{\alpha }_{p1}{\alpha }_{p2}{\beta }_{Z1}{\beta }_{p2}{\beta }_{p3}g}_{m1}{g}_{m2}}{s^2{C}_1{C}_2}+\frac{{{\alpha }_{p2}g}_{m2}{{\beta }_{p3}\beta }_{Z2}{\mathrm{A}}_1}{s{C}_2}+{{\beta }_{Z3}\mathrm{A}}_2\right)-V_{out}\left(\frac{{{\alpha }_{p1}{\alpha }_{p2}{\beta }_{n1}{\beta }_{p2}{\beta }_{p3}g}_{m1}{g}_{m2}}{s^2{C}_1{C}_2}+\frac{{{\alpha }_{p2}\beta }_{n2}{\beta }_{p3}{g}_{m2}}{s{C}_2}+{\beta }_{n3}\right)\right]$$

(19)

V_out, which is the voltage developed at the zc terminal of 3rd VDDDA will be as follows:

$$V_{out}=\frac{{\alpha }_{p3}{g}_{m3}{V}_{w3}}{s{C}_3}$$

(20)

After putting the value of V_w3 in (20) and solving the equation, the TF of the filter under the parasitic effect is given by the following:

$$\frac{{\mathit{V}}_{\mathit{O}\mathit{U}\mathit{T}}}{{\mathit{V}}_{\mathit{I}\mathit{N}}}=\frac{{\mathit{s}}^2{\mathit{\beta }}_{\mathit{z}3}{\mathit{X}}_1{\mathit{A}}_2+\mathit{s}{\mathit{\beta }}_{\mathit{z}2}{\mathit{X}}_1{\mathit{Y}}_1{\mathit{A}}_1+{\mathit{\beta }}_{\mathit{z}1}{\mathit{X}}_1{\mathit{Y}}_1{\mathit{Z}}_1}{{\mathit{s}}^3+{\mathit{s}}^2{\mathit{\beta }}_{\mathit{n}3}{\mathit{X}}_1+\mathit{s}{\mathit{\beta }}_{\mathit{n}2}{\mathit{X}}_1{\mathit{Y}}_1+{\mathit{\beta }}_{\mathit{n}1}{\mathit{X}}_1{\mathit{Y}}_1{\mathit{Z}}_1}\mathrm{.}$$

(21)

where, α_pi, β_zi, β_pi and β_ni (i = 1, 2, 3) are the errors of the i^th block, $X_1=\frac{{\alpha }_{p3}{g}_{m3}}{C_3}$, $Y_1=\frac{{\alpha }_{p2}{\beta }_{p3}{g}_{m2}}{C_2}$ and $Z_1=\frac{{\alpha }_{p1}{\beta }_{p2}{g}_{m1}}{C_1}$. Transconductance error between V₊ and z terminal and voltage gain errors between z, n, p to w terminal will affect the magnitude and phase response of the filter. The shift in pole frequency and slope value in the transition band will also be observed.

Considering the effect of parasitic impedances of VDDDA, the corresponding circuit is presented in Figure 9. The high impedance terminals V₊, V₋, n, p, and z of VDDDA exhibit parasitic impedance in the form of shunt-connected resistances and capacitances, and at w terminal, a series resistance (R_w) is present. When considering these parasitic impedances, $C_{T1}=C_1\Vert C_{ZC1}\Vert C_{p2}$, $C_{T2}=C_2\Vert C_{ZC2}\Vert C_{p3}$, $C_{T3}=C_3\Vert C_{ZC3}\Vert C_{n3}\Vert C_{n2}\Vert C_{n1}$, $G_1=G_{ZC1}+G_{p2}$, ${G_2=G_{ZC2}+G_{p3}{,G}_3=G_{ZC3}+G_{n1}+G_{n2}+G_{n3},G}_{ZC1}=\raisebox{1ex}{$1$}\!\left/ \!\raisebox{-1ex}{$R_{ZC1}$}\right.$, $G_{Z2}=\raisebox{1ex}{$1$}\!\left/ \!\raisebox{-1ex}{$R_{ZC2}$}\right.,G_{p2}=\raisebox{1ex}{$1$}\!\left/ \!\raisebox{-1ex}{$R_{p2}$}\right.$, $G_{p3}=\raisebox{1ex}{$1$}\!\left/ \!\raisebox{-1ex}{$R_{p3}$}\right.$, $G_{n1}=\raisebox{1ex}{$1$}\!\left/ \!\raisebox{-1ex}{$R_{n1}$}\right.$, $G_{n2}=\raisebox{1ex}{$1$}\!\left/ \!\raisebox{-1ex}{$R_{n2}$}\right.$, and $G_{n3}=\raisebox{1ex}{$1$}\!\left/ \!\raisebox{-1ex}{$R_{n3}$}\right.$. Also, assuming $A_2^{*}=\raisebox{1ex}{$g_{mB}$}\!\left/ \!\raisebox{-1ex}{$Z_B$}\right.$ and $A_1^{*}=\raisebox{1ex}{$g_{mA}$}\!\left/ \!\raisebox{-1ex}{$Z_A$}\right.$ where $Z_B=G_B+G_{Z2}$, $Z_A=G_A+G_{Z3}$, $G_B=\raisebox{1ex}{$1$}\!\left/ \!\raisebox{-1ex}{$R_B$}\right.$, $G_A=\raisebox{1ex}{$1$}\!\left/ \!\raisebox{-1ex}{$R_A$}\right.$, $G_{Z2}=\raisebox{1ex}{$1$}\!\left/ \!\raisebox{-1ex}{$R_{Z2}$}\right.$ and $G_{Z3}=\raisebox{1ex}{$1$}\!\left/ \!\raisebox{-1ex}{$R_{Z3}$}\right.$. After analyzing the circuit, the voltage at the zc terminal of 1st VDDDA will be as follows:

$$V_{ZC1}=\frac{g_{m1}\left(V_{in}-V_{out}\right)}{s{C}_{T1}+G_1}$$

(22)

Similarly, the voltage at the zc terminal of 2nd VDDDA is found to be as below:

$$V_{ZC2}=\frac{g_{m2}}{s{C}_{T2}+G_2}\left[V_{in}\left(\frac{g_{m1}}{s{C}_{T1}+G_1}+A_1^{*}\right)-V_{out}\left(\frac{g_{m1}}{s{C}_{T1}+G_1}+1\right)\right]$$

(23)

The voltage at the w terminal of 3rd VDDDA is realized as below:

$$V_{w3}=\left[V_{in}\left(\frac{g_{m1}{g}_{m2}}{\left(s{C}_{T1}+G_1\right)\left(s{C}_{T2}+G_2\right)}+\frac{A_1^{*}{g}_{m2}}{\left(s{C}_{T2}+G_2\right)}+A_2^{*}\right)-V_{out}\left(\frac{g_{m1}{g}_{m2}}{\left(s{C}_{T1}+G_1\right)\left(s{C}_{T2}+G_2\right)}+\frac{g_{m2}}{\left(s{C}_{T2}+G_2\right)}+1\right)\right]$$

(24)

V_out, which is the voltage developed at the zc terminal of 3rd VDDDA will be the following:

$$V_{out}=\frac{g_{m3}{V}_{w3}}{s{C}_{T3}+G_3}$$

(25)

After putting the value of V_w3 in (25) and solving the equation, the TF of the filter under the parasitic effect is given by the following:

$$\frac{{\mathit{V}}_{\mathit{O}\mathit{U}\mathit{T}}}{{\mathit{V}}_{\mathit{I}\mathit{N}}}=\frac{{\mathit{s}}^2\mathit{A}{\mathit{A}}_2^{\mathit{*}}+\mathit{s}\left(\mathit{A}\mathit{B}{\mathit{A}}_1^{\mathit{*}}+\mathit{A}\mathit{C}{\mathit{A}}_2^{\mathit{*}}+{\mathit{A}\mathit{D}\mathit{A}}_2^{\mathit{*}}\right)+\left({\mathit{G}}_{\mathit{M}}{\mathit{C}}_{\mathit{T}}+\mathit{A}\mathit{B}{\mathit{C}\mathit{A}}_1^{\mathit{*}}+\mathit{A}\mathit{C}\mathit{D}{\mathit{A}}_2^{\mathit{*}}\right)}{{\mathit{s}}^3+{\mathit{s}}^2\left(\begin{array}{c}\mathit{A}+\mathit{C}+\\ \mathit{D}+\mathit{E}\end{array}\right)+\mathit{s}\left(\begin{array}{c}\mathit{A}\mathit{B}+\mathit{A}\mathit{C}+\mathit{A}\mathit{D}\\ +\mathit{C}\mathit{D}+\mathit{C}\mathit{E}+\mathit{D}\mathit{E}\end{array}\right)+\left(\begin{array}{c}{\mathit{G}}_{\mathit{M}}{\mathit{C}}_{\mathit{T}}+\mathit{A}\mathit{B}\mathit{C}\\ +\mathit{A}\mathit{C}\mathit{D}+\mathit{C}\mathit{D}\mathit{E}\end{array}\right)},$$

(26)

where $A=\frac{g_{m3}}{C_{T3}}$, $B=\frac{g_{m2}}{C_{T2}}$, $C=\frac{G_1}{C_{T1}}$, $D=\frac{G_2}{C_{T2}},E=\frac{G_3}{C_{T3}},$   $G_M=g_{m1}{g}_{m2}{g}_{m3}$, and $C_T=\frac{1}{C_{T1}{C}_{T2}{C}_{T3}}$. When considering the parasitic model of VDDDA in the proposed filter, parasitic capacitances and resistances present at the terminals where a passive element is connected should be considered and may affect the magnitude and phase response of the filter at high frequency. These parasitics will also cause a shift in pole frequency and slightly change the slope value in the transition band. Nevertheless, the impact of the parasitic capacitances could be decreased by adjusting the magnitude of C₁ >> C_ZC1 & C_p2, C₂ >> C_ZC2 & C_p3, C₃ >> C_ZC2, C_n3, C_n2, & C_n1, R_A >> R_Z2 and R_B >> R_Z3.

3.4. Simulation Results

The proposed LP FO-LPF of order (1 + α), as shown in Figure 8, is simulated in the Cadence Virtuoso design tool using a 0.18 μm TSMC process parameter. The supply voltage used for filter simulation is, V_DD = −V_SS = 300 mV, and V_B is kept at −250 mV. The layout of the proposed LV-LP fractional-order LPF circuit is shown in Figure 10. It covers an overall area of 36,600 μm² (200.38 μm × 183.79 μm). Note that the MOS capacitor occupies a significant area in the layout. The proposed filter offers electronic tuning of its order and pole frequency by adjusting the bias current of the three VDDDAs used. Also, this electronic tuning of order and pole frequency is independent of each other. For changing the order of the filter, it is necessary to adjust the parameter α. All the parameters, such as forward gain (A₁, A₂), and time constants (τ₀, τ₁, and τ₂) are dependent on the value of α. Consequently, all the transconductance values are also reliant on α. So, in order to obtain the desired transconductance value for each individual order, it is necessary to establish a distinct bias current for each VDDDA block as well as it is also necessary to change the value of resistors connected in the forward path. Figure 11 demonstrates the pre-layout and post-layout magnitude and phase response of the proposed filter, which highlights the tunability of the filter’s order. The values of capacitances, resistances, transconductances, and corresponding bias currents for different filter orders are summarized in

Table 2. Parameter values for different values of orders for f₀ = 1 kHz.

Order of Filter	1.3	1.5	1.7	1.9
C1 [pF]	90	90	90	90
C2 [pF]	90	90	90	90
C3 [pF]	30	30	30	30
RA [kΩ]	2	1.67	1	0.5
RB [kΩ]	4.6	4	3.4	2.8
gm1 [nS]	150	172	190	210
gm2 [nS]	619	650	652	607
gm3 [nS]	643	537	485	475
Ib1 (nA)	12.3	12.5	12.9	14.5
Ib2 (nA)	72	74	74.1	65
Ib3 (nA)	75	53	47	46

. The bias current values are set accordingly to obtain the simulation results in Figure 11. The pole frequency selected for the simulation is 1 kHz. In Figure 11, it is evident that the attenuation in the stopband changes according to −20 × (1 + α) dB/dec, where (1 + α) is the order of the proposed filter. In

Table 3. Theoretical and simulated slope of attenuation for different values of orders for f₀ = 1 kHz.

Order of Filter	Slope of Attenuation [dB/dec]
	Theoretical	Simulated
1.3	26	26.04
1.5	30	30.57
1.7	34	33.64
1.9	38	37.61

, the attenuation obtained by simulation and theoretical calculation is compared for different orders. From Table 3, it is clear that the simulated result closely follows the theoretical values obtained mathematically. Also, the power consumption of the proposed FO-LPF is only 663 nW, which makes the proposed filter design suitable for the low-power application.

Figure 12 illustrates the magnitude and phase response of a FO-LPF for orders 1.3 and 1.7. The graphs provide a comparative analysis between the simulation results and the exact curves, as determined by (3). The resemblance between the simulated result and the exact curves is evident. The suggested filter design allows for the adjustment of the pole frequency without changing the filter’s order. This can be accomplished by modifying the transconductances of the VDDDAs that implement the integrators, while maintaining the forward current gain values as the same. In order to achieve tunability, the filter’s selected order is set to 1.5. The capacitance values, as well as the g_m4 and g_m5 parameters, remain unchanged from those specified in Table 2 for the purpose of this simulation.

Table 4. Parameter values for different values of frequencies with order 1.5.

Pole Frequency	500 Hz	1 kHz	2 kHz
C1 [pF]	90	90	90
C2 [pF]	90	90	90
C3 [pF]	30	30	30
RA [kΩ]	1.67	1.67	1.67
RB [kΩ]	4	4	4
gm1 [S]	85.8 n	172 n	343 n
gm2 [S]	325 n	650 n	1.3 μ
gm3 [S]	269 n	537 n	1.07 μ
Ib1 (nA)	5	12.5	29
Ib2 (nA)	26	74	150
Ib3 (nA)	20	53	145

provides a compilation of transconductances and biasing currents that were used. The simulated pre-layout and post-layout magnitude and phase response of the proposed filter showing the tunability feature for order 1.5 are shown in Figure 13. The theoretical pole frequencies chosen to illustrate the controllability are 500 Hz, 1 kHz, and 2 kHz. Pole frequency values obtained by post-layout simulations are 502 Hz, 1.003 kHz, and 2.007 kHz, which confirm the workability of the proposed design, as summarized in

Table 5. Theoretical and post-layout simulated pole frequency values for order 1.5.

Theoretical Pole Frequency	Simulated Pole Frequency
500 Hz	502 Hz
1 kHz	1.003 kHz
2 kHz	2.007 kHz

.

The output noise of the FO-LPF is plotted in Figure 14. The pre-layout and post-layout noise of FOF is found to be 691 nV/$\surd \mathrm{Hz}$ and 767 nV/$\surd \mathrm{Hz}$ at 10 Hz, and after that, it observes an exponential decay and decreases to a value of 134 nV/$\surd \mathrm{Hz}$ and 186 nV/$\surd \mathrm{Hz}$ at 1 kHz for pre-layout and post-layout respectively. The linear performance of the FOF for orders 1.5 and 1.7 was tested by an input signal of a single tone at 100 Hz with variable amplitude. The total harmonic distortion (THD) results are displayed in Figure 15. It is apparent that up to 250 mV of input amplitude, the THD value is below 4%, which is quite low. In Figure 16, the time domain response of FO-LPF is presented for voltage signals having amplitude of 200 mV and frequency of 100 Hz.

Transistor corners as SS, TT, and FF, voltage supply corners as ±10% of V_DD, and temperature corners as −40 °C, 0 °C, 27 °C, and 80 °C were used in the analysis of process, voltage and temperature (PVT) corners. Figure 17, Figure 18 and Figure 19 display the outcomes of the proposed filter’s magnitude characteristics with process, voltage, and temperature corner analysis, respectively. From Figure 17, it is clear that as anticipated, the response of the process corner exhibits limited variation. Based on the magnitude curve illustrated in Figure 18, it can be inferred that the FO-LPF design does not exhibit significant variations across different temperatures. Thus, the proposed circuit demonstrates satisfactory performance throughout a broad spectrum of temperature variations. From Figure 19, FO-LPF characteristics are satisfactory for up to 10% variation in V_DD. Through the use of the Monte-Carlo analysis for N = 600 samples, the sensitivity of the pole frequency with regard to the impact of transistor mismatching and process parameter fluctuations was assessed. The magnitude characteristics and statistical plots, obtained at α = 0.5, are shown in Figure 20. The standard deviation of the pole frequency is 12.94 Hz. Given that the desired pole frequency value is 1 kHz, it is possible to draw the conclusion that the filter has acceptable sensitivity characteristics.

The transfer function given in (21) represents filter characteristics when the filter is affected by tracking-error parameters. To observe the effect to these parameters, the sensitivity analysis was performed for the obtained transfer function in (21), with respect to the tracking-error parameters. The objective of sensitivity analysis is to assess the impact of changes in these parameters on the performance of the filter. The given expression comprises a total of eleven tracking-error parameters that are α_p1, α_p2, α_p3, β_z1, β_z2, β_z3, β_n1, β_n2, β_n3, β_p2, and β_p3. Through simulation, there values were obtained as follows: α_p = 0.98, β_z = 0.99, β_n = 1.003, β_p = 0.92. Generally speaking, the relative sensitivity to each parameter is characterized as follows:

$$S_x^{TF}=\frac{x}{TF}\frac{dTF}{dx}$$

(27)

where, TF represents the transfer function of the filter and x represents the parameter that affects this transfer function. This analysis was conducted for order 1.5 at f₀ = 1 kHz. The remaining parameter values, such as capacitance, resistance, and transconductance are presented in Table 2. The sensitivity obtained for these tracking-error parameters were a function of parameter values and frequency and thus the magnitude of sensitivity versus frequency curve, in terms of the aforementioned tracking-error parameters, is depicted in Figure 21. The graph demonstrates the variation in sensitivity as a function of frequency and parameters β_n1, and β_z1 show highest sensitivity in the pass band range of FO-LPF.

To demonstrate the practical significance of the proposed circuit, an assessment of the filter’s efficiency in processing the electrocardiogram (ECG) signal is performed. The input ECG signal exhibits an amplitude of 25 mV, and it was mixed with a sinusoidal signal of 1 kHz frequency and an amplitude of 50 μV. The noisy ECG signal was passed through the FO-LPF of pole frequency 2 kHz. Figure 22 displays the actual ECG, the ECG with added noise, and the ECG that was restored after passing through the filter. This demonstrates that the suggested filter is well-suited for practical applications such as ECG filtering.

4. Comparison

Given that the integer-order approximation technique is utilized for designing FO-LPF, the state-of-the-art in

Table 6. Relative studies of the proposed FO-LPF with fractional filters available in the literature.

[Ref.] (Year)	Type (Number) of ABB Used	Function Realized	No. of Passive Elements (R, C)	Grounded/Floating Elements	Supply Voltage	Electronic Tunability	Use of LV-LP Technique	Total Power Dissipation (W)
[6] (2016)	CCII (4), DDCC (1)	LPF	7, 3	G	NA	No	No	NA
[14] (2011)	OPAMP (2)	LPF	10, 3	F	NA	No	No	NA
[15] (2018)	CFOA (4)	LPF	9, 3	F	±10 V	No	No	NA
[16] (2016)	CFOA (4)	LPF	10, 3	F	±10 V	No	No	NA
[17] (2018)	OTA (3), MOCF (1), ACF (2)	LPF	0, 3	G	±1 V	Yes	No	NA
[18] (2017)	OTA (3), CF (1), ACA (3)	LPF	0, 3	G	NA	Yes	No	NA
[19] (2016)	DDCC (5)	LPF	7, 3	G	±0.5 V	No	Yes	0.185 m
[20] (2020)	CDBA (5)	LPF, BPF	11, 3	F	±10 V	No	No	NA
[21] (2017)	UVC (4)	LPF	10, 3	F	NA	No	No	NA
[32] (2018)	MOCF (2), DOCF (1), ACA (5)	LPF	3, 3	F	NA	Yes	No	NA
[33] (2017)	ACA (5), FD-CF (3)	LPF	6, 3	F	NA	Yes	No	NA
[34] (2019)	OTA (8), CF (1)	LPF, HPF, BPF, BRF	0, 3	G	±0.75 V	Yes	No	8.74 μ
[35] (2021)	OTA (6), CF (3), ACA (1)	LPF	0, 1 *	G	±1.65 V	No	No	72.6 m
[36] (2022)	CDBA (4)	APF	11, 3	F	NA	Yes	No	NA
[37] (2023)	CFTA (5)	LPF	2, 3	G	±0.9 V	Yes	No	6.8 m
Proposed	VDDDA (3), MOS (6)	LPF	0, 3	G	±0.3 V	Yes	Yes	663 n

* Uses 5 fractional-order capacitors.

incorporates FOFs that are designed using the same approximation technique. While comparing the proposed FOF with other FOFs available in the literature, several observations were made as outlined below.

The table reveals that the number of active blocks employed in the references [6,15,16,17,18,19,20,21,32,33,34,35,36,37] exceeds the number of blocks utilized in the proposed FOF. Additionally, the implementation of the FOF in [6,14,15,16,19,20,21,32,33,36,37] involves the utilization of a significant quantity of resistors. It is worth noting that the majority of these resistors are floating. Conversely, the proposed FOF incorporates a grounded active resistor that is implemented using MOSFET, making the design well-suited for the fabrication process. In addition, it should be noted that the designs, with the exception of the ones referenced as [17,18,32,33,34,36,37], do not offer tunability of order and pole frequency.

Regarding the utilization of passive components, it is seen that only [17,18,34,35] exhibit an equivalent or lesser quantity of passive components compared to the design under consideration. However, upon analysing the number of active components, it is evident that [17,18,34,35] exhibit a significantly greater number of active components in comparison to the proposed design. Additionally, the design of [35] incorporates the utilization of five fractional capacitors (FC). The functions performed by [20,34,36] encompass LPF along with additional functionalities. However, [20] employs floating passive components and lacks electronic tuning capabilities. On the other hand, [34] utilizes a significant number of active components, operates at a higher supply voltage, and exhibits high power dissipation. Ref. [36] employs floating passive components and incorporates five FCs in its design. The DC supply voltage employed for the operation of the suggested filter circuit is ±300 mV, which is the smallest value when compared to the other designs. It is comparable only to [19], where the supply voltage is ±0.5 V. However, it should be noted that [19] utilizes resistors in the implementation of the filter. The LV-LP methodology is utilized in the filter implementation only in [19] and the proposed method. Consequently, none of the other circuits can be considered suitable for operation in the LV-LP domain. Furthermore, the power consumption of the suggested circuit is the lowest among the designs that were studied.

Thus, the proposed circuit is beneficial in terms of its use of only three active building blocks, six MOS transistors, and three grounded capacitors for implementing fractional-order LPF, which is suitable for its operation in the LV-LP domain since it uses only ±300 mV as its power supply and consumes only 663 nW. The proposed filter offers electronic and independent order and pole frequency tuning. Furthermore, this is the only circuit apart from [19] to be used in the low-voltage and low-power domain.

5. Conclusions

In this paper, a VDDDA and a low-pass fractional-order filter structure capable of operating at low voltage and in low-power applications were presented. The VDDDA structure is implemented using the bulk-driven metal oxide semiconductor (BD-MOS) transistor technique and is operated in the subthreshold region. VDDDA uses V_DD = −V_SS = 300 mV and dissipates only 207 nW of power for its operation. Furthermore, this block is used to implement a FO-LPF of order (1 + α). The filter structure comprises three VDDDAs, three grounded capacitors, and two active resistors. Also, the electronic tuning feature of the proposed filter design offers independent tuning of its order and frequency through the bias current of the active component used. The effects of tracking errors and parasitics on the performance of the proposed FO-LPF were analyzed. This filter is capable of LV-LP operation because it is operated at ±300 mV and dissipates only 663 nW of power. The layout of the proposed VDDDA, as well as the FO-LPF, were laid out in a Cadence environment using 0.18 μm CMOS technology parameters and covered a chip area of 1208 μm² and 36,600 μm², respectively. Post-layout simulation results are also included, which imply that they are suitable for fabrication. Noise, total harmonic distortion, Monte-Carlo and PVT analyses were also performed.