A Piecewise Linear Approach for Implementing Fractional-Order Multi-Scroll Chaotic Systems on ARMs and FPGAs
Abstract
:1. Introduction
- Extra-degree of fredom. The most significant advantage of fractional-order systems is the extra degree of freedom provided by the non-integer order derivatives. This additional parameter allows for greater flexibility in modeling and control. In applications such as chaos synchronization, it is possible to tune and optimize the system behavior by varying the fractional order, thereby achieving precise synchronization schemes and control outcomes [18].
- Memory Properties and Hereditary Characteristics. Fractional-order systems possess memory properties and hereditary characteristics, which are absent in integer-order systems. These properties enhance the modeling of systems with memory effects and improve the effectiveness of chaos-based applications. For instance, the memory effects can introduce additional layers of complexity and unpredictability to the chaotic behavior, which can be used to create robust security applications [19,20].
- Larger Key-space. Fractional-order chaotic systems offer a significantly larger keyspace compared to integer-order systems due to the additional degrees of freedom provided by the fractional derivatives [21].
- Piecewise linear (PWL) functions. The reported digital implementations are predominantly based on fractional-order systems with quadratic functions, cubic functions, or quadratic cross-product functions. This could be caused because determining Adomian polynomials of complex functions is challenging [73]. Even when there are approaches to efficiently compute the Adomian polynomials of trigonometric, exponential, and logarithmic functions [59,74]; and improved ADM versions [75,76,77,78]; they still cannot represent PWL functions.
- Multi-scroll chaotic attractors. The informed physical implementations of chaotic systems using ADM are mostly confined to one-and two-scroll attractors. Indeed, the classical ADM does not cope with PWL functions, which are a fundamental mechanism to get multi-scroll chaotic attractors [79,80,81,82,83]. Thus, a relevant open problem is how to incorporate fractional-order dynamical systems based on PWL functions in the sense of ADM.
2. Background
3. Proposed Piecewise Linear Decomposition Method (PWL-DM Approach)
- is repeated once.
- is repeated times.
Convergence Analysis
4. Illustrative Example
4.1. Example 1: Step-by-Step Demonstration for a 2-scroll PWL Chaotic System
- Using PWL-DM
4.2. Example 2: 1D Multiscroll PWL Chaotic System
- Using PWL-DM
4.3. Example 3: 2D Grid Multi-Scroll PWL Chaotic System
- Using PWL-DM
5. Physical Implementation of the PWL-DM Based on FPGA and ARM Digital Boards
5.1. Non-Embedded Design: PWL-DM Implementation Based on FPGA
- Chaotic Oscillator Unit: The elements of the FPGA implementation for the , and scrolls are marked in color red. The highest level of the FPGA design for the and -scrolls (see Figure 7) comprises two blocks, whereas the -scrolls (see Figure 8) contains three blocks, each one performs calculations separately. The PWL blocks that describe the PWL function (Equations (28), (51) and (65)) are shown in Figure 9. Finally, the ADM_description block executes the proposed PWL-DM (20).
- Digital/Analog conversion: For visualization of the chaotic attractors on an oscilloscope, the Post_processing and dac_hdr blocks (blue square in Figure 7 and Figure 8), control the 12-bit dual-channel D/A converter MCP4922 at 20 MHz. It is worth remembering that both blocks may be deleted in practical applications, i.e., they should not be considered as part of the final implementation since they are just used for visualization purposes.
- 1D 2-scrolls generation mechanism
- Signal Comparison. The signal is compared against the predefined regions , and .
- Multiplexer (MUX). Based on the comparison results, the MUX selects appropriate values for the parameters and .
- PWL-DM Description. The parameters and are fed into the ADM_description block, which uses a Finite State Machine (FSM) that transitions from state to state . Each state processes parallel calculations corresponding to a set of coefficients . In state , the calculation results of the coefficients are used to calculate the solution of the system and hence to generate a 2-scroll chaotic attractor.
- 1D 4-scrolls generation mechanism
- Extended Signal Comparison. The signal is compared against more regions, from to , to determine which parameters to use.
- Expanded MUX. The MUX block is expanded to handle the additional regions and selects appropriate parameters , for generating a 4-scroll chaotic attractor.
- PWL-DM Description: Similar to the previous implementation, the FSM within the ADM Description block, transitions from the state to the state , ensuring that the correct are properly computed in each state, resulting in the generation of a 4-scrolls chaotic attractor.
- 2D-grid scrolls chaotic attractor generation mechanism
- Dual Signal Comparison: Signals and are each compared against their respective regions, and , .
- Separate MUX Units: Each signal has its own MUX unit, which selects the parameters for and for .
- Integrated PWL-DM Description: The outputs of the two MUX units are fed into a single ADM_description block, which combines the parameters and processes them using an FSM. The FSM inside this block handles the transition from state to state . It ensures that the combination of and produces the desired 2D 4-scroll chaotic attractor. Consequently, the calculations in this implementation are relatively more complex compared to the previous two.
5.2. Embedded Design: PWL-DM Implementation Realized on an ARM Platform
- Device configuration. The ARM-based design illustrated in Figure 13 is elaborated in the Xilinx Vivado Design Suite, version 2016.4. This block contains the ZYNQ7 Processing System IP, which is the software interface around the Processing System (PS) of the Xilinx Zynq-7000 board, currently working at 667 MHz. For including the data converter, a functional interface for communicating the PS with the PL of the Xilinx Zynq-7000 board, operating at 100 MHz, was designed (Figure 14). This interface comprises a Processor System Reset IP, an AXI Interconnect IP, and two AXI GPIO IPs. Later, the dac_hdr_v1_0 is a custom IP for controlling the MCP4922 D/A converter at 20 MHz.
- Calculation Preparation. From now on, the Xilinx Software Development Kit (XSDK), version 2016.4, will be used for the configuration of the PS of the Xilinx Zynq-7000 board in C programming language by using a single-precision (32-bits) floating-point format. The Algorithm 1 shows the pseudo-code for implementing the PWL-DM on an ARM digital platform.
6. Discussion
Algorithm 1: Pseudocode for implementing the PWL-DM for 2-scrolls (50), 4-scroll (63) and -grid scroll (71) chaotic attractors on an ARM platform. |
7. Conclusions
Author Contributions
Funding
Data Availability Statement
Acknowledgments
Conflicts of Interest
Abbreviations
Acronym | Description |
IoT | Internet of Things |
RNG | Random Number Generator |
ANN | Artificial Neural Network |
FDA | Frequency-Domain Approximations |
GL | Grünwald-Letnikov |
ABM | Adams-Bashforth-Moulton |
ADM | Adomian Decomposition Method |
PWL | Piecewise Linear |
PWL-DM | Piecewise Linear Decomposition Method |
ARM | Advanced RISC Machine |
RISC | Reduced Instruction Set Computer |
FPGA | Field-Programmable Gate Array |
CORDIC | coordinate Rotation Digital Computer |
VHDL | VHSIC Hardware Description Language |
DSP | Digital Signal Processor |
PL | Programmable Logic |
PS | Processing System |
IP | Intellectual Property |
RTL | Register Transfer Level |
MAE | Mean Absolute Error |
ECO | Expected Convergence Order |
TR | Trapezoidal rule |
NGF | Newton–Gregory formula |
FBDF | Fractional Backward Differentiation Formula |
Symbol | Description |
Gamma function | |
Riemann-Liouville fractional integral operator of order q | |
Caputo fractional derivative of order q | |
Finite partition of the phase space | |
Domains in the phase space partition, | |
Number of domains in the phase space partition | |
Subdomains generated by the function | |
Surfaces specifying the boundaries between consecutive subdomains | |
Values specifying the boundaries between subdomains in | |
Piecewise vector in the system definition | |
Slope and intercept of the piecewise linear functions | |
Matrices composed of the slopes and intercepts of the PWL functions | |
Number of piecewise linear (PWL) functions | |
Element of the decomposition series | |
Initial conditions vector | |
ADM Coefficients | |
Number of terms in the approximate solution |
Appendix A
Sub-Domain | ||
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, , , | , , | , , |
, , | , , | |
, , | , , | |
, , | , , | |
, , | , , | |
, , | , , | |
, | , , | , , |
Sub-Domain | ||
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, | , , | , , |
, | ||
, | ||
, | ||
, | ||
, | ||
, | ||
, | ||
, , | , , | |
, , | ||
, , | ||
, , | ||
, , | ||
, , | , , | |
Sub-Domain | ||
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, , | , , | |
, , | , , | |
, , | , , | |
Sub-Domain | ||
---|---|---|
, , | , , | |
, , | , , | |
, , | , , | |
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Fractional Order | Step Size | MAE | ECO |
---|---|---|---|
2−Terms | ||||
3−Terms | ||||
4−Terms | ||||
5−Terms |
FPGA Implementation | ||||
---|---|---|---|---|
Hardware | Available | 2-scrolls | 4-scrolls | -Grid Scrolls |
LUT | 53,200 | 1469 (2.75%) | 1588 (2.98%) | 2330 (4.38%) |
FF | 106,400 | 1155 (1.08%) | 1123 (1.06%) | 1170 (1.10%) |
DSP | 220 | 4 (1.82%) | 4 (1.82%) | 12 (5.45%) |
BRAM | 140 | 0 (0%) | 0 (0%) | 0 (0%) |
IO | 200 | 98 (49.0%) | 98 (49.0%) | 98 (49.0%) |
BUFG | 32 | 1 (3.13%) | 1 (3.13%) | 1 (3.13%) |
ARM implementation | ||||
Hardware | Available | 2-scrolls, 4-scrolls, -grid scrolls | ||
LUT | 53,200 | 676 (1.27%) | ||
FF | 106,400 | 62 (0.36%) | ||
DSP | 220 | 879 (0.83%) | ||
IO | 200 | 5 (2.50%) | ||
BUFG | 32 | 1 (3.13%) |
FPGA Implementation | Clock Frequency (MHz) | Throughput (Gbit/s) |
---|---|---|
2-scrolls | 110.238 | 3.527 |
4-scrolls | 103.627 | 3.316 |
-grid scrolls | 91.106 | 2.915 |
Algorithm | Integration Step-Size, h | Simulation Time | No. of Iterations | Computation Time |
---|---|---|---|---|
ABM [45] | 0.01 | 2000 s | 133,333 | 2809.19 s |
Short-memory GL [54,97], p. 19 | 0.01 | 2000 s | 133,333 | 12.91 s |
PWL-DM (This work) | 0.01 | 2000 s | 133,333 | 0.88 s |
Resource | Available | PWL-DM (This Work) | Short-Memory GL (Design Guidelines in Ref. [40]) |
---|---|---|---|
LUT | 53,200 | 1469 (2.75%) | 3197 (6.01%) |
FF | 106,400 | 1155 (1.08%) | 838 (0.79%) |
DSP | 220 | 4 (1.82%) | 20 (9.09%) |
BRAM | 140 | 0 (0%) | 1.5 (1.07%) |
IO | 200 | 98 (49%) | 98 (49%) |
BUFG | 32 | 1 (3.13%) | 1 (3.13%) |
Item | Tang System (Short-Memory GL) | Özoguz System (Short-Memory GL) | Yalcin System (Short-Memory GL) | Lü System in Equation (27) (Short-Memory GL) | V-Shape System (Short-Memory GL) | Lü System in Equation (27) (PWL-DM) |
---|---|---|---|---|---|---|
Nonlinearity | PWL function | PWL function | PWL function | PWL function | PWL function | PWL function |
Attractor | 1D multi-scroll | 1D multi-scroll | 1D multi-scroll | 1D multi-scroll | 1D multi-scroll | 1D multi-scroll |
LUT | 3339 | 3856 | 2125 | – | – | 1588 |
FF | 1763 | 2597 | 1932 | – | – | 1123 |
DSP | 134 | 194 | 132 | – | 59 | 4 |
BRAM | 0 | 0 | 0 | 3 | 0 | 0 |
Max. Clock (MHz) | 67.378 | 42.052 | 94.941 | 84.34 | 73.049 | 103.627 |
Throughput (Gb/s) | 2.156 | 1.345 | 3.038 | 2.69 | 2.921 | 3.316 |
FPGA chip & Design suite | Artix-7 ISE 14.5 | Artix-7 ISE 14.5 | Artix-7 ISE 14.5 | Cyclone IV-GX Quartus | Virtex-5 ISE 14.5 | Artix-7 Vivado 2016.4 |
Ref. | [21] | [21] | [21] | [98] | [57] | This work |
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Clemente-López, D.; Munoz-Pacheco, J.M.; Zambrano-Serrano, E.; Félix Beltrán, O.G.; Rangel-Magdaleno, J.d.J. A Piecewise Linear Approach for Implementing Fractional-Order Multi-Scroll Chaotic Systems on ARMs and FPGAs. Fractal Fract. 2024, 8, 389. https://doi.org/10.3390/fractalfract8070389
Clemente-López D, Munoz-Pacheco JM, Zambrano-Serrano E, Félix Beltrán OG, Rangel-Magdaleno JdJ. A Piecewise Linear Approach for Implementing Fractional-Order Multi-Scroll Chaotic Systems on ARMs and FPGAs. Fractal and Fractional. 2024; 8(7):389. https://doi.org/10.3390/fractalfract8070389
Chicago/Turabian StyleClemente-López, Daniel, Jesus M. Munoz-Pacheco, Ernesto Zambrano-Serrano, Olga G. Félix Beltrán, and Jose de Jesus Rangel-Magdaleno. 2024. "A Piecewise Linear Approach for Implementing Fractional-Order Multi-Scroll Chaotic Systems on ARMs and FPGAs" Fractal and Fractional 8, no. 7: 389. https://doi.org/10.3390/fractalfract8070389
APA StyleClemente-López, D., Munoz-Pacheco, J. M., Zambrano-Serrano, E., Félix Beltrán, O. G., & Rangel-Magdaleno, J. d. J. (2024). A Piecewise Linear Approach for Implementing Fractional-Order Multi-Scroll Chaotic Systems on ARMs and FPGAs. Fractal and Fractional, 8(7), 389. https://doi.org/10.3390/fractalfract8070389