1. Introduction
Visual impairment is a sensory challenge with a significant impact on the daily life of patients. Nearly 216 million people worldwide are visually impaired, of which 36 million are currently blind [
1,
2]. For a lot of these blind people, stimulating the visual cortex is the treatment of last resort due to damage to the visual pathway. Such a system, an intracortical visual prosthesis, consists of implanted electrodes, a signal processor on the outside as well as a camera and a feedback loop. [
3]. In the context of this work, the Dutch NESTOR project (NEuronal STimulation fOr Recovery of function) aims to implant 1024 electrodes for stimulation and recording in the brain [
4,
5] (funded by the Netherlands Organization for fundamental research—NWO). Wireless connection between the implanted electrode and the external processor is desired to facilitate mobility and to avoid infections during long-term use [
6]. On the implant side, this wireless connection involves uplink (for recording), downlink (for stimulation) and wireless power transfer.
This work focuses on the implanted transceiver IC, which is the transmitter for sending out of the head (uplink) and the receiver for receiving stimulation data (downlink).
There are a few possible configurations for the wireless system. The implanted electrodes are grouped into arrays of 64 electrodes. Our approach used in this work is to place the central transceiver beneath the skin. The electrode arrays are tethered to the central transceiver [
7].
Figure 1 illustrates our solution. Our approach is more easily scalable than placing an implanted transceiver on each electrode array beneath the skull, making them independent [
8], but requiring multiple implanted transceivers. For instance, our 1024 electrodes are implemented by 16 arrays of 64 electrodes (typical of Utah arrays). Taking an approach with an independent transceiver per electrode array would require 16 transceivers in total. Our proposed tethered approach, which requires only one central transceiver as in
Figure 1, is more scalable. Furthermore, in our approach, a single transceiver unit could be used with a smaller or larger amount of tethered electrode arrays. For the concept we propose, this does not matter. The electrode arrays need to be placed at the desired location, while communication with the outside world will not change, due to the central unit. Our approach is preferred over using a central transceiver placed beneath the skull, which will face more attenuation and path-loss by the bone tissue (up to 10 dB more) [
9]. The main challenge in our tethered solution is the possible micro-motion of the implanted connecting wires; this can be partly alleviated with better packaging and implantation. In this paper, we focus on the implanted transceiver IC design and analyze its link budget in the context of a complete system.
Generic biomedical telemetries have been proposed for the implanted transmitter for recording and also for an implanted receiver for stimulation. However, in this work, we combine them into a single implanted transceiver for bi-directional communication in an intracortical visual prosthesis. In [
10], optical communication was attempted for the uplink. However, this faces a challenge of alignment sensitivity. Impulse radio ultrawideband (IR-UWB) was used in [
11], showing a promising result. A high data rate was achieved in [
12] using an IR-UWB transmitter. In our work, for the recording, we use IR-UWB for the uplink because of its low-power and high data rate potential at its transmitter, which will be at the implant side. For our implanted transmitter, we applied current control to make the impulse generator tunable for pulse width. A straightforward on-off keying modulation (OOK) scheme is implemented, based on a simple D-latch to achieve low-power consumption. Furthermore, a current-controlled variable oscillator is proposed to tune the number of pulses per bit. The transmitter is built using predominantly digital components to strive towards low power consumption while delivering a high data rate (a minimum of 23 Mbps is required [
13]). The potential of digital-based designs is discussed in [
14,
15], which is beneficial to low-power transceivers.
For the downlink receiver, an analog differential phase-shift keying (DPSK) receiver was used in [
16]. Pulse delay modulation (PDM) was used in [
17] and an Amplitude Shift Keying (ASK) to Frequency Shift Keying (FSK) conversion receiver in [
18], both for low power consumption. However, for our implanted receiver we took an approach of a non-coherent digital receiver, with low-carrier frequency (4 MHz) and using an inductive link. The implanted receiver’s low-power and sufficient data rate due to its predominantly digital components and low frequency are the reasons for its selection. The receiver is above the minimum data rate requirement of 200 kbps for the downlink [
19].
In this work we describe the design of our fabricated implanted transceiver (excluding coils and antenna) on IC, based on CMOS 180 nm technology. Our idea is to: (1) use predominantly digital components to achieve lower power consumption; (2) provide tunability for the implanted IR-UWB transmitter with current control for its oscillator and impulse generator; and (3) make the implanted receiver adjustable with current controls to optimize for an inductive link.
3. Implanted Transceiver
3.1. IR-UWB Transmitter
To achieve the low power consumption, the IR-UWB transmitter can be designed as a radio frequency integrated circuit (RFIC) rather than with discrete microwave components [
26]. The IR-UWB transmitter can be implemented as an RFIC using CMOS technology. Since the transmit power of IR-UWB is low due to the FCC restriction [
27], a simple CMOS IC is sufficient. This renders the CMOS RFIC transmitter to consume little power and it allows for integration with the downlink implanted receiver in the same IC.
Figure 2 shows the overall circuit diagram of the proposed CMOS IC IR-UWB transmitter. The IR-UWB transmitter is comprised mainly of the modulator, the impulse generator and a current-controlled oscillator. The design of the transmit antenna, which will be connected to the chip, should be compact and wide band. Although this is also an important aspect for the overall system, it is outside the scope of this paper. To attain low power consumption and reduce complexity, an on-off keying modulation (OOK) scheme is used. It modulates the short pulses (impulse signals) that come from the impulse generator. The modulator can be implemented in CMOS technology by a simple D-Latch [
28], making it a digital component. The data bits and the current-controlled oscillator clock are fed as the control signal and D-input of the latch, respectively. The resulting signal is fed to the impulse generator (see
Figure 2).
Implementing the impulse generator in CMOS technology can be done with a tunable delay element, followed by squaring of both the signal and its delayed version, and then a NOR-logic gate to form the pulses. The oscillator used for pulse generation in the pulse generator is a five-stage current-starved single-ended ring oscillator as reported in [
29].
Figure 3 shows the circuit schematic of the five-stage current-starved single-ended ring oscillator. The difference compared to [
29], however, is that five stages was used in our work, and an extra transistor for current control makes it differ from [
29].
For tunable delay elements, a current-controlled shunt-capacitor as in [
30] is proposed. Tuning is realised via transistors M1, M2 and M3, while transistors M4, M5 and M6 are used for balance, see
Figure 2. Transistor M1 transforms the control current into voltage and biases M2. By changing the input current, the resistance of M2 is tuned. This changes the capacitive loading of M3 on the first stage of the inverter chain. The tunable delay elements add flexibility and help shaping the spectrum of the impulse signals as first explored in [
31], our differs with an extra transistor to make it current-controlled rather than voltage-controlled. For proper impulse forming using a NOR-logic gate, the squareness of the signals coming from the tunable delay lines is crucial, and this is done by using three inverters on both the reference line and the delay line for symmetry.
Figure 4 shows the IC layout design of the IR-UWB transmitter. From the figure it can be seen that the NOR gate, which is the impulse construction block, is made large enough to drive an antenna that could be connected to it in future work. Large transistor sizes improve the drive capability of the last stage, especially when logic gates are used [
32].
Finally, pulse shaping filters are needed, which can be implemented off-chip either by relying on the transmission parameter (S21) from the biological tissue (skin) between the transmit/receive antenna or by a bandpass filter. The shape response is similar if they are designed to pass the same band, and does not impact non-coherent detection of the OOK IR-UWB signal at the external side in our 3–7 mm near-field scenario. In open air, far-field transmission, pulse shaping filters are relevant to make the system satisfy the FCC mask. However, in our context, with transmission through 3–7 mm of skin, already 20–25 dB loss is seen, which causes the radiated power at the surface of the head to be already far below the FCC mask. This is based on our transmitter delivering −27 dBm and the aforementioned attenuation through skin. In spite of these losses, the link budget can still be met.
3.2. Non-Coherent BPSK Receiver
Similarly to the transmitter design for uplink, the requirements for downlink can be met by taking a system approach aimed at designing a low-power implementation. This involves using low frequency (<100 MHz), an inductive link, phase shift keying (PSK), and a nearly digital receiver with non-coherent demodulation after sampling and by means of edge detection, as introduced in [
19,
33,
34]. The sampling of the received signal makes it possible for a non-coherent demodulation in the BPSK signal by using only edge detection, as described in [
35]. We say the receiver is nearly digital because of the use of predominately digital components.
Figure 5 shows the block diagram of the receiver. At the receiver side, the entire signal is sampled. The sampling is essentially done using a comparator, sometimes also called a 1-bit analog to digital converter (ADC). This comparator is a dynamic comparator as in [
36]. Its threshold, which is the input common mode voltage, can be set by Vcntrl comparator, as shown in
Figure 5, and the sensitivity is found to be below 50 mV (in simulations). The comparator shares the same clock with the non-coherent digital demodulator.
Figure 6 shows the circuit schematic of the 1-bit ADC which is based on [
36]. After this 1-bit ADC stage, the resulting signal is non-coherently digitally demodulated. The non-coherent digital demodulator is the central part of the receiver, and it will be detailed next.
Figure 7 shows the schematic of the non-coherent-digital demodulator. The non-coherent digital demodulator detects if a ‘0’ or a ‘1’ was transmitted by detecting the type of edge it encounters in the digitized received modulated signal. Note that the digitized modulated signal has a falling edge for the ’0’ and a rising edge for the ‘1’. While detecting which type of edge is present, the sub-system must take care to avoid the transition points between symbols so that these are not detected as edge types. It is comprised mainly of an edge detector, a reset generator, and an oscillator. A similar concept was presented in [
35], but in our case, the data rate to carrier frequency ratio is not 100% due to practical bandwidth limitations and losses in inductive links. Inductive coils that are designed for transmission and reception create a bandwidth for which the BPSK signal is communicated, and this is band limited by design which leads to about 5–70% data rate to carrier frequency ratio in practice [
34]. We aim to be within this range, as delivering a sufficient data rate is the main priority, and because the carrier frequency can be scaled appropriately.
The edge detector uses a rising edge D-type flip-flop and a falling edge D-type flip-flop to detect if an edge occurs and which type of edge it is, using an OR logic gate and an AND logic gate, respectively. These logic gates will take the outputs of the flip-flops as their input. The inputs of both flip-flops are a logical ‘1’ while the received digitized modulated signal is fed as its clock input. This configuration yields the desired effect of edge detection in a power efficient way. The asynchronous clear input of the flip-flops is connected to the reset generator. Asynchronous clearing implies that the flip-flops are cleared decoupled from clock ticks. This is done to reset the flip-flops to avoid detecting the transition point between symbols.
The role of the reset generator module is to provide a reset signal to reset the edge detector at a time after an edge detection at , between and . Here, is the period of the carrier frequency. To achieve this, it counts, using an asynchronous counter. We determine the frequency of the clock, which is essentially the frequency of the oscillator, as follows.
Let
N be the count-up value
. The following inequalities must be satisfied. To reset after the transition point between carrier symbols, we have
To ensure that there is no reset after the next edge, we set
Combining (
1) and (
2), we arrive at
Taking reciprocals, the range of the frequency of the oscillator to avoid transition between symbols then results:
A low count-up value of
N, for example
, yields an oscillator frequency range of
. This already strongly relaxes the jitter or quality factor requirement of the oscillator. Thus, a low-power current-controlled oscillator can be used. Similar to the IR-UWB tranmsitter, the oscillator used for clock is in the receiver is another five-stage current-starved single-ended ring oscillator as in
Figure 3.
Figure 8 shows the layout of the receiver on IC. A count-up number of
was used to improve flexibility of adjusting the timing range, which corresponds to the most-significant bit of the 5-bit counter in the reset generator. More details on the components and principle of operation can be found in our previous works in [
21,
34].
7. Conclusions
A sub-milliwatt transceiver IC for the implant side of an intracortical visual prosthesis was designed, fabricated and measured. It delivers 1 Mbps for the downlink (for stimulation) and 50 Mbps for the uplink (for recording), using a non-coherent BPSK demodulator and an IR-UWB transmitter, respectively. Its predominately digital components and adjustability lead to the low power consumption of 0.2 mW for the BPSK receiver and 0.3 mW for the IR-UWB transmitter at 1.3 V supply on 180 nm CMOS technology. Based on our transceiver IC in the implant, the system link budget analysis for both uplink and downlink show achievable figures: there is 18–23 dB excess margin for uplink, and 12–26 dB for downlink. These figures show that the link can be closed with an excess margin for the antenna/coil pair to communicate through 3–7 mm skin, which is the transcutaneous interface between the implant side and outer side, while achieving good BER performance as a result of closing the link with an excess margin.
In the future, scaling to more advanced processes that use lower supply voltages will further drastically reduce power consumption due to the predominately digital architecture. Furthermore, the design of antennas/coils and a transceiver IC on the outside, in order to realize the system link budget, is the logical next step.