Optimal Bias Condition of Dummy WL for Sub-Block GIDL Erase Operation in 3D NAND Flash Memory

Abstract

In this study, we have analyzed the optimal bias condition of dummy WL for the sub-block gate induced drain leakage (GIDL) erase operation in 16-layer 3D NAND flash memory. Three-dimensional NAND flash memory performs an erase operation in units of pages. Increasing the number of stacks increases the number of cells that are erased at one time, which can lead to undesirable durability degradation. In this case, the sub-block erase operation can reduce the burden on the cell by up to half, due to the erase operation. The distribution of the hole density (hDensity) and the potential, according to V_Dummy, was analyzed when block1 and block2 were erased by setting WL0:WL7 to block1, WL9:WL15 to block2, and WL8 to dummy WL. For the simulation results, block1 showed an optimal distribution of hDensity and potential in the order of 20 V, floating, and 0 V. In block2, the optimal distribution of hDensity was shown in the order of 20 V, floating, and 0 V, with the optimal distribution of the potential in the order of floating and 0 V.

1. Introduction

Three-dimensional NAND flash memory is currently the most popular memory device and is being actively applied in various fields, such as SSD and flash memory [1]. As of 2013, 3D NAND flash memory has achieved growth, in both capacity and performance, by overcoming limits through vertical stacking in planar NAND, which uses existing floating gates [2,3,4,5,6]. However, this development trend has increased the block size of the 3D NAND [7,8,9,10]. In the bit-cost scalable (BiCS) architecture, the channel is connected to the common source line (CSL), so the body bias cannot be applied directly to the channel. For this reason, we use the GIDL deletion method in CSL to inject holes into the channel in order to increase the channel potential. Due to the structural characteristics of using common source line, the program/erase cycle increases in proportion to the increasing block size in the 3D NAND that performs the erase operation in units of blocks. When the program/erase cycle is increased, the reliability of the device decreases due to various problems, such as the deterioration of the retention characteristics caused by the heat that is generated during the P/E operation, cell disturbance caused by the P/E operation, and the deterioration of the durability of the blocking oxide [11,12,13,14,15,16,17]. This problem can be improved by using a dummy WL to split the blocks and to erase only the selected blocks [18,19,20,21]. In this case, the bias condition of the dummy WL affects the neighboring cells, because the bias that is applied to the dummy WL affects the channel potential according to the coupling ratio of the gate dielectrics [22,23,24,25]. Therefore, the optimal dummy WL bias condition means a state in which the neighboring cells can operate normally without causing a disturbance [26]. During the GIDL erase operation, the channel potential increases to almost the V_Erase that is applied to the CSL [27]. Based on these characteristics, six cases were simulated, including the condition of selecting block1 and block2 with the bias conditions of V_Dummy set to V_Erase, 0V, and floating. For fast and efficient simulation, a random string was selected from the 16-layer 3D NAND flash memory structure, as shown in Figure 1, and the GIDL erase operation was performed in order to analyze the potential difference between the channel and WL.

2. Simulation Design and Results

2.1. 3D NAND Flash Memory Structure Setup

Figure 2 shows a cross-section of the 3D NAND flash memory structure that is used in technology computer-aided design (TCAD) simulation. The gate length was set to 30 nm for all of the main cells, string select line (SSL), and ground select line (GSL), and the gate spacing was also set to 30 nm. The thickness of the oxide/nitride/oxide (O/N/O), which is a dielectric constituting the center of the gate, was set to 4/8/8 nm, respectively [24]. Block1 was set as WL0:WL7 and block2 was set as WL9:WL15, which was divided into two blocks based on WL8 set as dummy WL.

2.2. Simulation Setup

Figure 3 shows the timing diagram that was used for sub-block erase. For the erase operation, 0 V was applied to SSL and GSL, and 20 V V_Erase was applied to CSL. At this time, GIDL was generated by the potential difference between CSL and GSL; channel electrons leaked out and the channel potential rose. The WL of the Un-erase block was set to floating in order to reduce the potential difference between the channel and WL. A total of 0 V was applied to the WL of the Erase block in order to induce a potential difference between the channel and WL. The voltage of the dummy WL was simulated under the following three conditions: 20 V (V_Erase), 0 V, and floating.

2.3. Analysis of hDensity

Figure 4 shows the hDensity of the cross-section of the selected string after applying V_Erase to CSL for 100 µs. Figure 4a–c performed the erase operation in block2 (WL9:WL15), and Figure 4d–f performed the erase operation in block1 (WL0:WL7). The bias condition of the dummy WL was set to 20 V, 0 V, and floating. In the case of Figure 4a,d where 20 V was applied to V_Dummy, it was confirmed that the hDensity of the channel and the nitride was maintained less in the direction of the Un-erase block near to the dummy (WL) than in the other cases.

2.4. Analysis of Potential to Channel and WL

Figure 5 shows the channel and WL potential of the selected string after applying V_Erase to CSL for 100 µs. The bias condition of the dummy WL affected the adjacent WL, WL7, and WL9. The adjacent WLs were more affected when they were included in an Un-erase block than in an Erase block. This is because the WL in the Un-erase block remained floating during the erase phase. In Figure 5a, it was confirmed that the V_Dummy had the highest channel potential when it was maintained in a floating state. Figure 5b shows the best WL potential in the Un-erase block when the V_Dummy was 20 V. Figure 5c shows the potential that was obtained by subtracting Figure 5b from Figure 5a, which is the potential difference between the channel and WL. In the Erase block, the potential difference should be large, and in the Un-erase block, the potential difference should be close to zero in order to avoid unwanted erase disturbance. In Figure 5c, when the V_Dummy was 20 V, the WL7 and WL6 that were adjacent to the dummy WL showed a potential difference that was optimized for the Un-erase block but showed an inadequate potential difference of approximately 14 V in the Erase block. In Figure 5d, when the V_Dummy was 20 V, the channel potential difference was almost the same. In Figure 5e, almost the same potential was measured in the Erase block, and the most ideal potential was shown in the Un-erase block when the V_Dummy was 20 V. Figure 5f shows the potential that was obtained by subtracting Figure 5e from Figure 5d. Unlike the result shown in Figure 5c, an appropriate potential difference was measured in the Erase block, even when 20 V was applied to the V_Dummy. The WL9 and WL10, which were adjacent to the dummy WL, showed a potential difference close to zero, showing the potential suitability of the Un-erase block. In the channel and WL potential simulation results, the optimal V_Dummy showed a different order when performing the erase operation in block1 and block2. When the erase operation was performed on block1 close to the CSL, the optimal potential was shown in the order of 20 V, floating, and 0 V. When performing the erase operation on block2 far from the CSL, only floating and 0 V could be used as the V_Dummy, and 20 V was confirmed to be an unsuitable voltage for the V_Dummy.

3. Conclusions

In the simulation results of the channel and WL potential, the optimal V_Dummy was confirmed to be in a different order, according to the selected block during the erase operation. It was confirmed that the hDensity in the nitride layer of the Un-erase block could be effectively lowered if V_Erase and V_Dummy are applied at the same level when erasing block1 and block2. In particular, a lower hDensity was confirmed at the bottom of WL8, which was set as the dummy WL. This is because the high V_Dummy that was applied to the dummy WL prevents tunneling. Therefore, it was confirmed that the V_Dummy showed the ideal hDensity in the order of 20 V, floating, and 0 V. In the channel and WL potential measurement results, the optimal V_Dummy showed a different order when performing the erase operation. In the case where block1 was set as the Erase block, the optimal potential distribution was shown in the order of 20 V, floating, and 0 V. In the case where block2 was set as the Erase block, a V_Dummy of 20 V reduced the channel potential of the Erase block to 14 V, thereby reducing the erase efficiency. In this case, it was confirmed that the optimized potential distribution appeared in the order of floating, 0 V, and 20 V.