High-Performance Data Converters

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: closed (31 December 2023) | Viewed by 2511

Special Issue Editor


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Guest Editor
School of Microelectronics, Xidian University, Xi’an 710000, China
Interests: high-performance analog circuit; ADCs; DACs

Special Issue Information

Dear Colleagues,

ADCs and DACs are widely used in various signal-processing systems. With the increasing demand of ADCs and DACs in IoT, sensing, communication and controlling applications, the energy efficiency, sampling rate and conversion accuracy are required to be co-optimized.

This Special Issue seeks high-quality contributions that address latent challenges in ADCs and DACs with different architectures and contribute to the advancement of the state of the art in this field. Research papers detailing theoretical and experimental developments are welcome. The topics of interest include, but are not limited to, the following:

  1. High-resolution noise-shaping related ADC (NS SAR ADC, ∑Δ ADC, zoom ADC);
  2. High-resolution Nyquist ADC (the ENOB generally is no lower than 16 bits);
  3. High-speed ADCs, including both single-channel and TI types;
  4. Energy-efficient ADCs with the FoM result achieving the state-of-the-art level;
  5. High-performance analog circuits employing ADCs and DACs.

Dr. Yuhua Liang
Guest Editor

Manuscript Submission Information

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Keywords

  • ADC
  • DAC
  • noise-shaping
  • analog circuit

Published Papers (2 papers)

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Research

20 pages, 5540 KiB  
Article
New Method for Logarithmic Analogue-to-Digital Conversion Using Switched Capacitors with a Variable Logarithmic Base
by Zynoviy Mychuda, Mykola Mykyichuk, Igor Zhuravel, Lesia Mychuda, Adam Szcześniak and Zbigniew Szcześniak
Electronics 2024, 13(1), 29; https://doi.org/10.3390/electronics13010029 - 20 Dec 2023
Cited by 1 | Viewed by 776
Abstract
This article is devoted to the development of a new method of logarithmic analogue-to-digital conversion using switched capacitors with a variable logarithmic base. The essence of the method and its implementation are presented. Mathematical models have been developed, analysis has been carried out [...] Read more.
This article is devoted to the development of a new method of logarithmic analogue-to-digital conversion using switched capacitors with a variable logarithmic base. The essence of the method and its implementation are presented. Mathematical models have been developed, analysis has been carried out and errors have been assessed. It has been demonstrated that the developed converters, using the proposed method, significantly outperform known analogous converters: for input voltages ranging from 1 mV to 10 V, the processing error does not exceed 0.001% with a processing time not greater than 105 µs (microseconds). Full article
(This article belongs to the Special Issue High-Performance Data Converters)
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10 pages, 3890 KiB  
Communication
A Data Weight Averaging-Inspired Digital Calibration Method for a 10-Bit Noise-Shaping Successive Approximation Register
by Shuang Xie and Yong Wang
Electronics 2023, 12(14), 3046; https://doi.org/10.3390/electronics12143046 - 12 Jul 2023
Cited by 2 | Viewed by 1299
Abstract
This paper presents a digital calibration method for a 10-bit noise-shaping Successive Approximation Register Analog to Digital Converter (SAR ADC). The proposed calibration method is inspired by its Data Weight Averaging (DWA) counterpart, but stays static, while achieving a similar Integral Nonlinearity (INL) [...] Read more.
This paper presents a digital calibration method for a 10-bit noise-shaping Successive Approximation Register Analog to Digital Converter (SAR ADC). The proposed calibration method is inspired by its Data Weight Averaging (DWA) counterpart, but stays static, while achieving a similar Integral Nonlinearity (INL) and 1.3 dB better Signal-to-Noise Ratio (SNR) in measurements without oversampling. This advantage in SNR holds until an Oversampling Ratio (OSR) of 2 for the proposed method, which also saves 50 % power. At a 1.2 V power supply, the ADC consumes a power of 70 µW at a conversion rate of 50 kHz. Fabricated using 55 nm Complementary Metal Oxide Semiconductor (CMOS) Metal-Oxide-Metal Capacitor (MOMCAP) technology, it occupies an active area of 370 µm × 350 µm, when achieving an INL of 0.3 Least Significant Bit (LSB) and an SNR of 66.9 dB at an OSR of 8. Full article
(This article belongs to the Special Issue High-Performance Data Converters)
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