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Electronics
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Emerging Applications of FPGAs and Reconfigurable Computing System
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Emerging Applications of FPGAs and Reconfigurable Computing System

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Computer Science & Engineering".

Deadline for manuscript submissions: 15 February 2026 | Viewed by 16336

Special Issue Editor

Dr. José V. Frances-Villora

E-Mail Website
Guest Editor
School of Engineering (ETSE), University of Valencia, 46100 Burjassot, Spain
Interests: reconfigurable logic; hardware implementation of signal processing; hardware implementation of machine learning; hardware real-time applications; spiking neural networks; biomedical engineering; EEG processing; ECG processing; automotive applications
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

The continuous modernizing of the characteristics and features of FPGA devices has led to this becoming the natural choice of many final designs. Over the last three decades, these devices have evolved from a few thousand logic blocks to systems-on-chip, integrating billions of transistors. And the current result of this evolution is a set of flexibility and reconfigurability capabilities without precedents, capabilities that enable rapid prototyping, massive parallel designs, and high energy efficiency. Moreover, current FPGAs enable the integration of microprocessor architectures, thus becoming a powerful alternative to create highly efficient computer systems.

Thus, FPGA devices can be reconfigured to implement tailored designs and architectures based on the characteristics of target applications. This is the reason why the use of FPGAs and reconfigurable computing systems are rapidly increasing, bringing new opportunities for engineering across a wide range of applications.

This Special Issue, entitled “Emerging Applications of FPGAs and Reconfigurable Computing System”, is intended to present the latest advances (state-of-the-art contributions) in applications and designs using FPGAs and reconfigurable computing systems, including (but not limited to) the following:

  • Control
  • Image processing
  • Signal processing
  • Cybersecurity
  • Embedded systems
  • Power systems
  • Intelligent systems
  • Machine learning
  • Biomedical applications
  • Robotics
  • IoT applications
  • Telecommunications
  • Networking
  • High-performance computing
  • Reconfigurable computing
  • Particle physics
  • Manufacturing
  • Deep neural networks.

Dr. José V. Frances-Villora
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 250 words) can be sent to the Editorial Office for assessment.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • FPGA
  • reconfigurable computing
  • embedded systems
  • VHDL
  • high-level synthesis
  • verilog
  • FPGA application

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Published Papers (7 papers)

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Research

Jump to: Review

18 pages, 47766 KB  
Article
Scalable AI + DSP Compute Frameworks Using AMD Xilinx RF-SoC ZCU/VCU Platforms for Wireless Testbeds for Scientific, Commercial, Space, and Defense Applications
by Buddhipriya Gayanath, Gayani Rathnasekara, Kasun Karunanayake and Arjuna Madanayake
Electronics 2026, 15(2), 445; https://doi.org/10.3390/electronics15020445 - 20 Jan 2026
Viewed by 355
Abstract
This paper describes recent engineering designs that allow full-duplex SerDes connectivity between a number of cascaded Xilinx radio frequency system-on-chip (RF-SoC) and VCU FPGA systems. The design allows for unlimited scalability with all-to-all connectivity across FPGA systems and RF-SoCs that allow for bidirectional [...] Read more.
This paper describes recent engineering designs that allow full-duplex SerDes connectivity between a number of cascaded Xilinx radio frequency system-on-chip (RF-SoC) and VCU FPGA systems. The design allows for unlimited scalability with all-to-all connectivity across FPGA systems and RF-SoCs that allow for bidirectional data transport in streaming mode at a capacity of 50 Gbps per ADC-DAC channel. A custom massively parallel systolic-array architecture supporting 8 parallel data streams from time-interleaved ADC/DACs allow real-time matrix–vector-multiplication (MVM). The MVM can be 8 × 8, 8 × 16, …, 8 × 1024 in supported matrix size, and is demonstrated in real time sustained throughput of 1 TeraMAC/second, for matrix size 8 × 512. The MVM is the building block supporting machine learning and filtering, with the computational graph split across FPGA systems using the SerDes connections. The RF data processed by the FPGA chain can be further utilized for higher-level AI workloads on an NVIDIA DGX Spark platform connected to the system. We demonstrate two platforms in which ZCU111 and ZCU1285 RF-SoC boards perform direct-RF data acquisition, while compute engines operating in real time on VCU128 and VCU129 FPGA boards showcase both digital beamforming and polyphase FIR filterbanking in a real-time bandwidth of 1.0 GHz. Full article
(This article belongs to the Special Issue Emerging Applications of FPGAs and Reconfigurable Computing System)
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31 pages, 1411 KB  
Article
A Source-to-Source Compiler to Enable Hybrid Scheduling for High-Level Synthesis
by Yuhan She, Yanlong Huang, Jierui Liu, Ray C. C. Cheung and Hong Yan
Electronics 2025, 14(23), 4578; https://doi.org/10.3390/electronics14234578 - 22 Nov 2025
Viewed by 491
Abstract
High-Level Synthesis (HLS) has gained considerable attention for its ability to quickly generate hardware descriptions from untimed specifications. Most state-of-the-art commercial HLS tools employ static scheduling, which excels in compute-intensive applications but struggles with control-dominant designs. While some open-source tools propose dynamic and [...] Read more.
High-Level Synthesis (HLS) has gained considerable attention for its ability to quickly generate hardware descriptions from untimed specifications. Most state-of-the-art commercial HLS tools employ static scheduling, which excels in compute-intensive applications but struggles with control-dominant designs. While some open-source tools propose dynamic and hybrid scheduling techniques to synthesize dataflow-like architectures to improve speed, they lack well-established optimizations from static scheduling like datapath optimization and resource sharing, leading to frequency degradation and area overhead. Moreover, existing hybrid scheduling relies on extra dynamic synthesis support, either by dynamic or static HLS tools, and thereby loses generality. In this work, we propose another solution to achieve hybrid scheduling: a source-to-source compiler that exposes dynamism at the source code level, which reduces both frequency and area overhead while remaining fully compatible with modern static HLS tools without needing extra dynamic synthesis support. Experiments show significant improvements (1.26× speedup) on wall clock time (WCT) compared to VitisHLS and a better area–frequency–latency trade-off compared to dynamic (1.83× WCT speedup and 0.46× area) and hybrid (2.14× WCT speedup and 0.72× area) scheduling-based tools. Full article
(This article belongs to the Special Issue Emerging Applications of FPGAs and Reconfigurable Computing System)
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16 pages, 3971 KB  
Article
Enhancing Radiation Resilience and Throughput in Spaceborne RS(255,223) Encoder via Interleaved Pipelined Architecture
by Xufeng Li, Li Zhou and Yan Zhu
Electronics 2025, 14(12), 2447; https://doi.org/10.3390/electronics14122447 - 16 Jun 2025
Viewed by 679
Abstract
The error correction capability of the RS(255,223) code has been significantly enhanced compared to that of the RS(256,252) code, making it the preferred choice for the next generation of onboard solid-state recorders (O-SSRs). With the application of non-volatile double data rate (NV-DDR) interface [...] Read more.
The error correction capability of the RS(255,223) code has been significantly enhanced compared to that of the RS(256,252) code, making it the preferred choice for the next generation of onboard solid-state recorders (O-SSRs). With the application of non-volatile double data rate (NV-DDR) interface technology in O-SSRs, instantaneous transmission rates of up to 1 Gbps per data I/O interface can be achieved. This development imposes higher requirements on the encoding throughput of RS encoders. For RS(255,223) encoders, throughput improvement is limited by the structures of serial architectures. The algorithm’s inherent characteristics restrict the depth of pipelining. In contrast, parallel solutions face bottlenecks in resource efficiency. To address these challenges, an interleaved pipelined architecture is proposed. By integrating interleaving technology within the pipeline, the structure overcomes the limitations of serial architectures. Using this architecture, a 36-stage pipelined RS(255,223) encoder is implemented. The throughput is greatly enhanced, and the radiation tolerance is also improved due to the application of interleaving techniques. The RS(255,223) encoder performance was evaluated on the Xilinx XC7K325T platform. The results confirm that the proposed architecture can support high data rates and provide effective error correction. With an 8-bit symbol size, a single encoder achieved throughput of 3.043 Gbps, making it highly suitable for deployment in future space exploration missions. Full article
(This article belongs to the Special Issue Emerging Applications of FPGAs and Reconfigurable Computing System)
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17 pages, 4831 KB  
Article
Achieving Low-Latency, High-Throughput Online Partial Particle Identification for the NA62 Experiment Using FPGAs and Machine Learning
by Pierpaolo Perticaroli, Roberto Ammendola, Andrea Biagioni, Carlotta Chiarini, Andrea Ciardiello, Paolo Cretaro, Ottorino Frezza, Francesca Lo Cicero, Michele Martinelli, Roberto Piandani, Luca Pontisso, Mauro Raggi, Cristian Rossi, Francesco Simula, Matteo Turisini, Piero Vicini and Alessandro Lonardo
Electronics 2025, 14(9), 1892; https://doi.org/10.3390/electronics14091892 - 7 May 2025
Cited by 2 | Viewed by 1069
Abstract
FPGA-RICH is an FPGA-based online partial particle identification system for the NA62 experiment employing AI techniques. Integrated between the readout of the Ring Imaging Cherenkov detector (RICH) and the low-level trigger processor (L0TP+), FPGA-RICH implements a fast pipeline to process in real-time the [...] Read more.
FPGA-RICH is an FPGA-based online partial particle identification system for the NA62 experiment employing AI techniques. Integrated between the readout of the Ring Imaging Cherenkov detector (RICH) and the low-level trigger processor (L0TP+), FPGA-RICH implements a fast pipeline to process in real-time the RICH raw hit data stream, producing trigger primitives containing elaborate physics information—e.g., the number of charged particles in a physics event—that L0TP+ can use to improve trigger decision efficiency. Deployed on a single FPGA, the system combines classical online processing with a compact Neural Network algorithm to achieve efficient event classification while managing the challenging ∼10 MHz throughput requirement of NA62. The streaming pipeline ensures ∼1 μs latency, comparable to that of the NA62 detectors, allowing its seamless integration in the existing TDAQ setup as an additional detector. Development leverages High-Level Synthesis (HLS) and the open-source hls4ml package software–hardware codesign workflow, enabling fast and flexible reprogramming, debugging, and performance optimization. We describe the implementation of the full processing pipeline, the Neural Network classifier, their functional validation, performance metrics and the system’s current status and outlook. Full article
(This article belongs to the Special Issue Emerging Applications of FPGAs and Reconfigurable Computing System)
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20 pages, 3218 KB  
Article
An Innovative Digital Pulse Width Modulator and Its Field-Programmable Gate Array Implementation
by Giovanni Bonanno
Electronics 2025, 14(8), 1522; https://doi.org/10.3390/electronics14081522 - 9 Apr 2025
Viewed by 745
Abstract
Digital pulse-width modulation (DPWM)-based controls are characterized by a non-negligible phase delay due to analog-to-digital (ADC) conversion, sampling time, carrier shape, and algorithm computation time. These delays degrade the performance in closed-loop systems, where the bandwidth must be reduced to avoid instability issues [...] Read more.
Digital pulse-width modulation (DPWM)-based controls are characterized by a non-negligible phase delay due to analog-to-digital (ADC) conversion, sampling time, carrier shape, and algorithm computation time. These delays degrade the performance in closed-loop systems, where the bandwidth must be reduced to avoid instability issues due to the reduced closed-loop phase margin. To mitigate these delays, approaches such as utilizing low-latency ADCs or increasing the sampling frequency have been employed. However, these methods are often costly and do not address the fundamental delay issues inherent to DPWMs. In this paper, a novel zero phase-delay DPWM architecture is proposed. This enhanced architecture seamlessly integrates pulse width and frequency modulation to create a programmable derivative action, capable of effectively recovering the DPWM delay. The proposed architecture employs a reliable and straightforward organization, suitable for implementation in commercial field programmable gate array (FPGA). Furthermore, this architecture inherently generates a trigger signal that can be used in numerous power electronic applications to capture the average value in piecewise linear inductor currents. The validity of the proposed architecture is substantiated through simulations and experimental tests. The final implementation is shared in an open-source resource. Full article
(This article belongs to the Special Issue Emerging Applications of FPGAs and Reconfigurable Computing System)
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17 pages, 595 KB  
Article
Hardware Optimized Modular Reduction
by Alexander Magyari and Yuhua Chen
Electronics 2025, 14(3), 550; https://doi.org/10.3390/electronics14030550 - 29 Jan 2025
Cited by 1 | Viewed by 1975
Abstract
We introduce a modular reduction method that is optimized for hardware and outperforms conventional approaches. By leveraging calculated reduction cycles and combinatorial logic, we achieve a remarkable 30% reduction in power usage, 27% reduction in Configurable Logic Blocks (CLBs), and 42% fewer look-up [...] Read more.
We introduce a modular reduction method that is optimized for hardware and outperforms conventional approaches. By leveraging calculated reduction cycles and combinatorial logic, we achieve a remarkable 30% reduction in power usage, 27% reduction in Configurable Logic Blocks (CLBs), and 42% fewer look-up tables (LUTs) than the conventional implementation. Our Hardware-Optimized Modular Reduction (HOM-R) system can condense a 256-bit input to a four-bit base within a single 250 MHz clock cycle. Further, our method stands out from prevalent techniques, such as Barrett and Montgomery reduction, by eliminating the need for multipliers or dividers, and relying solely on addition and customizable LUTs. This innovative method frees up FPGA resources typically consumed by power-intensive DSPs, offering a compelling low-power, low-latency alternative for diverse design needs. Full article
(This article belongs to the Special Issue Emerging Applications of FPGAs and Reconfigurable Computing System)
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Review

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30 pages, 3046 KB  
Review
A Survey of Advancements in Scheduling Techniques for Efficient Deep Learning Computations on GPUs
by Rupinder Kaur, Arghavan Asad, Seham Al Abdul Wahid and Farah Mohammadi
Electronics 2025, 14(5), 1048; https://doi.org/10.3390/electronics14051048 - 6 Mar 2025
Cited by 3 | Viewed by 9787
Abstract
This comprehensive survey explores recent advancements in scheduling techniques for efficient deep learning computations on GPUs. The article highlights challenges related to parallel thread execution, resource utilization, and memory latency in GPUs, which can lead to suboptimal performance. The surveyed research focuses on [...] Read more.
This comprehensive survey explores recent advancements in scheduling techniques for efficient deep learning computations on GPUs. The article highlights challenges related to parallel thread execution, resource utilization, and memory latency in GPUs, which can lead to suboptimal performance. The surveyed research focuses on novel scheduling policies to improve memory latency tolerance, exploit parallelism, and enhance GPU resource utilization. Additionally, it explores the integration of prefetching mechanisms, fine-grained warp scheduling, and warp switching strategies to optimize deep learning computations. These techniques demonstrate significant improvements in throughput, memory bank parallelism, and latency reduction. The insights gained from this survey can guide researchers, system designers, and practitioners in developing more efficient and powerful deep learning systems on GPUs. Furthermore, potential future research directions include advanced scheduling techniques, energy efficiency considerations, and the integration of emerging computing technologies. Through continuous advancement in scheduling techniques, the full potential of GPUs can be unlocked for a wide range of applications and domains, including GPU-accelerated deep learning, task scheduling, resource management, memory optimization, and more. Full article
(This article belongs to the Special Issue Emerging Applications of FPGAs and Reconfigurable Computing System)
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