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Electronics
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Emerging Applications of FPGAs and Reconfigurable Computing System
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Emerging Applications of FPGAs and Reconfigurable Computing System

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Computer Science & Engineering".

Deadline for manuscript submissions: 15 May 2025 | Viewed by 2090

Special Issue Editor

Dr. José V. Frances-Villora

E-Mail Website
Guest Editor
School of Engineering (ETSE), University of Valencia, 46100 Burjassot, Spain
Interests: reconfigurable logic; hardware implementation of signal processing; hardware implementation of machine learning; hardware real-time applications; spiking neural networks; biomedical engineering; EEG processing; ECG processing; automotive applications
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

The continuous modernizing of the characteristics and features of FPGA devices has led to this becoming the natural choice of many final designs. Over the last three decades, these devices have evolved from a few thousand logic blocks to systems-on-chip, integrating billions of transistors. And the current result of this evolution is a set of flexibility and reconfigurability capabilities without precedents, capabilities that enable rapid prototyping, massive parallel designs, and high energy efficiency. Moreover, current FPGAs enable the integration of microprocessor architectures, thus becoming a powerful alternative to create highly efficient computer systems.

Thus, FPGA devices can be reconfigured to implement tailored designs and architectures based on the characteristics of target applications. This is the reason why the use of FPGAs and reconfigurable computing systems are rapidly increasing, bringing new opportunities for engineering across a wide range of applications.

This Special Issue, entitled “Emerging Applications of FPGAs and Reconfigurable Computing System”, is intended to present the latest advances (state-of-the-art contributions) in applications and designs using FPGAs and reconfigurable computing systems, including (but not limited to) the following:

  • Control
  • Image processing
  • Signal processing
  • Cybersecurity
  • Embedded systems
  • Power systems
  • Intelligent systems
  • Machine learning
  • Biomedical applications
  • Robotics
  • IoT applications
  • Telecommunications
  • Networking
  • High-performance computing
  • Reconfigurable computing
  • Particle physics
  • Manufacturing
  • Deep neural networks.

Dr. José V. Frances-Villora
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • FPGA
  • reconfigurable computing
  • embedded systems
  • VHDL
  • high-level synthesis
  • verilog
  • FPGA application

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Published Papers (3 papers)

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Research

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20 pages, 3218 KiB  
Article
An Innovative Digital Pulse Width Modulator and Its Field-Programmable Gate Array Implementation
by Giovanni Bonanno
Electronics 2025, 14(8), 1522; https://doi.org/10.3390/electronics14081522 - 9 Apr 2025
Viewed by 77
Abstract
Digital pulse-width modulation (DPWM)-based controls are characterized by a non-negligible phase delay due to analog-to-digital (ADC) conversion, sampling time, carrier shape, and algorithm computation time. These delays degrade the performance in closed-loop systems, where the bandwidth must be reduced to avoid instability issues [...] Read more.
Digital pulse-width modulation (DPWM)-based controls are characterized by a non-negligible phase delay due to analog-to-digital (ADC) conversion, sampling time, carrier shape, and algorithm computation time. These delays degrade the performance in closed-loop systems, where the bandwidth must be reduced to avoid instability issues due to the reduced closed-loop phase margin. To mitigate these delays, approaches such as utilizing low-latency ADCs or increasing the sampling frequency have been employed. However, these methods are often costly and do not address the fundamental delay issues inherent to DPWMs. In this paper, a novel zero phase-delay DPWM architecture is proposed. This enhanced architecture seamlessly integrates pulse width and frequency modulation to create a programmable derivative action, capable of effectively recovering the DPWM delay. The proposed architecture employs a reliable and straightforward organization, suitable for implementation in commercial field programmable gate array (FPGA). Furthermore, this architecture inherently generates a trigger signal that can be used in numerous power electronic applications to capture the average value in piecewise linear inductor currents. The validity of the proposed architecture is substantiated through simulations and experimental tests. The final implementation is shared in an open-source resource. Full article
(This article belongs to the Special Issue Emerging Applications of FPGAs and Reconfigurable Computing System)
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17 pages, 595 KiB  
Article
Hardware Optimized Modular Reduction
by Alexander Magyari and Yuhua Chen
Electronics 2025, 14(3), 550; https://doi.org/10.3390/electronics14030550 - 29 Jan 2025
Viewed by 678
Abstract
We introduce a modular reduction method that is optimized for hardware and outperforms conventional approaches. By leveraging calculated reduction cycles and combinatorial logic, we achieve a remarkable 30% reduction in power usage, 27% reduction in Configurable Logic Blocks (CLBs), and 42% fewer look-up [...] Read more.
We introduce a modular reduction method that is optimized for hardware and outperforms conventional approaches. By leveraging calculated reduction cycles and combinatorial logic, we achieve a remarkable 30% reduction in power usage, 27% reduction in Configurable Logic Blocks (CLBs), and 42% fewer look-up tables (LUTs) than the conventional implementation. Our Hardware-Optimized Modular Reduction (HOM-R) system can condense a 256-bit input to a four-bit base within a single 250 MHz clock cycle. Further, our method stands out from prevalent techniques, such as Barrett and Montgomery reduction, by eliminating the need for multipliers or dividers, and relying solely on addition and customizable LUTs. This innovative method frees up FPGA resources typically consumed by power-intensive DSPs, offering a compelling low-power, low-latency alternative for diverse design needs. Full article
(This article belongs to the Special Issue Emerging Applications of FPGAs and Reconfigurable Computing System)
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Review

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30 pages, 3046 KiB  
Review
A Survey of Advancements in Scheduling Techniques for Efficient Deep Learning Computations on GPUs
by Rupinder Kaur, Arghavan Asad, Seham Al Abdul Wahid and Farah Mohammadi
Electronics 2025, 14(5), 1048; https://doi.org/10.3390/electronics14051048 - 6 Mar 2025
Viewed by 768
Abstract
This comprehensive survey explores recent advancements in scheduling techniques for efficient deep learning computations on GPUs. The article highlights challenges related to parallel thread execution, resource utilization, and memory latency in GPUs, which can lead to suboptimal performance. The surveyed research focuses on [...] Read more.
This comprehensive survey explores recent advancements in scheduling techniques for efficient deep learning computations on GPUs. The article highlights challenges related to parallel thread execution, resource utilization, and memory latency in GPUs, which can lead to suboptimal performance. The surveyed research focuses on novel scheduling policies to improve memory latency tolerance, exploit parallelism, and enhance GPU resource utilization. Additionally, it explores the integration of prefetching mechanisms, fine-grained warp scheduling, and warp switching strategies to optimize deep learning computations. These techniques demonstrate significant improvements in throughput, memory bank parallelism, and latency reduction. The insights gained from this survey can guide researchers, system designers, and practitioners in developing more efficient and powerful deep learning systems on GPUs. Furthermore, potential future research directions include advanced scheduling techniques, energy efficiency considerations, and the integration of emerging computing technologies. Through continuous advancement in scheduling techniques, the full potential of GPUs can be unlocked for a wide range of applications and domains, including GPU-accelerated deep learning, task scheduling, resource management, memory optimization, and more. Full article
(This article belongs to the Special Issue Emerging Applications of FPGAs and Reconfigurable Computing System)
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