Electronics

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14 pages, 3826 KiB

Open AccessArticle

Full-Swing Nanosecond Delay Hybrid Level Shifter for Time-Critical Applications

by Mohammed Mahaboob Basha, Lachi Reddy Poreddy, Virupakshi Madhurima, Srinivasulu Gundala and Javed Syed

Electronics 2024, 13(13), 2570; https://doi.org/10.3390/electronics13132570 - 30 Jun 2024

Cited by 1 | Viewed by 819

Abstract

A crucial component of digital integrated circuits with numerous power domains is the level shifter (LS). The traditional topologies are currently the mirror LS and cross-coupled LS. For full-swing level conversions from extremely low voltage to the nominal voltage of the supply, ahybrid [...] Read more.

A crucial component of digital integrated circuits with numerous power domains is the level shifter (LS). The traditional topologies are currently the mirror LS and cross-coupled LS. For full-swing level conversions from extremely low voltage to the nominal voltage of the supply, ahybrid LS is proposed in this paper, which is a combination of the current mirror LS and cross-coupled LS with a swing-aware output inverter. The proposed LS circuit is designed to ensure full swing, static current-free, and limited current-contention level conversions by preserving the benefits of the current mirror and cross-coupled LS, and using them to eliminate each other’s shortcomings. The proposed hybrid LS is designed and implemented by using 45-nm technology in Cadence Virtuoso tool. Pass transistors and current limiters with multiple thresholds are included for the suggested LS. The proposed LS provides voltage conversion from 0.10 V to 1.20 V. At alevel-shifting voltage of 0.20 V, the proposed hybrid LS at 1 MHz input frequency demonstrates a delay of 8.38 ns, an average power consumption of 3.81 µW, and an energy per transition of 26.64 fJ. Additionally, the suggested LS has low delay, good supply voltage scaling, and delay scalability. Full article

(This article belongs to the Special Issue Design of Low-Voltage and Low-Power Integrated Circuits)

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14 pages, 6849 KiB

Open AccessArticle

Reconfigurable Low-Power CMOS Amplifier Stages for Broadband Impedance Spectroscopy

by Jorge Pérez-Bailón, Belén Calvo-López and Nicolás Medrano

Electronics 2024, 13(9), 1674; https://doi.org/10.3390/electronics13091674 - 26 Apr 2024

Cited by 1 | Viewed by 1131

Abstract

In this paper, a fully differential amplifier is proposed in a 1.8 V-0.18 μm CMOS (Complementary Metal-Oxide-Semiconductor) technology, which can accommodate both voltage (V-mode) and current (C-mode) inputs. Post-layout simulation results show a fixed gain amplifier exhibiting a 26 dB (V-mode)/89 dBΩ (C-mode) [...] Read more.

In this paper, a fully differential amplifier is proposed in a 1.8 V-0.18 μm CMOS (Complementary Metal-Oxide-Semiconductor) technology, which can accommodate both voltage (V-mode) and current (C-mode) inputs. Post-layout simulation results show a fixed gain amplifier exhibiting a 26 dB (V-mode)/89 dBΩ (C-mode) gain and a programmable gain amplifier featuring a 6–26 dB gain, overall yielding a 26.8–46.4 dB dB (V-mode)/89.6–109.2 dBΩ (C-mode) programmable gain range, with a 100 MHz bandwidth and a power and area consumption of 360.5 µW and 0.0177 mm², respectively. This amplifier has been designed considering the constraints and specifications (including low voltage, low power, reduced noise and high common mode rejection ratio) for its use in an analogue Lock-in-based Frequency Response Analyser-Impedance Spectroscopy (FRA-IS) device. The proposed design introduces a novel fully differential open-loop structure based on a transconductance–transimpedance (TC-TI) topology for high performance applications with a broad programmable bandwidth. To compare this work, different figures of merit (FoMs) are introduced as well as a comparison table with other simulated and experimental results, reporting an overall better performance in terms of gain, frequency and power-area consumption. Full article

(This article belongs to the Special Issue Design of Low-Voltage and Low-Power Integrated Circuits)

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11 pages, 4429 KiB

Open AccessArticle

Input Voltage-Level Driven Split-Input Inverter Level Shifter for Nanoscale Applications

by Srinivasulu Gundala, Mohammed Mahaboob Basha, Virupakshi Madhurima and Ovidiu Petru Stan

Electronics 2024, 13(6), 1115; https://doi.org/10.3390/electronics13061115 - 18 Mar 2024

Cited by 4 | Viewed by 1192

Abstract

A level shifter (LS) appears to be highly efficient and effective in solving voltage contentions between deep sub-threshold and core voltage levels. An input voltage-level driven split-input inverter that can create common unconnected PMOS and NMOS transistors for the input inverter is proposed, [...] Read more.

A level shifter (LS) appears to be highly efficient and effective in solving voltage contentions between deep sub-threshold and core voltage levels. An input voltage-level driven split-input inverter that can create common unconnected PMOS and NMOS transistors for the input inverter is proposed, which is powered and used at the input stage to achieve maximum conversion efficiency. Layout and simulation results across different corners have demonstrated that the proposed LS is highly useful for cutting-edge nanoscale applications. It can up-convert voltage from 0.2 V to 1.2 V and down-convert from 1.2 V to 0.2 V @ 1 MHz input pulse, with a level-up or level-down mean switching delay of 1.3 ns, and a power of 9.5 nW. Moreover, the LS occupies an area of 8 μm², which is a reasonably compact size compared to the typical LS designs. Overall, the proposed voltage LS design is an efficient and effective solution that could have an ample range of applications in IoT and biomedical, wireless sensor networks. Full article

(This article belongs to the Special Issue Design of Low-Voltage and Low-Power Integrated Circuits)

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12 pages, 5827 KiB

Open AccessArticle

A 10.5 ppm/°C Modified Sub-1 V Bandgap in 28 nm CMOS Technology with Only Two Operating Points

by Rajasekhar Nagulapalli, Nabil Yassine, Amr A. Tammam, Steve Barker and Khaled Hayatleh

Electronics 2024, 13(6), 1011; https://doi.org/10.3390/electronics13061011 - 7 Mar 2024

Cited by 2 | Viewed by 1449

Abstract

Reference voltage/current generation is essential to the Analog circuit design. There have been several ways to generate quality reference voltage using bandgap reference (BGR) and there are mainly two types: current mode and voltage mode. The current-mode bandgap reference (CBGR) is widely accepted [...] Read more.

Reference voltage/current generation is essential to the Analog circuit design. There have been several ways to generate quality reference voltage using bandgap reference (BGR) and there are mainly two types: current mode and voltage mode. The current-mode bandgap reference (CBGR) is widely accepted in industry due to having an output voltage which is below 1 V. However, its drawbacks include a lack of proportional to absolute temperature (PTAT) current availability, a large silicon area, multiple operating points, and a large temperature coefficient (TC). In this paper, various operating points are explained in detail with diagrams. Similar to the conventional voltage mode bandgap reference (VBGR) circuits, modifications of the existing circuits with only two operating points have also been proposed. Moreover, the proposed BGR occupies a much smaller area due to eliminating the complimentary to absolute temperature (CTAT) current-generating resistor. A new self-biased opamp was introduced to operate from a 1.05 V supply, reducing systematic offset and TC of the BGR. The proposed solution has been implemented in 28 nm CMOS TSMC technology, and extraction simulations were performed to prove the robustness of the proposed circuit. The targeted mean BGR output is 500 mV, and across the industrial temperature range (−40 to 125 °C), the simulated TC is approximately 10.5 ppm/°C. The integrated output noise within the observable frequency band is 19.6 µV (rms). A 200-point Monte Carlo simulation displays a histogram with a 2.6 mV accuracy of 1.2% (±3-sigma). The proposed BGR circuit consumes 32.8 µW of power from a 1.05 V supply in a fast process and hot (125 °C) corner. It occupies a silicon area of 81 × 42 µm (including capacitors). This design can aim for use in biomedical and sensor applications. Full article

(This article belongs to the Special Issue Design of Low-Voltage and Low-Power Integrated Circuits)

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11 pages, 3846 KiB

Open AccessCommunication

A 0.5 V Nanowatt Biquadratic Low-Pass Filter with Tunable Quality Factor for Electronic Cochlea Applications

by Jacek Jakusz and Waldemar Jendernalik

Electronics 2024, 13(2), 399; https://doi.org/10.3390/electronics13020399 - 18 Jan 2024

Cited by 1 | Viewed by 860

Abstract

A novel implementation of an analogue low-power, second-order, low-pass filter with tunable quality factor (Q) is presented and discussed. The filter feature is a relatively simple, buffer-based, circuit network consisting of eleven transistors operating in a subthreshold region. Q tuning is [...] Read more.

A novel implementation of an analogue low-power, second-order, low-pass filter with tunable quality factor (Q) is presented and discussed. The filter feature is a relatively simple, buffer-based, circuit network consisting of eleven transistors operating in a subthreshold region. Q tuning is accomplished by injecting direct current into a network node, which changes the output resistance of the transistors and, as a result, modifies the filter network’s loss, and thus its Q. Q tuning is independent of a filter cut-off frequency (ω₀). The filter, with a nominal ω₀ of 1 kHz, was fabricated using a 0.18 µm CMOS technology, and features a Q range of 2–11, power consumption of up to 52 nW, and a 59 dB dynamic range when using a 0.5 V supply. The ω₀ can be tuned from 0.5 to 2.5 kHz using a traditional method by changing the transistor transconductances, but this process partially affects the quality factor. Full article

(This article belongs to the Special Issue Design of Low-Voltage and Low-Power Integrated Circuits)

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12 pages, 3603 KiB

Open AccessArticle

Implementation of High-Speed Compact Level-Up Shifter for Nano-Scale Applications

by Muppidi Venkata Sudhakar and Ovidiu Petru Stan

Electronics 2023, 12(24), 5015; https://doi.org/10.3390/electronics12245015 - 15 Dec 2023

Cited by 3 | Viewed by 1753

Abstract

The objective of this study is to present a level shifter architecture that utilizes a pair of inverters and a Wilson current mirror to reduce power consumption while improving voltage shifting capabilities. We introduce novel components such as super-cut-off pull-down and stacked pull-up [...] Read more.

The objective of this study is to present a level shifter architecture that utilizes a pair of inverters and a Wilson current mirror to reduce power consumption while improving voltage shifting capabilities. We introduce novel components such as super-cut-off pull-down and stacked pull-up networks to effectively minimize leakage power. Our design leverages multi-threshold CMOS (MTCMOS) technology, incorporating sleep transistors to boost operational speed, decrease power consumption, and reduce the physical footprint. The proposed circuit is engineered to step up voltage levels, ranging from a mere 0.4 V to a substantial 1.2 V. Through extensive optimization of performance parameters, including power efficiency, delay, and area utilization, we have tailored this design to cater specifically to the demands of nano-scale applications. Key results from our research reveal that the average active power consumption for “level-up” shifts is impressively low at 48.5 nW, with an average latency of a mere 1.58 ns for 1 MHz transmission frequencies. Post-layout modeling demonstrates that our suggested design occupies a compact area of just 9.97 µm². These findings were meticulously modeled using Cadence Virtuoso with 45 nm processes. Furthermore, our research highlights the substantial advancements achieved when compared to previous methods. The proposed design boasts a threefold increase in operational speed and delivers significant savings in both area and power consumption. These outcomes have far-reaching implications for emerging technologies and applications in the field. Full article

(This article belongs to the Special Issue Design of Low-Voltage and Low-Power Integrated Circuits)

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13 pages, 2182 KiB

Open AccessArticle

Three-Stage CMOS LDO with Optimized Power and Dynamic Performance for Portable Devices

by Andrés Serrano-Reyes, María Teresa Sanz-Pascual and Belén Calvo-López

Electronics 2023, 12(22), 4638; https://doi.org/10.3390/electronics12224638 - 13 Nov 2023

Viewed by 2114

Abstract

Low dropout (LDO) regulators are crucial components in power management systems for portable, i.e., battery-powered, devices. However, the design of LDO regulators presents a challenging trade-off between dynamic performance, power consumption, and area efficiency. This paper proposes a novel LDO regulator design that [...] Read more.

Low dropout (LDO) regulators are crucial components in power management systems for portable, i.e., battery-powered, devices. However, the design of LDO regulators presents a challenging trade-off between dynamic performance, power consumption, and area efficiency. This paper proposes a novel LDO regulator design that addresses these challenges by employing the reverse nested Miller compensation (RNMC) with current buffers embedded within the own class AB high gain error amplifier (EA) topology, and a time response enhancement circuit (TREC). High-gain (>120 dB) class AB EA renders good regulation performance with enhanced dynamic performance. The proposed compensation scheme improves the gain bandwidth product (GBW) and stability of the regulator, while the TREC reduces overshoot and undershoot during load transients without additional steady-state power consumption. Post-layout simulations confirm the robustness of the proposed 180 nm CMOS design across a wide range of operating conditions, achieving a regulated output voltage of 1.8 V with 100 mV dropout, good load and line regulating performance, and excellent load transient response with reduced undershoot and overshoot at minimum power (

I_{q}

= 13.8 μA) and area (314 μm × 150 μm) consumption. The proposed LDO regulator thus offers a compelling compromise between power consumption, area efficiency, and dynamic performance, making it highly suitable for portable applications. Full article

(This article belongs to the Special Issue Design of Low-Voltage and Low-Power Integrated Circuits)

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16 pages, 11297 KiB

Open AccessArticle

Multi-Layer QCA Shift Registers and Wiring Structure for LFSR in Stream Cipher with Low Energy Dissipation in Quantum Nanotechnology

by Jun-Cheol Jeon

Electronics 2023, 12(19), 4093; https://doi.org/10.3390/electronics12194093 - 29 Sep 2023

Cited by 9 | Viewed by 1018

Abstract

Pseudorandom numbers (PRN) are used in various cryptographic applications, such as cryptographic protocols and stream ciphers. The most efficient hardware method used to generate PRNs is to use a Linear Feedback Shift Register (LFSR) structure, which is generally composed of a Shift Register [...] Read more.

Pseudorandom numbers (PRN) are used in various cryptographic applications, such as cryptographic protocols and stream ciphers. The most efficient hardware method used to generate PRNs is to use a Linear Feedback Shift Register (LFSR) structure, which is generally composed of a Shift Register (SR) and an XOR gate. The most important factors in designing the entire LFSR structure are design cost and energy efficiency, which are highly dependent on the SR structure. In the proposed study, the structural characteristics and problems of existing various types of SRs are presented, and new multi-layered serial-in-serial-out (SISO) and parallel-in-parallel-out (PIPO) SRs are proposed. In addition, we compare and analyze the area-time complexity, design cost, and energy dissipation through simulation using QCADesigner and QCADesigner-E. As a result, the proposed SISO and PIPO showed a performance improvement of more than 27% compared to the existing structure, which showed the best performance, and showed energy dissipation reduction rates of about 65% and 59%, respectively. In particular, we proposed multi-layer wiring that can reduce energy dissipation and verified through simulation that it can save up to 24.8%. Full article

(This article belongs to the Special Issue Design of Low-Voltage and Low-Power Integrated Circuits)

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