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Electronics
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Embedded Systems: Design, Challenges and Trends
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Embedded Systems: Design, Challenges and Trends

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Computer Science & Engineering".

Deadline for manuscript submissions: closed (31 December 2021) | Viewed by 14258

Special Issue Editor

Dr. Jean-Christophe Prévotet

E-Mail Website
Guest Editor
Institut National des Sciences Appliquées de Rennes—IETR-INSA, Rennes, France
Interests: reconfigurable computing; embedded systems; virtualization; IoT; communication systems; hardware design; FPGAs

Special Issue Information

Dear Colleagues,

One of the major issues in designing embedded systems consists in providing more computing power in smaller and smaller devices, while guaranteeing energy efficiency and a high performance level. Other issues are related to the new usage of these systems, such as the possibility to transparently and concurrently execute many applications or operating systems, sometimes in real-time.

The scope of this Special Issue encompasses the full stack of technologies behind modern embedded applications: design of embedded devices, development of software, integration within a larger system, deployment, and management.

This Special Issue welcomes contributions on novel and inspiring applications of embedded systems, including, but not limited to, the following domains:

  • Real-time embedded systems design: energy management, dynamic reconfiguration, QoS, heterogeneity and interoperability
  • Virtualization of embedded systems
  • Hardware/software co-design, synthesis, reconfigurable hardware, real-time network- and system on chip
  • Embedded systems security
  • Embedded systems performance
  • Novel and inspiring applications of embedded systems

Dr. Jean-Christophe Prévotet
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Published Papers (5 papers)

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Research

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10 pages, 308 KiB  
Article
Survey of Software-Implemented Soft Error Protection
by Yohan Ko
Electronics 2022, 11(3), 456; https://doi.org/10.3390/electronics11030456 - 3 Feb 2022
Viewed by 1780
Abstract
As soft errors are important design concerns in embedded systems, several schemes have been presented to protect embedded systems against them. Embedded systems can be protected by hardware redundancy; however, hardware-based protections cannot provide flexible protection due to hardware-only protection modifications. Further, they [...] Read more.
As soft errors are important design concerns in embedded systems, several schemes have been presented to protect embedded systems against them. Embedded systems can be protected by hardware redundancy; however, hardware-based protections cannot provide flexible protection due to hardware-only protection modifications. Further, they incur significant overheads in terms of area, performance, and power consumption. Therefore, hardware redundancy techniques are not appropriate for resource-constrained embedded systems. On the other hand, software-based protection techniques can be an attractive alternative to protect embedded systems, especially specific-purpose architectures. This manuscript categorizes and compares software-based redundancy techniques for general-purpose and specific-purpose processors, such as VLIW (Very Long Instruction Word) and CGRA (Coarse-Grained Reconfigurable Architectures). Full article
(This article belongs to the Special Issue Embedded Systems: Design, Challenges and Trends)
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15 pages, 4322 KiB  
Article
HAL-ASOS Accelerator Model: Evolutive Elasticity by Design
by Vítor Silva, Paulo Pinto, Paulo Cardoso, Jorge Cabral and Adriano Tavares
Electronics 2021, 10(17), 2078; https://doi.org/10.3390/electronics10172078 - 27 Aug 2021
Viewed by 1949
Abstract
To address the integration of software threads and hardware accelerators into the Linux Operating System (OS) programming models, an accelerator architecture is proposed, based on micro-programmable hardware system calls, which fully export these resources into the Linux OS user-space through a design-specific virtual [...] Read more.
To address the integration of software threads and hardware accelerators into the Linux Operating System (OS) programming models, an accelerator architecture is proposed, based on micro-programmable hardware system calls, which fully export these resources into the Linux OS user-space through a design-specific virtual file system. The proposed HAL-ASOS accelerator model is split into a user-defined Hardware Task and a parameterizable Hardware Kernel with three differentiated transfer channels, aiming to explore distinct BUS technology interfaces and promote the accelerator to a first-class computing unit. This paper focuses on the Hardware Kernel and mainly its microcode control unit, which will leverage the elasticity to naturally evolve with Linux OS through key differentiating capabilities of field programmable gate arrays (FPGAs) when compared to the state of the art. To comply with the evolutive nature of Linux OS, or any Hardware Task incremental features, the proposed model generates page-faults signaling runtime errors that are handled at the kernel level as part of the virtual file system runtime. To evaluate the accelerator model’s programmability and its performance, a client-side application based on the AES 128-bit algorithm was implemented. Experiments demonstrate a flexible design approach in terms of hardware and software reconfiguration and significant performance increases consistent with rising processing demands or clock design frequencies. Full article
(This article belongs to the Special Issue Embedded Systems: Design, Challenges and Trends)
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15 pages, 621 KiB  
Article
Fixed-Point Arithmetic Unit with a Scaling Mechanism for FPGA-Based Embedded Systems
by Andrzej Przybył
Electronics 2021, 10(10), 1164; https://doi.org/10.3390/electronics10101164 - 13 May 2021
Cited by 8 | Viewed by 2561
Abstract
The work describes the new architecture of a fixed-point arithmetic unit. It is based on the use of integer arithmetic operations for which the information about the scale of the processed numbers is contained in the binary code of the arithmetic instruction being [...] Read more.
The work describes the new architecture of a fixed-point arithmetic unit. It is based on the use of integer arithmetic operations for which the information about the scale of the processed numbers is contained in the binary code of the arithmetic instruction being executed. Therefore, this approach is different from the typical way of implementing fixed-point operations on standard processors. The presented solution is also significantly different from the one used in floating-point arithmetic, as the decision to determine the appropriate scale is made at the stage of compiling the code and not during its execution. As a result, the real-time processing of real numbers is simplified and, therefore, faster. The described method provides a better ratio of the processing efficiency to the complexity of the digital system than other methods. In particular, the advantage of using the described method in FPGA-based embedded control systems should be indicated. Experimental tests on an industrial servo-drive confirm the correctness of the described solution. Full article
(This article belongs to the Special Issue Embedded Systems: Design, Challenges and Trends)
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15 pages, 476 KiB  
Article
Optimizing Computer Networks Communication with the Band Collocation Problem: A Variable Neighborhood Search Approach
by Isaac Lozano-Osorio, Jesus Sanchez-Oro, Miguel Ángel Rodriguez-Garcia and Abraham Duarte
Electronics 2020, 9(11), 1860; https://doi.org/10.3390/electronics9111860 - 5 Nov 2020
Cited by 4 | Viewed by 2501
Abstract
The Band Collocation Problem appears in the context of problems for optimizing telecommunication networks with the aim of solving some concerns related to the original Bandpass Problem and to present a more realistic approximation to be solved. This problem is interesting to optimize [...] Read more.
The Band Collocation Problem appears in the context of problems for optimizing telecommunication networks with the aim of solving some concerns related to the original Bandpass Problem and to present a more realistic approximation to be solved. This problem is interesting to optimize the cost of networks with several devices connected, such as networks with several embedded systems transmitting information among them. Despite the real-world applications of this problem, it has been mostly ignored from a heuristic point of view, with the Simulated Annealing algorithm being the best method found in the literature. In this work, three Variable Neighborhood Search (VNS) variants are presented, as well as three neighborhood structures and a novel optimization based on Least Recently Used cache, which allows the algorithm to perform an efficient evaluation of the objective function. The extensive experimental results section shows the superiority of the proposal with respect to the best previous method found in the state-of-the-art, emerging VNS as the most competitive method to deal with the Band Collocation Problem. Full article
(This article belongs to the Special Issue Embedded Systems: Design, Challenges and Trends)
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Review

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16 pages, 5602 KiB  
Review
The Role of Mixed Criticality Technology in Industry 4.0
by José Simó, Patricia Balbastre, Juan Francisco Blanes, José-Luis Poza-Luján and Ana Guasque
Electronics 2021, 10(3), 226; https://doi.org/10.3390/electronics10030226 - 20 Jan 2021
Cited by 10 | Viewed by 3022
Abstract
Embedded systems used in critical systems, such as aeronautics, have undergone continuous evolution in recent years. In this evolution, many of the functionalities offered by these systems have been adapted through the introduction of network services that achieve high levels of interconnectivity. The [...] Read more.
Embedded systems used in critical systems, such as aeronautics, have undergone continuous evolution in recent years. In this evolution, many of the functionalities offered by these systems have been adapted through the introduction of network services that achieve high levels of interconnectivity. The high availability of access to communications networks has enabled the development of new applications that introduce control functions with higher levels of intelligence and adaptation. In these applications, it is necessary to manage different components of an application according to their levels of criticality. The concept of “Industry 4.0” has recently emerged to describe high levels of automation and flexibility in production. The digitization and extensive use of information technologies has become the key to industrial systems. Due to their growing importance and social impact, industrial systems have become part of the systems that are considered critical. This evolution of industrial systems forces the appearance of new technical requirements for software architectures that enable the consolidation of multiple applications in common hardware platforms—including those of different criticality levels. These enabling technologies, together with use of reference models and standardization facilitate the effective transition to this approach. This article analyses the structure of Industry 4.0 systems providing a comprehensive review of existing techniques. The levels and mechanisms of interaction between components are analyzed while considering the impact that the handling of multiple levels of criticality has on the architecture itself—and on the functionalities of the support middleware. Finally, this paper outcomes some of the challenges from a technological and research point of view that the authors identify as crucial for the successful development of these technologies. Full article
(This article belongs to the Special Issue Embedded Systems: Design, Challenges and Trends)
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