Research Trends in Network-on-Chip Architectures and Selected Papers from NoCArc 2020
A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).
Deadline for manuscript submissions: closed (30 April 2021) | Viewed by 826
Special Issue Editors
Interests: interconnection network; Network-on-Chip (NoC); multi-chip system integration; wireless interconnects; data center networks
Special Issues, Collections and Topics in MDPI journals
Interests: Network-on-Chip (NoC); wireless interconnects; manycore architectures; DNN accelerators
Special Issue Information
Dear colleagues,
With the advancement in both computing architectures and process technology, many-core architectures can put thousands of cores into a single chip. This integration opens up a plethora of challenges, e.g., in terms of specialization and energy-focused implementations, and supports the spread of various applications and computational paradigms, ranging from multiprocessing to reconfigurable computing, from quantum computing to the emerging area of neuromorphic computing. The Network-on-Chip (NoC) design paradigm, based on a modular packet-switched mechanism, can address many of the on-chip communication issues such as performance limitations of long interconnects, the integration of a large number of PEs on a chip, or heterogeneous workloads.
The goal of this Special Issue is to curate innovative ideas and solutions related to the design and implementation of NoCs. Accepted papers from NoCArc 2020 are invited to be submitted with substantial extensions. Submissions of contributions not presented at the Workshopare also welcome if they are related to the themes of the Special Issue.
Dr. Amlan GangulyDr. Sergi Abadal
Dr. Salvatore Monteleone
Guest Editor
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