Reliability Issues in Advanced Transistor Nodes, Second Edition

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "E:Engineering and Technology".

Deadline for manuscript submissions: 15 March 2025 | Viewed by 32

Special Issue Editor


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Guest Editor
Interuniversity Microelectronics Centre (IMEC), 3001 Leuven, Belgium
Interests: transistor reliability; device and degradation modeling; hot-carrier degradation; bias temperature instability; time dependent dielectric breakdown; 2D materials; SiC; tunneling phenomena
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Special Issue Information

Dear Colleagues,

Microelectronics, based on metal-oxide-semiconductor field-effect transistors (MOSFETs), pervade all aspects of our lives and enable progress in virtually all fields of humankind. Although transistor scaling has been actively exploited for more than 50 years, MOSFET technology still requires at least 10–15 years of development. To enable further progress in mobile electronic components and gadgets, novel transistor architectures, such as fin, nanowire, nanosheet, forksheet, and complementary FET structures, have recently been introduced. These advanced transistor nodes are designed to ensure low OFF currents and long battery life.

However, any further developments and progress can only be achieved by acquiring and retaining a thorough understanding of the microscopic physics underlying the behavior of novel devices and materials. Unlike the more tangible product parameters, such as performance or power consumption, reliability specifications are often neither disclosed nor considered by the typical end-user. In practice, however, reliability is the essential metric required for the introduction of each new transistor node. Accordingly, this Special Issue seeks to showcase research papers and review articles that focus on the most detrimental reliability concerns plaguing modern transistors such as hot-carrier degradation, self-heating, bias-temperature instability, OFF-state stress, and time-dependent dielectric breakdown. Special attention will be paid to (i) experimental studies/characterization and (ii) modeling of these degradation mechanisms, as well as (iii) pathways to device architecture optimization targeting alleviation of these parasitic effects.

We look forward to receiving valuable submissions!

Dr. Stanislav Tyaginov
Guest Editor

Manuscript Submission Information

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Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2600 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • reliability issues
  • hot-carrier degradation
  • self-heating
  • bias temperature instability
  • time dependent dielectric breakdown
  • defects
  • characterization of reliability issues
  • modeling of reliability issues
  • novel transistor architectures
  • finFET
  • NWFET
  • NSFET
  • FSFET
  • CFET

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Published Papers

This special issue is now open for submission.
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