Reliability Issues in Advanced Transistor Nodes, Second Edition

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "E:Engineering and Technology".

Deadline for manuscript submissions: 15 March 2025 | Viewed by 619

Special Issue Editor


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Guest Editor
Interuniversity Microelectronics Centre (IMEC), 3001 Leuven, Belgium
Interests: transistor reliability; device and degradation modeling; hot-carrier degradation; bias temperature instability; time dependent dielectric breakdown; 2D materials; SiC; tunneling phenomena
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Special Issue Information

Dear Colleagues,

Microelectronics, based on metal-oxide-semiconductor field-effect transistors (MOSFETs), pervade all aspects of our lives and enable progress in virtually all fields of humankind. Although transistor scaling has been actively exploited for more than 50 years, MOSFET technology still requires at least 10–15 years of development. To enable further progress in mobile electronic components and gadgets, novel transistor architectures, such as fin, nanowire, nanosheet, forksheet, and complementary FET structures, have recently been introduced. These advanced transistor nodes are designed to ensure low OFF currents and long battery life.

However, any further developments and progress can only be achieved by acquiring and retaining a thorough understanding of the microscopic physics underlying the behavior of novel devices and materials. Unlike the more tangible product parameters, such as performance or power consumption, reliability specifications are often neither disclosed nor considered by the typical end-user. In practice, however, reliability is the essential metric required for the introduction of each new transistor node. Accordingly, this Special Issue seeks to showcase research papers and review articles that focus on the most detrimental reliability concerns plaguing modern transistors such as hot-carrier degradation, self-heating, bias-temperature instability, OFF-state stress, and time-dependent dielectric breakdown. Special attention will be paid to (i) experimental studies/characterization and (ii) modeling of these degradation mechanisms, as well as (iii) pathways to device architecture optimization targeting alleviation of these parasitic effects.

We look forward to receiving valuable submissions!

Dr. Stanislav Tyaginov
Guest Editor

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Keywords

  • reliability issues
  • hot-carrier degradation
  • self-heating
  • bias temperature instability
  • time dependent dielectric breakdown
  • defects
  • characterization of reliability issues
  • modeling of reliability issues
  • novel transistor architectures
  • finFET
  • NWFET
  • NSFET
  • FSFET
  • CFET

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Published Papers (1 paper)

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Research

13 pages, 3971 KiB  
Article
Charge Trapping and Emission during Bias Temperature Stressing of Schottky Gate GaN-on-Silicon HEMT Structures Targeting RF/mm Wave Power Amplifiers
by Barry O’Sullivan, Aarti Rathi, Alireza Alian, Sachin Yadav, Hao Yu, Arturo Sibaja-Hernandez, Uthayasankaran Peralagu, Bertrand Parvais, Adrian Chasin and Nadine Collaert
Micromachines 2024, 15(8), 951; https://doi.org/10.3390/mi15080951 - 24 Jul 2024
Viewed by 494
Abstract
For operation as power amplifiers in RF applications, high electron mobility transistor (HEMT) structures are subjected to a range of bias conditions, applied at both the gate and drain terminals, as the device is biased from the OFF- to ON-state conditions. The stability [...] Read more.
For operation as power amplifiers in RF applications, high electron mobility transistor (HEMT) structures are subjected to a range of bias conditions, applied at both the gate and drain terminals, as the device is biased from the OFF- to ON-state conditions. The stability of the device threshold voltage (Vt) condition is imperative from a circuit-design perspective and is the focus of this study, where stresses in both the ON and OFF states are explored. We see rapid positive threshold voltage increases under negative bias stress and subsequent recovery (i.e., Vt reduces), whereas conversely, we see a negative Vt shift under positive stress and Vt increase during the subsequent relaxation phase. These effects are correlated with the thickness of the GaN layer and ultimately result from the deep carbon-acceptor levels in the C-GaN back barrier incorporated to screen the buffer between the silicon substrate and the epitaxially grown GaN layer. Methods to mitigate this effect are explored, and the consequences are discussed. Full article
(This article belongs to the Special Issue Reliability Issues in Advanced Transistor Nodes, Second Edition)
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