Search Results (6)

This study focuses on the evaluation of electrical stress limit capability for 3D-packaged memory (256 M × 72-bit DDR3 SDRAM) (Shanghai Fudan Microelectronics Group Co., Ltd., Shanghai, China). Guided by Reliability Enhancement Theory, this study presents a meticulously designed comprehensive test profile that incorporates critical stress parameters, including supply voltage, input clock frequency, electrostatic discharge (ESD) sensitivity, and electrical endurance. Explicit criteria for stress selection, upper/lower bounds, step increments, and duration are established. A dedicated test platform is constructed, integrating automated test equipment (ATE) and ESD sensitivity analyzers with detailed specifications on device selection criteria and operational principles. The functional performance testing methodology is systematically investigated, covering test platform configuration, initialization protocols, parametric testing procedures, functional verification, and acceptance criteria. Extreme-condition experiments—including supply voltage margining, input clock frequency tolerance, ESD sensitivity characterization, and accelerated electrical endurance testing—are conducted to quantify operational and destructive limits. The findings provide critical theoretical insights and practical guidelines for the design optimization, quality control, and reliability enhancement of 3D-packaged memory devices. Full article

The rise of 3D heterogeneous packaging holds promise for increased performance in applications such as AI by bringing compute and memory modules into close proximity. This increased performance comes with increased thermal management challenges. This research explores the use of thermal sensing and load throttling combined with federated computation to manage localized internal heating in a multi-3D chip package. The overall concept is that individual chiplets may heat at different rates due to operational and geometric factors. Shifting computational loads from hot to cooler chiplets can prevent local overheating while maintaining overall computational output. This concept is verified with experiments in a low-cost test vehicle. The test vehicle mimics a 3D chiplet stack with a tightly stacked assembly of SoC devices. These devices can sense and report internal temperature and dynamically adjust frequency. The configuration is for ESP32-S3 microcontrollers to work on a federated computational task, while reporting internal temperature to a host controller. The tight packing of processors causes temperatures to rise, with those internal to the stack rising more quickly than external ones. With real-time temperature monitoring, when the temperatures exceed a threshold, the AI system reduces the processor frequency, i.e., throttles the processor, to save power and dynamically shifts part of the workload to other ESP32-S3s with lower temperatures. This approach maximizes overall efficiency while maintaining thermal safety without compromising computational power. Experimental results with up to six processors confirm the validity of the concept. Full article

The rapid advancement of 3D packaging technology has emerged as a key solution to overcome the scaling-down limitation of advanced memory and logic devices. Redistribution layer (RDL) fabrication, a critical process in 3D packaging, requires the use of polyimide (PI) films with thicknesses in the micrometer range. However, these polyimide films present surface topography variations in the range of hundreds of nanometers, necessitating chemical–mechanical planarization (CMP) to achieve nanometer-level surface flatness. Polyimide films, composed of copolymers of pyromellitimide and diphenyl ether, possess strong covalent bonds such as C–C, C–O, C=O, and C–N, leading to inherently low polishing rates during CMP. To address this challenge, the introduction of Fe(NO₃)₃ into CMP slurries has been proposed as a polishing rate accelerator. During CMP, this Fe(NO₃)₃ deformed the surface of a polyimide film into strongly positively charged 1,2,4,5-benzenetetracarbonyliron and weakly negatively charged 4,4′-oxydianiline (ODA). The chemically dominant polishing rate enhanced with the concentration of the Fe(NO₃)₃ due to accelerated surface interactions. However, higher Fe(NO₃)₃ concentrations reduce the attractive electrostatic force between the positively charged wet ceria abrasives and the negatively charged deformed surface of the polyimide film, thereby decreasing the mechanically dominant polishing rate. A comprehensive investigation of the chemical and mechanical polishing rate dynamics revealed that the optimal Fe(NO₃)₃ concentration to achieve the maximum polyimide film removal rate was 0.05 wt%. Full article

As the core carrier of information storage, a semiconductor memory device is a basic product with a large volume that is widespread in the integrated circuit industry. With the rapid development of semiconductor manufacturing processes and materials, the internal structure of memory has gradually shifted from a 2D planar packaging structure to a 3D packaging structure to meet industry demands for high-frequency, high-speed, and large-capacity devices with low power consumption. However, advanced 3D packaging technology can pose some reliability risks, making devices prone to failure, especially when used in harsh environmental conditions, including temperature changes, high temperature and humidity levels, and mechanical stress. In this paper, the authors introduce the typical structure characteristics of 3D packaged memory; analyze the reasons for device failure caused by stress; summarize current research methods that utilize temperature, mechanical and hygrothermal theories, and failure models; and present future challenges and directions regarding the reliability research of 3D packaged memory. Full article

Encoding sensor data into a map is a problem that must be undertaken by any robotic agent operating in unknown or uncertain environments, and real-time updates are crucial to safe planning and control. Most modern robotic sensors produce some form of depth data or point cloud information that is only useful to the agent after being processed into the appropriate data structure, oftentimes an occupancy map. However, as the quality of sensor technology improves, so does the magnitude of the input data, which can creates a problem when trying to construct occupancy maps in real-time. Populating such an occupancy map using these dense point clouds can quickly become an expensive process, and many robotic agents have limited onboard computational bandwidth and memory. This results in delayed map updates and reduced operational performance in dynamic environments where real-time information is crucial for safe operation. However, while many modern robotic agents are still relatively limited by the power of onboard central processing units (CPUs), many platforms are gaining access to onboard graphics processing units (GPUs), and these resources remain underutilised with respect to the problem of occupancy mapping. We propose a novel probabilistic mapping solution that leverages a combination of OpenVDB, NanoVDB, and Nvidia’s Compute Unified Device Architecture (CUDA) to encode dense point clouds into OpenVDB data structures, leveraging the parallel compute strength of GPUs to provide significant speed advantages and further free up resources for tasks that cannot as easily be performed in parallel. An evaluation of our solution is provided, with performance benchmarks provided for both a laptop and a low power single board computer with onboard GPU. Similar performance improvements should be accessible on any system with access to a CUDA-compatible GPU. Additionally, our library provides the means to simulate one or more sensors on an agent operating within a randomly generated 3D-grid environment and create a live map for the purposes of evaluating planning and control techniques and for training agents via deep reinforcement learning. We also provide interface packages for the Robotic Operating System (ROS1) and the Robotic Operating System 2 (ROS2), and a ROS2 visualisation (RVIZ2) plugin for the underlying OpenVDB data structure. Full article

In 3D packaging memory devices, solder joints are critical links between the chip and the printed circuit board (PCB). Under severe working conditions, cracks inevitably occur due to thermal shock. If cracks grow in the solder joint, the chip will be disconnected with the PCB, causing its function failure. In this paper, the reliability of solder joints under thermal shock are evaluated for 3D packaging memory devices by means of the SEM and finite element analysis. As microscopically studied by the SEM, it is found out that the main failure mechanism of solder joints in such test is the thermal fatigue failure of solder joints. Finite element analysis shows that cracks are caused by the accumulation of plastic work and creep strain. The initiation and growth of cracks are mainly influenced by the inelastic strain accumulation. The trends of cracks are influenced by the difference between the coefficient of thermal expansion (CTE) of epoxy resin and that of the chip. Full article