Search Results (206)

Low-frequency (LF) time code timing technology holds significant importance in civilian applications such as radio-controlled clocks. This study focuses on the design and implementation of a high-precision Binary Phase Code (BPC) LF time code signal generator. A generator system was constructed, demonstrating good stability, superior resolution, and flexible adjustment capabilities for both amplitude and phase. The system employs an ARM + FPGA cooperative architecture: the ARM processor is responsible for parsing and scheduling the time code data, while the FPGA implements carrier wave generation and high-precision digital modulation. This digital processing is combined with analog circuitry to achieve digital-to-analog (D/A) signal conversion. Compared to traditional methods, carrier generation is achieved using Direct Digital Synthesis (DDS) technology. Digital modulation techniques enable the precise control of the modulation depth (adjustable between 70% and 90%) and phase (with a resolution of 1 ns). A sliding window algorithm was utilized for time difference calculation and compensation. Testing confirmed the stability of key signal parameters, including integrity, carrier frequency and modulation depth. These results validate the feasibility and superiority of the digital LF time code generation technology proposed in this study, providing a valuable reference for the development of next-generation timing equipment. Full article

This paper presents a low-power data acquisition (DAQ) chip tailored for impulsive charge sensing, featuring a comparator-gated dynamic acquisition (CG-DAQ) architecture. A dynamic comparator triggers both the gain stage and a 12-bit successive-approximation register (SAR) analog-to-digital converter (ADC) through a shared timing path, enabling event-driven amplification and digitization. Programmable conversion gain ranging from 5 to 40 mV/pC is achieved by switching the sampling capacitance. Fabricated in TSMC 65 nm CMOS, the chip detects input charges from 0.01 to 36 pC, supports a signal bandwidth of 10 kHz to 100 kHz, and enables sampling rates up to 1 MS/s. It achieves an input-referred noise of 5.5 fC_rms and a peak signal-to-noise ratio (SNR) of 67 dB, all within a 54 μW power envelope and a compact 0.03 mm² core area. The proposed architecture facilitates accurate and energy-efficient charge-domain sensing for capacitive and piezoelectric sensor applications. Full article

This paper proposes a dual-mode CMOS analog front-end (AFE) circuit for short-wave infrared (SWIR) image sensors, which integrates a hybrid readout circuit (ROIC) and a 12-bit two-step single-slope analog-to-digital converter (TS-SS ADC). The ROIC dynamically switches between buffered-direct-injection (BDI) and direct-injection (DI) modes, thus balancing injection efficiency against power consumption. While the DI structure offers simplicity and low power, it suffers from unstable biasing and reduced injection efficiency under high background currents. Conversely, the BDI structure enhances injection efficiency and bias stability via an input buffer but incurs higher power consumption. To address this trade-off, a dual-mode injection architecture with mode-switching transistors is implemented. Mode selection is executed in-pixel via a low-leakage transmission gate and coordinated by the column timing controller, enabling low-current pixels to operate in low-noise BDI mode, whereas high-current pixels revert to the low-power DI mode. The TS-SS ADC employs a four-terminal comparator and dynamic reference voltage compensation to mitigate charge leakage and offset, which improves signal-to-noise ratio (SNR) and linearity. The prototype occupies 2.1 mm × 2.88 mm in a 0.18 µm CMOS process and serves a 64 × 64 array. The AFE achieves a dynamic range of 75.58 dB, noise of 249.42 μV, and 81.04 mW power consumption. Full article

As the primary electronic payload of laser interferometry system for space gravitational wave detection, the core function of the phasemeter is ultra-high precision phase measurement. According to the principle of laser heterodyne interferometry and the requirement of 1 pm ranging accuracy of the phasemeter, the phase measurement noise should reach 2π μrad/Hz^1/2@(0.1 mHz–1 Hz). The heterodyne interference signal first passes through the quadrant photoelectric detector (QPD) to achieve photoelectric conversion, then passes through the analog-to-digital converter (ADC) to achieve analog and digital conversion, and finally passes through the digital phase-locked loop (DPLL) for phase locking. The sampling timing jitter of the heterodyne interference signal caused by the ADC is the main noise affecting the phase measurement performance and must be suppressed. This paper proposes a sampling timing jitter noise suppression system (STJNSS), which can set system parameters for high-frequency signals used for inter-satellite clock noise transmission, the system clock of the phasemeter, and the pilot frequency for suppressing ADC sampling timing jitter noise, meeting the needs of the current major space gravitational wave detection plans. The experimental results after the integration of SJNSS and the phase meter show that the phase measurement noise of the heterodyne interferometer signal reaches 2π μrad/Hz^1/2@(0.1 mHz–1 Hz), which meets the requirements of space gravitational wave missions. Full article

Modern radar systems frequently encounter constraints on bandwidth, transmission speed, and resolution, particularly within complex electromagnetic settings. Microwave photonics (MWP) provides solutions through the integration of photonic elements to improve radar’s functionalities. This review paper examines the question of how to improve radar performance by using MWP-based radar components for signal transmission, local oscillator signal generation, radar waveforming, optical beamforming networks, mixing, filtering, co-site interference suppression, real-time Fourier transformation, and analog-to-digital conversion. MWP radar systems achieve wider bandwidths, greater resistance to electromagnetic interference, and reduced phase noise, size, weight, and power consumption. Consequently, the integration of MWP into radar systems has the potential to increase the accuracy of these systems. Full article

This paper presents an ultrasonic driving and detection system based on a CMUT array using MEMS technology. Among them, the core component CMUT array is composed of 8 × 8 CMUT array elements, and each CMUT array element contains 6 × 6 CMUT units. The collapse voltage of a single CMUT unit obtained through finite element analysis is 95.91 V, and the resonant frequency is 3.16 MHz. The driving section achieves 64-channel synchronous driving, with key parameters including an adjustable excitation signal frequency ranging from 10 kHz to 5.71 MHz, a delay precision of up to 1 ns, and an excitation duration of eight pulse cycles. For the echo reception, a two-stage amplification circuit for high-frequency weak echoes with 32 channels was designed, achieving a gain of 113.72 dB and −3 dB bandwidth of 3.89 MHz. Simultaneously, a 32-channel analog-to-digital conversion based on a self-calibration algorithm was implemented, with a sampling rate of 50 Mbps and a data width of 10 bits. Finally, the experimental results confirm the successful implementation of the driving system’s designed functions, yielding a center frequency of 1.4995 MHz and a relative bandwidth of 127.9%@−6 dB for the CMUT operating in silicone oil. This paper successfully conducted the transmit–receive integrated experiment of the CMUT and applied Butterworth filtering to the echo data, resulting in high-quality ultrasonic echo signals that validate the applicability of the designed CMUT-based system for ultrasonic imaging. Full article

We propose a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) that performs edge mask computation and detection during the analog-to-digital (A/D) conversion process to output 1-bit edge images. By utilizing the characteristics of the edge that can obtain a 1-bit image, the edge mask and thresholding operations are performed simultaneously during the A/D conversion process, thereby reducing memory capacity along with a high number of frames per second (FPS). Additionally, by implementing a 1-bit analog-to-digital converter (ADC) instead of a high-resolution ADC and counter through the 1-bit edge data obtained from the edge mask operation, both static and dynamic power consumption are reduced. The proposed CIS, fabricated with a one-poly six-metal CIS process with a 4T-active pixel sensor, has a core area of 2.546 mm $\times$ 1.923 mm in a chip area of 2.558 mm × 4.3 mm. The total power consumption is 1.52 mW at 23 FPS, with power supplies of 2.8 V and 1.5 V for the analog domain and 1.5 V for the digital domain. Full article

As wireless communication systems continue to demand higher data transmission rates, the need for analog-to-digital converters (ADCs) with a higher sampling rate becomes increasingly critical. However, traditional successive approximation register (SAR) ADCs operating at 1 bit/cycle often face speed limitations due to the fixed bit intervals and comparator regeneration delays, which constrain their scalability in advanced technology nodes. To address these challenges, this paper presents a high-speed 8-bit single-channel SAR ADC featuring a novel delay generation circuit that enables tailored bit intervals (TBIs) to reduce conversion latency. A split capacitive digital-to-analog converter (CDAC) is employed to suppress input common-mode voltage shifts, while inverted dynamic latch pairs and early capacitor reset techniques are introduced to improve conversion speed. The proposed ADC is implemented in a 16 nm CMOS process, occupying only 0.0012 mm². Post-layout simulations across extreme process and temperature corners validate the robustness of the design. The TBI-ADC achieves an effective number of bits (ENOB) of 7.20 bits at Typical–Typical (TT) 25 °C with a power consumption of 6.94 mW. Furthermore, it reaches a sampling rate of 1.6 GS/s at Fast–Fast (FF) −40 °C, representing a 33% improvement over the fastest previously reported single-channel, 1 bit/cycle, 8-bit SAR ADC. Full article

This paper presents a successive approximation register (SAR) and incremental sigma-delta modulator (ISDM) hybrid analog-to-digital converter (ADC) that operated at a minimum voltage supply of 0.575 V. A thorough analysis of the non-linearities caused by PVT variations and common-mode voltage (VCM) shifts in the ISDM stage is presented. The ADC employs an improved high-precision double-bootstrapped switch, and the synchronous clock is also double-bootstrapped to work under the low supply voltage. A modified merged capacitor switching (MCS) approach is presented to maintain a stable VCM at the differential input. The chip was fabricated using a 0.18 µm CMOS process, with a core area of 0.21 mm². It consumed only 0.42 µW at a 0.6 V supply and a sampling rate of 10 kS/s, which achieved an effective number of bits (ENOB) of 11.03. The resulting figure of merit (FOM_W) was 20.05 fJ/conversion-step, which is the lowest reported for ADCs of this architecture in a 0.18 µm process. Full article

Digital Imaging and Communication in Medicine (DICOM) is a standard format for storing medical images, which are typically represented in higher bit depths (10–16 bits), enabling detailed representation but exceeding the display capabilities of standard displays and human visual perception. To address this, DICOM images are often accompanied by windowing parameters, analogous to tone mapping in High-Dynamic-Range image processing, which compress the intensity range to enhance diagnostically relevant regions. This study evaluates traditional histogram-based methods and explores the potential of deep learning for predicting window parameters in radiographs where such information is missing. A range of architectures, including MobileNetV3Small, VGG16, ResNet50, and ViT-B/16, were trained on high-bit-depth computed radiography images using various combinations of loss functions, including structural similarity (SSIM), perceptual loss (LPIPS), and an edge preservation loss. Models were evaluated based on multiple criteria, including pixel entropy preservation, Hellinger distance of pixel value distributions, and peak-signal-to-noise ratio after 8-bit conversion. The tested approaches were further validated on the publicly available GRAZPEDWRI-DX dataset. Although histogram-based methods showed satisfactory performance, especially scaling through identifying the peaks in the pixel value histogram, deep learning-based methods were better at selectively preserving clinically relevant image areas while removing background noise. Full article

Digital pulse-width modulation (DPWM)-based controls are characterized by a non-negligible phase delay due to analog-to-digital (ADC) conversion, sampling time, carrier shape, and algorithm computation time. These delays degrade the performance in closed-loop systems, where the bandwidth must be reduced to avoid instability issues due to the reduced closed-loop phase margin. To mitigate these delays, approaches such as utilizing low-latency ADCs or increasing the sampling frequency have been employed. However, these methods are often costly and do not address the fundamental delay issues inherent to DPWMs. In this paper, a novel zero phase-delay DPWM architecture is proposed. This enhanced architecture seamlessly integrates pulse width and frequency modulation to create a programmable derivative action, capable of effectively recovering the DPWM delay. The proposed architecture employs a reliable and straightforward organization, suitable for implementation in commercial field programmable gate array (FPGA). Furthermore, this architecture inherently generates a trigger signal that can be used in numerous power electronic applications to capture the average value in piecewise linear inductor currents. The validity of the proposed architecture is substantiated through simulations and experimental tests. The final implementation is shared in an open-source resource. Full article

In this work, an energy-efficient noise-shaping (NS) successive-approximation (SAR) capacitance-to-digital converter (CDC) is proposed. The interface is based on a direct-comparison technique, in which the sensor capacitance is compared directly to an on-chip binary weighted capacitive digital-to-analog converter (DAC). To implement NS, a 2nd order feed-forward loop filter processes the extracted residue at the end of each conversion cycle. Employing NS to achieve the target resolution leads to a small capacitive DAC and hence a small Si-area compared to the conventional SAR approach that would require a capacitive DAC with the same resolution as the overall CDC resolution. The proposed capacitive NS SAR sensor interface is designed and implemented in 130 nm CMOS technology for a 4 pF dynamic range and achieves an effective number of bits (ENOB) of 12.0 bits with a measurement time of 2.5 ms. The CDC dissipates 1.0 $\mathsf{\mu }$A from a 0.8 V supply resulting in a figure of merit (FoM) of 488 fJ/conversion-step. Full article

This paper presents a low-power photoplethysmography (PPG) readout system designed for wearable health monitoring. The system employs a differential current mirror (DCM) to convert single-ended PPG currents into differential voltages, inherently suppressing DC components. A wide common-mode input range (WCMIR) SAR ADC processes the differential signals, ensuring accurate analog-to-digital conversion. The DCM eliminates the need for DC cancelation loops, simplifying the design and reducing power consumption. Implemented in a 0.18 µm CMOS process, the system occupies only 0.30 mm², making it suitable for multi-channel applications. The system achieves over 60 dB DC dynamic range and consumes only 9.6 µW, demonstrating its efficiency for portable devices. The simulation results validate its ability to process PPG signals across various conditions, offering a scalable solution for advanced biomedical sensing platforms. Full article

Reliable acoustic coupling in a non-handheld mode and reducing the form factor of electronics are specific challenges in making ultrasound wearable. Applications relying on a large field of view (such as tracking of large muscles) induce a need for a large element count to achieve high image quality. In our work, we developed a 256-element linear array for imaging of abdominal muscles with four integrated custom-developed 8:32 multiplexer Integrated Circuits (ICs), allowing the array to be driven by our compact 32 ch electronics. The system is optimized for flexible use in R&D applications and allows adjustable transmit voltages (up to +/−100 V), arbitrary delay patterns, and 12-bit analog-to-digital conversion (ADC) with up to 50 MSPS and wireless (21.6 MBit/s) or USB link. Image metrics (SLL, FWHM) were very similar to a fully populated array driven with a 256 ch system. The contrast allowed imaging of lesions down to 7 cm in the phantom. In a first in-vivo study, we demonstrated reliable acoustic contact even during exercise and were able to visualize deep abdominal muscles such as the TrA. In combination with a muscle tracking algorithm, the change of thickness of the TrA during SSE could be monitored, demonstrating the potential of the approach as biofeedback for physiotherapy training. Full article

Based on the mobility requirements of electric vehicles, four-wheel drive (4WD) can significantly enhance driving capability and increase operational flexibility in handling. If the output of different drive motors can be effectively controlled, energy losses during the distribution process can be reduced, thereby greatly improving overall efficiency. This study presents a simulation platform for an electric vehicle with four motors as power sources. This platform also consists of the driving cycle, driver, lithium-ion battery, vehicle dynamics, and energy management system models. Two rapid-prototyping controllers integrated with the required circuit to process analog-to-digital signal conversion for input and output are utilized to carry out a hardware-in-the-loop (HIL) simulation. The driving cycle, called NEDC (New European Driving Cycle), and FTP-75 (Federal Test Procedure 75) are used for evaluating the performance characteristics and response relationship among subsystems. A control strategy, called ECMS (Equivalent Consumption Minimization Strategy), is simulated and compared with the four-wheel average torque mode. The ECMS method considers different demanded powers and motor speeds, evaluating various drive motor power distribution combinations to search for motor power consumption and find the minimum value. As a result, it can identify the global optimal solution. Simulation results indicate that, compared to the average torque mode and rule-based control, in the pure simulation environment and HIL simulation during the UDDS driving cycle, the maximum improvement rates for pure electric energy efficiency for the 45 kW and 95 kW power systems are 6.1% and 6.0%, respectively. In the HIL simulation during the FTP-75 driving cycle, the maximum improvement rates for pure electric energy efficiency for the 45 kW and 95 kW power systems are 5.1% and 4.8%, respectively. Full article