Search Results (3,118)

The excellent mechanical properties of AISI 201 make it well-suited for applications in industrial components, transportation, and household appliances. However, during machining, this material generates high cutting forces and temperatures, leading to rapid tool wear and high costs. To address this issue, micro-grooves were designed on the rake face in areas prone to thermal and mechanical stress concentration. Through machining experiments focusing on workpiece surface quality, it was found that micro-grooved tools produced superior surface quality, specifically manifested in lower surface roughness, reduced work hardening, and shallower hardened layer depth. Experiments demonstrate that under identical conditions, increasing the cutting speed with tool M reduces the workpiece surface roughness by 0.096 μm to 0.236 μm compared to tool O. Under identical conditions, increasing the feed rate with tool M reduces the workpiece surface roughness by 0.070 μm to 0.236 μm compared to tool O. As cutting speed varies, the absolute surface hardness of workpieces machined by tool M decreases by approximately 39.85 HV, representing a hardness reduction of 14.5%. As feed rate varies, the surface hardness of workpieces machined with tool M is suppressed to a level 10.2%–14.2% lower than that of tool O. As cutting depth varies, the surface hardness of workpieces machined with tool M is suppressed to a level 10.0%–14.7% lower than that of tool O. Additionally, micro-grooved tools demonstrated superior chip curling and breaking performance. This tool design approach, optimized for tool durability and workpiece surface quality, establishes a research foundation for tool design targeting difficult-to-machine materials. Full article

This article explores the concept of low-level modeling of networks-on-chip (NoCs). A method for reducing the low-level NoC model by replacing the real IP blocks with a data packet generator module is proposed. This method is implemented in the low-level NoC modeling ECAD tool HDLNoCGen. This makes it possible to significantly increase the maximum number of nodes in the simulated NoC, as well as speed up the modeling and investigate the resource costs for network synthesis. A universal interface that can be used to connect new components to the network is also described. This interface has two main benefits: it reduces connection resource costs by eliminating the need to modify the connected component and shortens the time required to configure the connection interface itself. The proposed methodology of low-level NoC modeling is shown to be effective in analyzing the operation of routing algorithms of the NoC communication subsystem based on various topologies. Full article

Background: Facing global wheat production pressures such as environmental degradation and reduced cultivated land, breeding innovation is urgent to boost yields. Genomic selection (GS) is a useful wheat breeding technology to make the breeding process more efficient, increasing the genetic gain per unit time and cost. Precise genomic estimated breeding value (GEBV) via genome-wide markers is usually hampered by high-dimensional genomic data. Methods: To address this, we propose GRE, a framework combining genome-wide association study (GWAS)’s biological significance and random forest (RF)’s prediction efficiency for an explainable machine learning GS model. First, GRE identifies significant SNPs affecting wheat yield traits by comparison of the constructed 24 SNP subsets (intersection/union) selected by leveraging GWAS and RF, to analyze the marker scale’s impact. Furthermore, GRE compares six GS algorithms (GBLUP and five machine learning models), evaluating performance via prediction accuracy (Pearson correlation coefficient, PCC) and error. Additionally, GRE leverages Shapley additive explanations (SHAP) explainable techniques to overcome traditional GS models’ “black box” limitation, enabling cross-scale quantitative analysis and revealing how significant SNPs affect yield traits. Results: Results show that XGBoost and ElasticNet perform best in the union (383 SNPs) of GWAS and RF’s TOP 200 SNPs, with high accuracy (PCC > 0.864) and stability (standard deviation, SD < 0.005), and the significant SNPs identified by XGBoost are precisely explained by their main and interaction effects on wheat yield by SHAP. Conclusions: This study provides tool support for intelligent breeding chip design, important trait gene mining, and GS technology field transformation, aiding global agricultural sustainable productivity. Full article

Recently, with the rapid development of underwater resource exploration and underwater activities, underwater acoustic (UA) target recognition has become crucial in marine resource exploration. However, traditional underwater acoustic recognition systems face challenges such as low energy efficiency, poor accuracy, and slow response times. Systems for UA target recognition using deep learning networks have garnered widespread attention. Convolutional neural network (CNN) consumes significant computational resources and energy during convolution operations, which exacerbates the issues of energy consumption and complicates edge deployment. This paper explores a high-energy-efficiency UA target recognition system. Based on the DenseNet CNN, the system uses fine-grained pruning for sparsification and sparse convolution computations. The UA target recognition CNN was deployed on FPGAs and chips to achieve low-power recognition. Using the noise-disturbed ShipsEar dataset, the system reaches a recognition accuracy of 98.73% at 0 dB signal-to-noise ratio (SNR). After 50% fine-grained pruning, the accuracy is 96.11%. The circuit prototype on FPGA shows that the circuit achieves an accuracy of 95% at 0 dB SNR. This work implements the circuit design and layout of the UA target recognition chip based on a 65 nm CMOS process. DC synthesis results show that the power consumption is 90.82 mW, and the single-target recognition time is 7.81 ns. Full article

This work presents the design of a transparent Fresnel-zone lens antenna fabricated from Polydimethylsiloxane, also known as PDMS or dimethicone, a polymer widely used for manufacturing and prototyping microfluidic chips. The antenna operates in the $K_u$ band at 15 GHz. Specifically, a 3D-printed polylactic acid (PLA) mold is created and filled with PDMS to obtain the lens structure. The PLA mold can be used multiple times to produce different lens prototypes. An antenna prototype has been designed, fabricated, and assessed numerically and experimentally, demonstrating the capabilities and potential of the proposed design and production methodology. Full article

AISI 304 stainless steel is widely used in the equipment manufacturing industry due to its excellent corrosion resistance. However, its high toughness and plasticity lead to severe tool wear during machining, significantly shortening the tool’s life. To mitigate tool wear, this study designed and fabricated a novel micro-groove structure on the tool’s rake face, aiming to reduce friction and thermal stress. The performance of the micro-groove tool was evaluated through cutting simulations and durability tests. Results demonstrate that this micro-groove structure effectively reduces cutting forces, suppresses tool wear, and improves chip control and heat dissipation. Full article

We present the design and analysis of three CMOS 4-way power splitters operating in the K/Ka-band (18–27 GHz/27–40 GHz) for low Earth orbit (LEO) satellite communications and 26.5–29.5/37–40 GHz 5G radio applications. The first power splitter (PS1) consists of a two-way power splitter using circular double-helical transmission lines (DH-TLs) cascaded with two two-way power splitters using noninverting circular sole-helical coupled-TL (SH-CL). The second power splitter (PS2) consists of a two-way power splitter using circular DH-TLs cascaded with two two-way power splitters using inverting circular SH-CL. The third power splitter (PS3) consists of three two-way power splitters using DH-TLs. For each two-way power splitter, a parallel input capacitor is included to satisfy the requirement for two equivalent quarter-wavelength (λ/4) TLs, ensuring a low input reflection coefficient. λ/10-DH-TL-based-double-λ/4-TLs, λ/12-noninverting-SH-CL-based-double-λ/4-TLs, and λ/9-inverting-SH-CL-based-double-λ/4-TLs are utilized to attain compact chip size and low amplitude inequality (AI) and phase deviation (PD). Prominent results are attained. For instance, the chip size of PS1 is 0.057 mm². At 33 GHz, PS1 attains S₁₁ of −16 dB, S₂₂ of −21.2 dB, S₃₃ of −19.7 dB, S₂₃ of −15.3 dB, S₂₁ of −7.862 dB, S₃₁ of −7.803 dB, AI₂₃ of −0.059 dB, and PD₂₃ of 0.197°. The chip size of PS2 is 0.071 mm². At 33 GHz, PS2 attains S₁₁ of −13.5 dB, S₂₂ of −16.1 dB, S₃₃ of −16.7 dB, S₂₃ of −34.8 dB, S₂₁ of −8.1 dB, S₃₁ of −8.146 dB, AI₂₃ of 0.046 dB, and PD₂₃ of −0.581°. To the authors’ knowledge, the overall performance of PS1, PS2, and PS3 ranks among the best published in the literature for K- and Ka-band four-way power splitters. Full article

Random number generators play a critical role in ensuring information security, supporting encrypted communications, and preventing data leakage. However, the random number generators widely used in hardware are faced with potential threats such as environmental disturbances and fault injection attacks. Especially in automotive-grade environments, chips encounter threat scenarios involving multidimensional fault injection, which may lead to functional failures or malicious exploitation, endangering the security of the entire system. This paper focuses on a Counter Mode Deterministic Random Bit Generator (CTR-DRBG) based on the AES-128 algorithm and implements a hardware prototype system compliant with the NIST SP 800-22 standard on an FPGA platform. Centering on typical fault modes such as temperature disturbances, voltage glitches, electromagnetic interference, and bit flips, single-dimensional and multidimensional fault injection and simulated fault injection experiments were designed and conducted. The impact characteristics and sensitivities of electromagnetic faults, voltage faults, and temperature faults regarding the output sequences of random numbers were systematically evaluated. The experimental results show that this type of random number generator exhibits modular-level differential vulnerability under physical disturbances, especially in the data transmission processes of encryption paths and critical registers, which demonstrate higher sensitivity to flip-type faults. This research provides a feasible analysis framework and practical basis for the security assessment and fault-tolerant design of random number generators, possessing certain engineering applicability and theoretical reference value. Full article

Iris recognition is currently considered the most promising biometric method and has been applied in many fields. Current commercial and research systems typically use software solutions running on a dedicated computer, whose power consumption, size and price are considerably high. This paper presents a hardware-based embedded solution for real-time iris segmentation. From an algorithmic point of view, the system consists of two steps. The first employs a YOLOX trained to detect two classes: eyes and iris/pupil. Both classes intersect in the last of the classes and this is used to emphasise the detection of the iris/pupil class. The second stage uses a lightweight U-Net network to segment the iris, which is applied only on the locations provided by the first stage. Designed to work in an Iris At A Distance (IAAD) scenario, the system includes quality parameters to discard low-contrast or low-sharpness detections. The whole system has been integrated on one MultiProcessor System-on-Chip (MPSoC) using AMD’s Deep learning Processing Unit (DPU). This approach is capable of processing the more than 45 frames per second provided by a 16 Mpx CMOS digital image sensor. Experiments to determine the accuracy of the proposed system in terms of iris segmentation are performed on several publicly available databases with satisfactory results. Full article

We present a multifunctional, reconfigurable terahertz metasurface built from dual split-ring resonators combining photosensitive silicon and metallic elements. By hybridizing structural and Pancharatnam–Berry phase control, the device achieves spin-decoupled manipulation of circularly polarized wavefronts and an optical, light-intensity-driven reconfiguration mechanism. Using spatially encoded bifocal responses, we implement two two-input/two-output logic modules (OR-XOR and AND-NAND), and full-wave simulations verify the expected truth-table behaviors; additionally, a spin- and intensity-dependent hologram produces four distinct far-field images under different input conditions. At the selected working point (≈0.95 THz), the design exhibits a strong cross-polarization response (cross-polarized reflection amplitude > 0.7), demonstrating a viable route toward chip-scale, integrated terahertz logic and multifunctional imaging devices. Full article

This paper presents an advanced W-band bidirectional Power Amplifier–Low Noise Amplifier (PALNA) implemented using 130 nm SiGe BiCMOS technology. The proposed RF front-end eliminates the need for conventional transmit/receive (T/R) switches by employing a bidirectional architecture with a passive matching network. This approach minimizes area requirements and reduces signal losses. Post-layout simulation results demonstrate that the designed PALNA achieves a peak small-signal gain of 30 dB in Tx mode and 26 dB in Rx mode, with reverse isolation better than 40 dB. The 3 dB bandwidth spans from 94 to 106 GHz. In LNA mode, the design achieves a minimum noise figure of 6 dB at 100 GHz, remaining below 6.5 dB across the entire 3 dB bandwidth. In PA mode, the simulated saturated output power is 10.5 dBm, with a maximum power-added efficiency of 12% at 100 GHz. The chip size is 0.7 mm² including pads. It consumes 78 and 22 mW in the Tx and Rx modes, respectively. Full article

Respiratory infectious diseases, such as COVID-19, influenza, and tuberculosis, continue to impose a significant global health burden, underscoring the urgent demand for rapid, sensitive, and cost-effective diagnostic technologies. Integrated microfluidic platforms offer compelling advantages through miniaturization, automation, and high-throughput processing, enabling “sample-in, answer-out” workflows suitable for point-of-care applications. However, their clinical deployment faces challenges, including the complexity of sample matrices, low-abundance target detection, and the need for reliable multiplexing. The convergence of artificial intelligence (AI) with microfluidic systems has emerged as a transformative paradigm, addressing these limitations by optimizing chip design, automating sample pre-processing, enhancing signal interpretation, and enabling real-time feedback control. This critical review surveys AI-enabled strategies across each functional layer of respiratory pathogen diagnostics: from chip architecture and fluidic control to amplification analysis, signal prediction, and smartphone/IoT-linked decision support. We highlight key areas where AI offers measurable benefits over conventional methods. To transition from research prototypes to clinical tools, future systems must become more adaptive, data-efficient, and clinically insightful. Advances such as sensor-integrated chips, privacy-preserving machine learning, and multimodal data fusion will be essential to ensure robust performance and meaningful outputs across diverse scenarios. This review outlines recent progress, current limitations, and future directions. The rapid development of AI and microfluidics presents exciting opportunities for next-generation pathogen diagnostics, and we hope this work contributes to the advancement of intelligent, point-of-care testing (POCT) solutions. Full article

Semantic communication (SemCom), as a revolutionary paradigm for next-generation networks, shifts the focus from traditional bit-level transmission to the delivery of meaning and purpose. Grounded in the Data, Information, Knowledge, Wisdom, Purpose (DIKWP) model and its mapping framework, together with the relativity of understanding theory, the discussion systematically reviews advances in semantic-aware communication and personalized semantic security. By innovatively introducing the “Purpose” dimension atop the classical DIKW hierarchy and establishing interlayer feedback mechanisms, the DIKWP model enables purpose-driven, dynamic semantic processing, providing a theoretical foundation for both SemCom and personalized semantic security based on cognitive differences. A comparative analysis of existing SemCom architectures, personalized artificial intelligence (AI) systems, and secure communication mechanisms highlights the unique value of the DIKWP model. An integrated cognitive–conceptual–semantic network, combined with the principle of semantic relativity, supports the development of explainable, cognitively adaptive, and trustworthy communication systems. Practical implementation paths are explored, including DIKWP-based semantic chip design, white-box AI evaluation standards, and dynamic semantic protection frameworks, establishing theoretical links with emerging trends such as task-oriented communication and personalized foundation models. Embedding knowledge representation and cognitive context into communication protocols is shown to enhance efficiency, reliability, and security significantly. In addition, key research challenges in semantic alignment, cross-domain knowledge sharing, and formal semantic metrics are identified, while future research directions are outlined to guide the evolution of intelligent communication networks and provide a systematic reference for the advancement of the field. Full article

This paper presents a 90–100 GHz wideband digital phase shifter with a fine resolution of 5.625°, implemented in a 0.13 μm SiGe BiCMOS process. A switch-type architecture with six cascaded units, including a novel 180° cell based on a broadband coupler, enables full 0–360° phase coverage while improving phase accuracy, bandwidth, and process robustness. Post-layout simulations demonstrate an insertion loss below 15.5 dB, an RMS phase error under 2.3°, and an RMS amplitude error better than 0.9 dB across the 90–100 GHz band. The total chip area, including test pads, is 0.39 mm², making the design compact and well suited for high-density phased-array applications. Full article

This paper presents an innovative and low-cost approach to the dispensing of multiple liquids on a microfluidic chip with the aim of dispensing liquids in a controlled sequence. The project focused on the design and development of a microfluidic liquid dispensing system that is an integral part of the Lab-on-Chip (LOC). Liquids are often dispensed into LOCs through blisters, syringes, or electric microfluidic pumps, but these can be impractical for Point-of-Care (POC) settings, especially in remote areas. Additionally, incorrect volumes of biochemical reagents and the introduction of reagents outside the sequence can distort the results of the diagnosis. The process undertaken involved designing and 3D printing prototypes of the dispensing system, along with laser cutting and manufacturing the Polymethyl Methacrylate (PMMA) LOC devices intended for receiving the liquids. The proposed novel low-cost dispensing system uses manually operated actuators and cams to disperse metered fluids sequentially to minimise end-user errors at POC settings. Full article